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set-plls: Make script more robust

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The set-plls script was running too quickly, and could sometimes
finish before the PLLs were stable.  This patch fixes this problem,
in addition to making it clearer what the various settings do.

Signed-off-by: Sean Cross <xobs@kosagi.com>
This commit is contained in:
Sean Cross 2015-02-05 13:00:47 +08:00
parent ef9d60df5c
commit f7207812b4
1 changed files with 9 additions and 3 deletions
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12
scriptic/set-plls.S
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@ -6,24 +6,30 @@
sc_write16 0, 0, PLL_CTRL_CON2 sc_write16 0, 0, PLL_CTRL_CON2
sc_write16 0, 0, PLL_CTRL_CON3 sc_write16 0, 0, PLL_CTRL_CON3
sc_write16 0, 0, PLL_CTRL_CON0 sc_write16 0, 0, PLL_CTRL_CON0
sc_usleep 1 sc_usleep 3
sc_write16 1, 1, PLL_CTRL_UPLL_CON0 sc_write16 1, 1, PLL_CTRL_UPLL_CON0
/* Run EIM at 166 MHz */
sc_write16 0x1840, 0, PLL_CTRL_EPLL_CON0 sc_write16 0x1840, 0, PLL_CTRL_EPLL_CON0
sc_write16 0x100, 0x100, PLL_CTRL_EPLL_CON1 sc_write16 0x100, 0x100, PLL_CTRL_EPLL_CON1
sc_write16 1, 0, PLL_CTRL_MDDS_CON0 sc_write16 1, 0, PLL_CTRL_MDDS_CON0
sc_write16 1, 1, PLL_CTRL_MPLL_CON0 sc_write16 1, 1, PLL_CTRL_MPLL_CON0
sc_usleep 1 sc_usleep 1
sc_write16 1, 0, PLL_CTRL_EDDS_CON0 sc_write16 1, 0, PLL_CTRL_EDDS_CON0
sc_write16 1, 1, PLL_CTRL_EPLL_CON0 sc_write16 1, 1, PLL_CTRL_EPLL_CON0
sc_usleep 1 sc_usleep 70
sc_write16 0x4000, 0x4000, PLL_CTRL_CLK_CONDB sc_write16 0x4000, 0x4000, PLL_CTRL_CLK_CONDB
sc_usleep 1 sc_usleep 1
/* Enable digital frequency divider */
sc_write32 0x8048, 0, PLL_CTRL_CLK_CONDC sc_write32 0x8048, 0, PLL_CTRL_CLK_CONDC
/* Run the SPI clock at 104 MHz */
/* Run the SPI clock at 104 MHz and EMI at 166 MHz */
sc_write32 0xd002, 0, PLL_CTRL_CLK_CONDH sc_write32 0xd002, 0, PLL_CTRL_CLK_CONDH
sc_write32 0xb6a0, 0, PLL_CTRL_CLK_CONDC sc_write32 0xb6a0, 0, PLL_CTRL_CLK_CONDC
sc_end sc_end