#ifndef __FV_SPI_H__ #define __FV_SPI_H__ #define SPI_ADDR 0xa0140000 #define SPI_BLOCKMODE (SPI_ADDR + 0x00) #define SPI_BLOCKMODE_BUSY (1 << 0) #define SPI_BLOCKMODE_PREP (1 << 1) #define SPI_BLOCKMODE_TRIGGER (1 << 2) #define SPI_BLOCKMODE_ENABLE (1 << 3) #define SPI_BLOCKMODE_QUAD (1 << 4) #define SPI_BLOCKMODE_RELEASE (1 << 16) #define SPI_BLOCKMODE_CS (0 << 28) #define SPI_BLOCKMODE_CS0 (0 << 28) #define SPI_BLOCKMODE_CS1 (1 << 28) #define SPI_PIO_CS0 (SPI_ADDR + 0x04) #define SPI_PIO_QUAD_ENABLE (1 << 0) #define SPI_PIO_CMD1_WIDE (1 << 1) #define SPI_PIO_CMD2_ON (1 << 2) #define SPI_PIO_CMD2_WIDE (1 << 3) #define SPI_PIO_MODE (7 << 4) #define SPI_PIO_MODE_SLOW (0 << 4) #define SPI_PIO_MODE_FAST (1 << 4) #define SPI_PIO_MODE_QUAD (7 << 4) #define SPI_PIO_CMD1_DUMMY_CYCLES_0 (0 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_1 (1 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_2 (2 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_3 (3 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_4 (4 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_5 (5 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_6 (6 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_7 (7 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_8 (8 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_9 (9 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_10 (10 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_11 (11 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_12 (12 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_13 (13 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_14 (14 << 8) #define SPI_PIO_CMD1_DUMMY_CYCLES_15 (15 << 8) #define SPI_PIO_CMD2_DUMMY_CYCLES_0 (0 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_1 (1 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_2 (2 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_3 (3 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_4 (4 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_5 (5 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_6 (6 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_7 (7 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_8 (8 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_9 (9 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_10 (10 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_11 (11 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_12 (12 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_13 (13 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_14 (14 << 12) #define SPI_PIO_CMD2_DUMMY_CYCLES_15 (15 << 12) #define SPI_PIO_CMD1_SHIFT 16 #define SPI_PIO_CMD1_MASK (255 << 16) #define SPI_PIO_CMD2_SHIFT 24 #define SPI_PIO_CMD2_MASK (255 << 24) #define SPI_CTRL1 (SPI_ADDR + 0x08) #define SPI_CTRL1_LATCH_DELAY_0 (0 << 0) #define SPI_CTRL1_LATCH_DELAY_1 (1 << 0) #define SPI_CTRL1_LATCH_DELAY_2 (2 << 0) #define SPI_CTRL1_LATCH_DELAY_3 (3 << 0) #define SPI_CTRL1_BUS_IDLE (1 << 8) #define SPI_CTRL2 (SPI_ADDR + 0x0c) #define SPI_CTRL2_DDR_ENABLE (1 << 1) #define SPI_WRITE_COUNT (SPI_ADDR + 0x10) #define SPI_READ_COUNT (SPI_ADDR + 0x14) #define SPI_RESET (SPI_ADDR + 0x18) #define SPI_STATUS (SPI_ADDR + 0x1c) #define SPI_DELAY1 (SPI_ADDR + 0x20) #define SPI_DELAY2 (SPI_ADDR + 0x24) #define SPI_DELAY3 (SPI_ADDR + 0x28) #define SPI_DELAY4 (SPI_ADDR + 0x2c) #define SPI_DELAY5 (SPI_ADDR + 0x30) #define SPI_DELAY6 (SPI_ADDR + 0x34) #define SPI_DELAY7 (SPI_ADDR + 0x38) #define SPI_DELAY8 (SPI_ADDR + 0x3c) #define SPI_PIO_CS1 (SPI_ADDR + 0x40) /* Same map as SPI_PIO_CS0 */ #define SPI_CTRL3 (SPI_ADDR + 0x44) #define SPI_CTRL3_CHANNEL1_MASK (1 << 8) #define SPI_CTRL3_CHANNEL2_MASK (1 << 9) #define SPI_CTRL3_CHANNEL3_MASK (1 << 10) #define SPI_CTRL3_CHANNEL4_MASK (1 << 11) #define SPI_CTRL3_CHANNEL1_IDLE (1 << 12) #define SPI_CTRL3_CHANNEL2_IDLE (1 << 13) #define SPI_CTRL3_CHANNEL3_IDLE (1 << 14) #define SPI_CTRL3_CHANNEL4_IDLE (1 << 15) /* Dedicated buffer for SPI data */ #define SPI_DATA ((void *)(SPI_ADDR + 0x800)) #endif /* __FV_SPI_H__ */