78 lines
1.8 KiB
ArmAsm
78 lines
1.8 KiB
ArmAsm
#include "scriptic.h"
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#include "fernvale-emi.h"
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sc_new "enable_psram", 1, 0, 0
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/* Unclear what these do, but required on some chips */
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sc_write32 0x39320d61, 0, EMI_CTRL_CONB
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sc_write32 0x400, 0x400, EMI_CTRL_CONF
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sc_write32 0x401, 0, EMI_CTRL_GENA
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/* Remap EMI to 0x10000000, and SPI to 0x00000000 */
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sc_write32 2, 0, EMI_CTRL_REMAP
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/* Memory configuration */
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sc_read16 0, 0, 0x1ffffffe
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sc_usleep 50
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sc_read16 0, 0, 0x1ffffffe
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sc_usleep 50
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sc_write16 1, 0, 0x1ffffffe
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sc_usleep 50
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sc_write16 0x2b13, 0, 0x1ffffffe
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sc_usleep 50
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sc_read16 0, 0, 0x1ffffffe
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sc_usleep 50
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sc_read16 0, 0, 0x1ffffffe
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sc_usleep 50
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sc_write16 0, 0, 0x1ffffffe
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sc_usleep 50
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sc_write16 0x10, 0, 0x1ffffffe
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sc_usleep 50
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sc_write32 0xa0000000, 0, EMI_CTRL_CONB
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sc_write32 0xb2024419, 0, EMI_CTRL_CONF
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sc_usleep 50
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sc_write32 0x400, 0x400, EMI_CTRL_GENA
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/* Now map EMI back to 0x00000000, and SPI to 0x10000000 */
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sc_write32 3, 0, EMI_CTRL_REMAP
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sc_usleep 50
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sc_write32 0x20004001, 0, EMI_CTRL_RDCT
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sc_write32 0x5111, 0, EMI_CTRL_DSRAM
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sc_write32 0, 0, EMI_CTRL_IDLA
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sc_write32 0, 0, EMI_CTRL_IDLB
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sc_write32 0, 0, EMI_CTRL_IDLC
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sc_write32 0, 0, EMI_CTRL_IDLD
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sc_write32 0, 0, EMI_CTRL_IDLE
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sc_write32 0, 0, EMI_CTRL_ODLA
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sc_write32 0, 0, EMI_CTRL_ODLB
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sc_write32 0, 0, EMI_CTRL_ODLC
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sc_write32 0, 0, EMI_CTRL_ODLD
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sc_write32 0, 0, EMI_CTRL_ODLE
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sc_write32 0x00010001, 0, EMI_CTRL_IOA
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sc_write32 0x00010001, 0, EMI_CTRL_IOB
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sc_usleep 50
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/* Calibrate DQ in delay */
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sc_call calibrate_psram, 0
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sc_write32 0x300f0000, 0, EMI_CTRL_DLLV
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sc_read32 0x80, 0x80, EMI_CTRL_DLLV
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sc_write32 0x700f0000, 0, EMI_CTRL_DLLV
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sc_read32 0x80, 0x00, EMI_CTRL_DLLV
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sc_write32 0x100f0000, 0, EMI_CTRL_DLLV
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sc_write32 0x5426, 0, EMI_CTRL_ARBA
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sc_write32 0x5009, 0, EMI_CTRL_ARBB
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sc_write32 0x5051, 0, EMI_CTRL_ARBC
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sc_end
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