616 lines
26 KiB
C
616 lines
26 KiB
C
#ifndef __FV_GPIO_H__
|
|
#define __FV_GPIO_H__
|
|
|
|
/* Register names taken from MT6260 reference manual */
|
|
|
|
|
|
#define GPIO_CTRL_ADDR 0xa0020000
|
|
|
|
/* Direction control */
|
|
#define GPIO_CTRL_DIR0 (GPIO_CTRL_ADDR + 0x0000)
|
|
#define GPIO_CTRL_DIR1 (GPIO_CTRL_ADDR + 0x0010)
|
|
#define GPIO_CTRL_DIR2 (GPIO_CTRL_ADDR + 0x0020)
|
|
#define GPIO_CTRL_DIR3 (GPIO_CTRL_ADDR + 0x0030)
|
|
#define GPIO_CTRL_DIR4 (GPIO_CTRL_ADDR + 0x0040)
|
|
|
|
#define GPIO_CTRL_DIR_IN 0
|
|
#define GPIO_CTRL_DIR_OUT 1
|
|
|
|
/* Pull up/down enable */
|
|
#define GPIO_CTRL_PULLEN0 (GPIO_CTRL_ADDR + 0x0100)
|
|
#define GPIO_CTRL_PULLEN1 (GPIO_CTRL_ADDR + 0x0110)
|
|
#define GPIO_CTRL_PULLEN2 (GPIO_CTRL_ADDR + 0x0120)
|
|
#define GPIO_CTRL_PULLEN3 (GPIO_CTRL_ADDR + 0x0130)
|
|
#define GPIO_CTRL_PULLEN4 (GPIO_CTRL_ADDR + 0x0140)
|
|
|
|
#define GPIO_CTRL_PULLEN_DISABLE 1
|
|
#define GPIO_CTRL_PULLEN_ENABLE 1
|
|
|
|
/* Data inversion */
|
|
#define GPIO_CTRL_DINV0 (GPIO_CTRL_ADDR + 0x0200)
|
|
#define GPIO_CTRL_DINV1 (GPIO_CTRL_ADDR + 0x0210)
|
|
#define GPIO_CTRL_DINV2 (GPIO_CTRL_ADDR + 0x0220)
|
|
#define GPIO_CTRL_DINV3 (GPIO_CTRL_ADDR + 0x0230)
|
|
#define GPIO_CTRL_DINV4 (GPIO_CTRL_ADDR + 0x0240)
|
|
|
|
#define GPIO_CTRL_DINV_NORMAL 0
|
|
#define GPIO_CTRL_DINV_INVERT 1
|
|
|
|
/* Data output */
|
|
#define GPIO_CTRL_DOUT0 (GPIO_CTRL_ADDR + 0x0300)
|
|
#define GPIO_CTRL_DOUT1 (GPIO_CTRL_ADDR + 0x0310)
|
|
#define GPIO_CTRL_DOUT2 (GPIO_CTRL_ADDR + 0x0320)
|
|
#define GPIO_CTRL_DOUT3 (GPIO_CTRL_ADDR + 0x0330)
|
|
#define GPIO_CTRL_DOUT4 (GPIO_CTRL_ADDR + 0x0340)
|
|
|
|
#define GPIO_CTRL_DOUT_0 0
|
|
#define GPIO_CTRL_DOUT_1 0
|
|
|
|
/* Data input */
|
|
#define GPIO_CTRL_DIN0 (GPIO_CTRL_ADDR + 0x0400)
|
|
#define GPIO_CTRL_DIN1 (GPIO_CTRL_ADDR + 0x0410)
|
|
#define GPIO_CTRL_DIN2 (GPIO_CTRL_ADDR + 0x0420)
|
|
#define GPIO_CTRL_DIN3 (GPIO_CTRL_ADDR + 0x0430)
|
|
#define GPIO_CTRL_DIN4 (GPIO_CTRL_ADDR + 0x0440)
|
|
|
|
#define GPIO_CTRL_DIN_0 0
|
|
#define GPIO_CTRL_DIN_1 0
|
|
|
|
/* Select a pull up or pull down */
|
|
#define GPIO_CTRL_PULLSEL0 (GPIO_CTRL_ADDR + 0x0500)
|
|
#define GPIO_CTRL_PULLSEL1 (GPIO_CTRL_ADDR + 0x0510)
|
|
#define GPIO_CTRL_PULLSEL2 (GPIO_CTRL_ADDR + 0x0520)
|
|
#define GPIO_CTRL_PULLSEL3 (GPIO_CTRL_ADDR + 0x0530)
|
|
#define GPIO_CTRL_PULLSEL4 (GPIO_CTRL_ADDR + 0x0540)
|
|
|
|
#define GPIO_CTRL_PULLSEL_DOWN 0
|
|
#define GPIO_CTRL_PULLSEL_UP 1
|
|
|
|
/* Schmit trigger control */
|
|
#define GPIO_CTRL_SMT0 (GPIO_CTRL_ADDR + 0x0600)
|
|
#define GPIO_CTRL_SMT1 (GPIO_CTRL_ADDR + 0x0610)
|
|
#define GPIO_CTRL_SMT2 (GPIO_CTRL_ADDR + 0x0620)
|
|
|
|
/* Only available on certain GPIOs */
|
|
|
|
/* Slew rate control */
|
|
#define GPIO_CTRL_SR0 (GPIO_CTRL_ADDR + 0x0700)
|
|
#define GPIO_CTRL_SR1 (GPIO_CTRL_ADDR + 0x0710)
|
|
#define GPIO_CTRL_SR2 (GPIO_CTRL_ADDR + 0x0720)
|
|
#define GPIO_CTRL_SR3 (GPIO_CTRL_ADDR + 0x0730)
|
|
|
|
/* Only available on certain GPIOs */
|
|
|
|
/* Driving control */
|
|
#define GPIO_CTRL_DRV0 (GPIO_CTRL_ADDR + 0x0800)
|
|
#define GPIO_CTRL_DRV1 (GPIO_CTRL_ADDR + 0x0810)
|
|
#define GPIO_CTRL_DRV2 (GPIO_CTRL_ADDR + 0x0820)
|
|
|
|
/* Receive input buffer control */
|
|
#define GPIO_CTRL_IES0 (GPIO_CTRL_ADDR + 0x0900)
|
|
#define GPIO_CTRL_IES1 (GPIO_CTRL_ADDR + 0x0910)
|
|
#define GPIO_CTRL_IES2 (GPIO_CTRL_ADDR + 0x0920)
|
|
|
|
/* Enable pull up or pull down */
|
|
#define GPIO_CTRL_PUPDEN0 (GPIO_CTRL_ADDR + 0x0a00)
|
|
#define GPIO_CTRL_PUPDEN1 (GPIO_CTRL_ADDR + 0x0a10)
|
|
#define GPIO_CTRL_PUPDEN2 (GPIO_CTRL_ADDR + 0x0a20)
|
|
|
|
#define PULL_DOWN 0
|
|
#define PULL_UP 1
|
|
|
|
/* Resistence enable */
|
|
#define GPIO_CTRL_RESEN0_R0 (GPIO_CTRL_ADDR + 0x0b00)
|
|
#define GPIO_CTRL_RESEN1_R0 (GPIO_CTRL_ADDR + 0x0b10)
|
|
#define GPIO_CTRL_RESEN2_R0 (GPIO_CTRL_ADDR + 0x0b20)
|
|
#define GPIO_CTRL_RESEN0_R1 (GPIO_CTRL_ADDR + 0x0b30)
|
|
#define GPIO_CTRL_RESEN1_R1 (GPIO_CTRL_ADDR + 0x0b40)
|
|
#define GPIO_CTRL_RESEN2_R1 (GPIO_CTRL_ADDR + 0x0b50)
|
|
|
|
/* Write R0 into RESENx_R0, and R1 into RESENx_R1 */
|
|
|
|
/* KCOL 0-4 and KROW 0-4 */
|
|
#define PULL_HIZ_R0 0
|
|
#define PULL_HIZ_R1 0
|
|
#define PULL_75K_R0 0
|
|
#define PULL_75K_R1 1
|
|
|
|
/* KCOL 0-4 */
|
|
#define PULL_200K_R0 1
|
|
#define PULL_200K_R1 0
|
|
#define PULL_54K_R0 1
|
|
#define PULL_54K_R1 1
|
|
|
|
/* KROW 0-4 */
|
|
#define PULL_2K_R0 1
|
|
#define PULL_2K_R1 0
|
|
#define PULL_1p9K_R0 1
|
|
#define PULL_1p9K_R1 1
|
|
|
|
/* MSDC / KCOL6 / KROW 7 / KCOL7 */
|
|
#define PULL_NONE_R0 0
|
|
#define PULL_NONE_R1 0
|
|
#define PULL_47K_R0 0 /* R0 and R1 can also be swapped */
|
|
#define PULL_47K_R1 1
|
|
#define PULL_23p5K_R0 1
|
|
#define PULL_23p5K_R1 1
|
|
|
|
/* GPIO pull ups and pull downs have a weird mapping. -1 is for GPIOs
|
|
* that don't have a pull available.
|
|
*/
|
|
#define GPIO_PULL_MAPPING {\
|
|
-1, -1, -1, 16, 17, 12, 15, 14, \
|
|
21, 9, 19, 11, 10, 18, 20, 13, \
|
|
-1, -1, -1, -1, -1, -1, 22, -1, \
|
|
-1, 6, 8, 7, -1, -1, -1, -1, -1, \
|
|
-1, -1, -1, 27, 28, 24, 26, 25, \
|
|
23, -1, -1, -1, -1, -1, -1, -1, \
|
|
-1, -1, 36, 38, 37, 39, 40, 41, \
|
|
-1, -1, -1, -1, -1, -1, -1, -1, \
|
|
-1, -1, 29, 31, 35, 33, 34, 32, \
|
|
30 }
|
|
|
|
#define GPIO_CTRL_PULL_CTRL0_IO25 6
|
|
#define GPIO_CTRL_PULL_CTRL0_IO27 7
|
|
#define GPIO_CTRL_PULL_CTRL0_IO26 8
|
|
#define GPIO_CTRL_PULL_CTRL0_IO9 9
|
|
#define GPIO_CTRL_PULL_CTRL0_IO12 10
|
|
#define GPIO_CTRL_PULL_CTRL0_IO11 11
|
|
#define GPIO_CTRL_PULL_CTRL0_IO5 12
|
|
#define GPIO_CTRL_PULL_CTRL0_IO15 13
|
|
#define GPIO_CTRL_PULL_CTRL0_IO7 14
|
|
#define GPIO_CTRL_PULL_CTRL0_IO6 15
|
|
#define GPIO_CTRL_PULL_CTRL1_IO3 16
|
|
#define GPIO_CTRL_PULL_CTRL1_IO4 17
|
|
#define GPIO_CTRL_PULL_CTRL1_IO13 18
|
|
#define GPIO_CTRL_PULL_CTRL1_IO10 19
|
|
#define GPIO_CTRL_PULL_CTRL1_IO14 20
|
|
#define GPIO_CTRL_PULL_CTRL1_IO8 21
|
|
#define GPIO_CTRL_PULL_CTRL1_IO22 22
|
|
#define GPIO_CTRL_PULL_CTRL1_IO40 23
|
|
#define GPIO_CTRL_PULL_CTRL1_IO37 24
|
|
#define GPIO_CTRL_PULL_CTRL1_IO39 25
|
|
#define GPIO_CTRL_PULL_CTRL1_IO38 26
|
|
#define GPIO_CTRL_PULL_CTRL1_IO35 27
|
|
#define GPIO_CTRL_PULL_CTRL1_IO36 28
|
|
#define GPIO_CTRL_PULL_CTRL1_IO66 29
|
|
#define GPIO_CTRL_PULL_CTRL1_IO72 30
|
|
#define GPIO_CTRL_PULL_CTRL1_IO67 31
|
|
#define GPIO_CTRL_PULL_CTRL2_IO71 0
|
|
#define GPIO_CTRL_PULL_CTRL2_IO69 1
|
|
#define GPIO_CTRL_PULL_CTRL2_IO70 2
|
|
#define GPIO_CTRL_PULL_CTRL2_IO68 3
|
|
#define GPIO_CTRL_PULL_CTRL2_IO50 4
|
|
#define GPIO_CTRL_PULL_CTRL2_IO52 5
|
|
#define GPIO_CTRL_PULL_CTRL2_IO51 6
|
|
#define GPIO_CTRL_PULL_CTRL2_IO53 7
|
|
#define GPIO_CTRL_PULL_CTRL2_IO54 8
|
|
#define GPIO_CTRL_PULL_CTRL2_IO55 9
|
|
|
|
/* Mode control */
|
|
#define GPIO_CTRL_MODE0 (GPIO_CTRL_ADDR + 0x0c00)
|
|
#define GPIO_CTRL_MODE0_IO0_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE0_IO0_GPIO0 (0 << 0)
|
|
#define GPIO_CTRL_MODE0_IO0_EDICK (1 << 0)
|
|
#define GPIO_CTRL_MODE0_IO0_PWM (2 << 0)
|
|
#define GPIO_CTRL_MODE0_IO0_EINT0 (3 << 0)
|
|
#define GPIO_CTRL_MODE0_IO0_DEBUG0MON0 (7 << 0)
|
|
#define GPIO_CTRL_MODE0_IO1_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE0_IO1_GPIO1 (0 << 4)
|
|
#define GPIO_CTRL_MODE0_IO1_SCL (1 << 4)
|
|
#define GPIO_CTRL_MODE0_IO1_SPISCK0 (4 << 4)
|
|
#define GPIO_CTRL_MODE0_IO1_D1_ICK (5 << 4)
|
|
#define GPIO_CTRL_MODE0_IO1_DEBUG0MON1 (7 << 4)
|
|
#define GPIO_CTRL_MODE0_IO2_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE0_IO2_GPIO2 (0 << 8)
|
|
#define GPIO_CTRL_MODE0_IO2_SDA (1 << 8)
|
|
#define GPIO_CTRL_MODE0_IO2_SPICS0 (4 << 8)
|
|
#define GPIO_CTRL_MODE0_IO2_D1_IMS (5 << 8)
|
|
#define GPIO_CTRL_MODE0_IO2_DEBUG0MON2 (7 << 8)
|
|
#define GPIO_CTRL_MODE0_IO3_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE0_IO3_GPIO3 (0 << 12)
|
|
#define GPIO_CTRL_MODE0_IO3_MCDA1 (1 << 12)
|
|
#define GPIO_CTRL_MODE0_IO3_FMJTDI (4 << 12)
|
|
#define GPIO_CTRL_MODE0_IO3_JTDI (5 << 12)
|
|
#define GPIO_CTRL_MODE0_IO4_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE0_IO4_GPIO4 (0 << 16)
|
|
#define GPIO_CTRL_MODE0_IO4_MCDA2 (1 << 16)
|
|
#define GPIO_CTRL_MODE0_IO4_WIFITOBT (2 << 16)
|
|
#define GPIO_CTRL_MODE0_IO4_FMJTMS (4 << 16)
|
|
#define GPIO_CTRL_MODE0_IO4_JTMS (5 << 16)
|
|
#define GPIO_CTRL_MODE0_IO5_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE0_IO5_GPIO15 (0 << 20)
|
|
#define GPIO_CTRL_MODE0_IO5_KROW0 (1 << 20)
|
|
#define GPIO_CTRL_MODE0_IO5_EINT1 (3 << 20)
|
|
#define GPIO_CTRL_MODE0_IO5_FMJTDI (4 << 20)
|
|
#define GPIO_CTRL_MODE0_IO5_JTDI (5 << 20)
|
|
#define GPIO_CTRL_MODE0_IO5_BTJDI (6 << 20)
|
|
#define GPIO_CTRL_MODE0_IO5_DEBUG0MON12 (7 << 20)
|
|
#define GPIO_CTRL_MODE0_IO6_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE0_IO6_GPIO6 (0 << 24)
|
|
#define GPIO_CTRL_MODE0_IO6_KCOL3 (1 << 24)
|
|
#define GPIO_CTRL_MODE0_IO6_EDI2CK (2 << 24)
|
|
#define GPIO_CTRL_MODE0_IO6_FMJTMS (4 << 24)
|
|
#define GPIO_CTRL_MODE0_IO6_JTMS (5 << 24)
|
|
#define GPIO_CTRL_MODE0_IO6_BTJTMS (6 << 24)
|
|
#define GPIO_CTRL_MODE0_IO6_DEBUG0MON4 (7 << 24)
|
|
#define GPIO_CTRL_MODE0_IO7_MASK (0x7 << 28)
|
|
#define GPIO_CTRL_MODE0_IO7_GPIO7 (0 << 28)
|
|
#define GPIO_CTRL_MODE0_IO7_KCOL2 (1 << 28)
|
|
#define GPIO_CTRL_MODE0_IO7_FMJTCK (4 << 28)
|
|
#define GPIO_CTRL_MODE0_IO7_JTCK (5 << 28)
|
|
#define GPIO_CTRL_MODE0_IO7_BTJTCK (6 << 28)
|
|
#define GPIO_CTRL_MODE0_IO7_DEBUG0MON5 (7 << 28)
|
|
#define GPIO_CTRL_MODE1 (GPIO_CTRL_ADDR + 0x0c10)
|
|
#define GPIO_CTRL_MODE1_IO8_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE1_IO8_GPIO8 (0 << 0)
|
|
#define GPIO_CTRL_MODE1_IO8_KCOL1 (1 << 0)
|
|
#define GPIO_CTRL_MODE1_IO8_DEBUG0MON4 (7 << 0)
|
|
#define GPIO_CTRL_MODE1_IO9_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE1_IO9_GPIO9 (0 << 4)
|
|
#define GPIO_CTRL_MODE1_IO9_KCOL0 (1 << 4)
|
|
#define GPIO_CTRL_MODE1_IO9_DEBUG0MON7 (7 << 4)
|
|
#define GPIO_CTRL_MODE1_IO10_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE1_IO10_GPIO10 (0 << 8)
|
|
#define GPIO_CTRL_MODE1_IO10_MCDA3 (1 << 8)
|
|
#define GPIO_CTRL_MODE1_IO10_EINT2 (3 << 8)
|
|
#define GPIO_CTRL_MODE1_IO10_FMJTCK (4 << 8)
|
|
#define GPIO_CTRL_MODE1_IO10_JTCK (5 << 8)
|
|
#define GPIO_CTRL_MODE1_IO11_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE1_IO11_GPIO11 (0 << 12)
|
|
#define GPIO_CTRL_MODE1_IO11_KROW4 (1 << 12)
|
|
#define GPIO_CTRL_MODE1_IO11_EDI2WS (2 << 12)
|
|
#define GPIO_CTRL_MODE1_IO11_EINT3 (3 << 12)
|
|
#define GPIO_CTRL_MODE1_IO11_FMJTRSTB (4 << 12)
|
|
#define GPIO_CTRL_MODE1_IO11_JTRSTB (5 << 12)
|
|
#define GPIO_CTRL_MODE1_IO11_BTJTRSTB (6 << 12)
|
|
#define GPIO_CTRL_MODE1_IO11_DEBUG0MON8 (7 << 12)
|
|
#define GPIO_CTRL_MODE1_IO12_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE1_IO12_GPIO12 (0 << 16)
|
|
#define GPIO_CTRL_MODE1_IO12_KROW3 (1 << 16)
|
|
#define GPIO_CTRL_MODE1_IO12_EDI2DAT (2 << 16)
|
|
#define GPIO_CTRL_MODE1_IO12_FMJTDO (4 << 16)
|
|
#define GPIO_CTRL_MODE1_IO12_JTDO (5 << 16)
|
|
#define GPIO_CTRL_MODE1_IO12_BTJDO (6 << 16)
|
|
#define GPIO_CTRL_MODE1_IO12_DEBUG0MON9 (7 << 16)
|
|
#define GPIO_CTRL_MODE1_IO13_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE1_IO13_GPIO13 (0 << 20)
|
|
#define GPIO_CTRL_MODE1_IO13_KROW2 (1 << 20)
|
|
#define GPIO_CTRL_MODE1_IO13_JRTCK (5 << 20)
|
|
#define GPIO_CTRL_MODE1_IO13_BTDBGACKN (6 << 20)
|
|
#define GPIO_CTRL_MODE1_IO13_DEBUG0MON10 (7 << 20)
|
|
#define GPIO_CTRL_MODE1_IO14_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE1_IO14_GPIO14 (0 << 24)
|
|
#define GPIO_CTRL_MODE1_IO14_KROW1 (1 << 24)
|
|
#define GPIO_CTRL_MODE1_IO14_D1_IDA (5 << 24)
|
|
#define GPIO_CTRL_MODE1_IO14_BTDBGIN (6 << 24)
|
|
#define GPIO_CTRL_MODE1_IO14_DEBUG0MON11 (7 << 24)
|
|
#define GPIO_CTRL_MODE2 (GPIO_CTRL_ADDR + 0x0c20)
|
|
#define GPIO_CTRL_MODE2_IO16_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE2_IO16_GPIO16 (0 << 0)
|
|
#define GPIO_CTRL_MODE2_IO16_GPSFSYNC (1 << 0)
|
|
#define GPIO_CTRL_MODE2_IO17_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE2_IO17_GPIO17 (0 << 4)
|
|
#define GPIO_CTRL_MODE2_IO17_BPI_BUS5 (1 << 4)
|
|
#define GPIO_CTRL_MODE2_IO17_DEBUG0MON13 (7 << 4)
|
|
#define GPIO_CTRL_MODE2_IO18_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE2_IO18_GPIO18 (0 << 8)
|
|
#define GPIO_CTRL_MODE2_IO18_EDIWS (1 << 8)
|
|
#define GPIO_CTRL_MODE2_IO18_DEBUG0MON14 (7 << 8)
|
|
#define GPIO_CTRL_MODE2_IO19_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE2_IO19_GPIO19 (0 << 12)
|
|
#define GPIO_CTRL_MODE2_IO19_BPI_BUS4 (1 << 12)
|
|
#define GPIO_CTRL_MODE2_IO19_DEBUG0MON15 (7 << 12)
|
|
#define GPIO_CTRL_MODE2_IO20_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE2_IO20_GPIO20 (0 << 16)
|
|
#define GPIO_CTRL_MODE2_IO20_U2RXD (1 << 16)
|
|
#define GPIO_CTRL_MODE2_IO20_U1RTS (2 << 16)
|
|
#define GPIO_CTRL_MODE2_IO20_BTPRI (3 << 16)
|
|
#define GPIO_CTRL_MODE2_IO20_SPIMOSI0 (4 << 16)
|
|
#define GPIO_CTRL_MODE2_IO21_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE2_IO21_GPIO21 (0 << 20)
|
|
#define GPIO_CTRL_MODE2_IO21_U2TXD (1 << 20)
|
|
#define GPIO_CTRL_MODE2_IO21_U1CTS (2 << 20)
|
|
#define GPIO_CTRL_MODE2_IO21_CLKO0 (3 << 20)
|
|
#define GPIO_CTRL_MODE2_IO21_SPIMISO0 (4 << 20)
|
|
#define GPIO_CTRL_MODE2_IO22_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE2_IO22_GPIO22 (0 << 24)
|
|
#define GPIO_CTRL_MODE2_IO22_U1RXD (1 << 24)
|
|
#define GPIO_CTRL_MODE2_IO22_EINT4 (3 << 24)
|
|
#define GPIO_CTRL_MODE2_IO23_MASK (0x7 << 28)
|
|
#define GPIO_CTRL_MODE2_IO23_GPIO23 (0 << 28)
|
|
#define GPIO_CTRL_MODE2_IO23_U1TXD (1 << 28)
|
|
#define GPIO_CTRL_MODE3 (GPIO_CTRL_ADDR + 0x0c30)
|
|
#define GPIO_CTRL_MODE3_IO24_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE3_IO24_GPIO24 (0 << 0)
|
|
#define GPIO_CTRL_MODE3_IO24_EINT5 (1 << 0)
|
|
#define GPIO_CTRL_MODE3_IO25_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE3_IO25_GPIO25 (0 << 4)
|
|
#define GPIO_CTRL_MODE3_IO25_MCCK (1 << 4)
|
|
#define GPIO_CTRL_MODE3_IO25_JTRCK (5 << 4)
|
|
#define GPIO_CTRL_MODE3_IO25_DEBUG1MIN0 (6 << 4)
|
|
#define GPIO_CTRL_MODE3_IO25_DEBUG1MON0 (7 << 4)
|
|
#define GPIO_CTRL_MODE3_IO26_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE3_IO26_GPIO26 (0 << 8)
|
|
#define GPIO_CTRL_MODE3_IO26_MCDA0 (1 << 8)
|
|
#define GPIO_CTRL_MODE3_IO26_FMJTRSTB (4 << 8)
|
|
#define GPIO_CTRL_MODE3_IO26_JTRSTB (5 << 8)
|
|
#define GPIO_CTRL_MODE3_IO26_DEBUG1MIN1 (6 << 8)
|
|
#define GPIO_CTRL_MODE3_IO26_DEBUG1MON1 (7 << 8)
|
|
#define GPIO_CTRL_MODE3_IO27_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE3_IO27_GPIO27 (0 << 12)
|
|
#define GPIO_CTRL_MODE3_IO27_MCCM0 (1 << 12)
|
|
#define GPIO_CTRL_MODE3_IO27_FMJTDO (4 << 12)
|
|
#define GPIO_CTRL_MODE3_IO27_JTDO (5 << 12)
|
|
#define GPIO_CTRL_MODE3_IO27_DEBUG1MIN2 (6 << 12)
|
|
#define GPIO_CTRL_MODE3_IO27_DEBUG1MON2 (7 << 12)
|
|
#define GPIO_CTRL_MODE3_IO28_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE3_IO28_GPIO28 (0 << 16)
|
|
#define GPIO_CTRL_MODE3_IO28_NLD8 (1 << 16)
|
|
#define GPIO_CTRL_MODE3_IO28_CMMCLK (5 << 16)
|
|
#define GPIO_CTRL_MODE3_IO28_DEBUG1MIN3 (6 << 16)
|
|
#define GPIO_CTRL_MODE3_IO28_DEBUG1MON3 (7 << 16)
|
|
#define GPIO_CTRL_MODE3_IO29_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE3_IO29_GPIO29 (0 << 20)
|
|
#define GPIO_CTRL_MODE3_IO29_NLD7 (1 << 20)
|
|
#define GPIO_CTRL_MODE3_IO29_CMCSK (5 << 20)
|
|
#define GPIO_CTRL_MODE3_IO29_DEBUG1MIN4 (6 << 20)
|
|
#define GPIO_CTRL_MODE3_IO29_DEBUG1MON4 (7 << 20)
|
|
#define GPIO_CTRL_MODE3_IO30_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE3_IO30_GPIO30 (0 << 24)
|
|
#define GPIO_CTRL_MODE3_IO30_NLD6 (1 << 24)
|
|
#define GPIO_CTRL_MODE3_IO30_CMRST (5 << 24)
|
|
#define GPIO_CTRL_MODE3_IO30_DEBUG1MIN5 (6 << 24)
|
|
#define GPIO_CTRL_MODE3_IO30_DEBUG1MON5 (7 << 24)
|
|
#define GPIO_CTRL_MODE3_IO31_MASK (0x7 << 28)
|
|
#define GPIO_CTRL_MODE3_IO31_GPIO31 (0 << 28)
|
|
#define GPIO_CTRL_MODE3_IO31_NLD5 (1 << 28)
|
|
#define GPIO_CTRL_MODE3_IO31_CMCSD0 (5 << 28)
|
|
#define GPIO_CTRL_MODE3_IO31_DEBUG1MIN6 (6 << 28)
|
|
#define GPIO_CTRL_MODE3_IO31_DEBUG1MON6 (7 << 28)
|
|
#define GPIO_CTRL_MODE4 (GPIO_CTRL_ADDR + 0x0c40)
|
|
#define GPIO_CTRL_MODE4_IO32_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE4_IO32_GPIO32 (0 << 0)
|
|
#define GPIO_CTRL_MODE4_IO32_NLD4 (1 << 0)
|
|
#define GPIO_CTRL_MODE4_IO32_CMPDN (5 << 0)
|
|
#define GPIO_CTRL_MODE4_IO32_DEBUG1MON7 (7 << 0)
|
|
#define GPIO_CTRL_MODE4_IO33_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE4_IO33_GPIO33 (0 << 4)
|
|
#define GPIO_CTRL_MODE4_IO33_NLD3 (1 << 4)
|
|
#define GPIO_CTRL_MODE4_IO33_CMCSD1 (5 << 4)
|
|
#define GPIO_CTRL_MODE4_IO33_DEBUG1MON8 (7 << 4)
|
|
#define GPIO_CTRL_MODE4_IO34_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE4_IO34_GPIO34 (0 << 8)
|
|
#define GPIO_CTRL_MODE4_IO34_NLD2 (1 << 8)
|
|
#define GPIO_CTRL_MODE4_IO34_DEBUG1MON9 (7 << 8)
|
|
#define GPIO_CTRL_MODE4_IO35_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE4_IO35_GPIO35 (0 << 12)
|
|
#define GPIO_CTRL_MODE4_IO35_NLD1 (1 << 12)
|
|
#define GPIO_CTRL_MODE4_IO35_SFWP (3 << 12)
|
|
#define GPIO_CTRL_MODE4_IO35_BT_RGPIO0 (6 << 12)
|
|
#define GPIO_CTRL_MODE4_IO35_DEBUG1MON10 (7 << 12)
|
|
#define GPIO_CTRL_MODE4_IO36_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE4_IO36_GPIO36 (0 << 16)
|
|
#define GPIO_CTRL_MODE4_IO36_NLD0 (1 << 16)
|
|
#define GPIO_CTRL_MODE4_IO36_LSA0DA0 (2 << 16)
|
|
#define GPIO_CTRL_MODE4_IO36_SFCS0 (3 << 16)
|
|
#define GPIO_CTRL_MODE4_IO36_BT_RGPIO1 (6 << 16)
|
|
#define GPIO_CTRL_MODE4_IO36_DEBUG1MON11 (7 << 16)
|
|
#define GPIO_CTRL_MODE4_IO37_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE4_IO37_GPIO37 (0 << 20)
|
|
#define GPIO_CTRL_MODE4_IO37_LWRB (1 << 20)
|
|
#define GPIO_CTRL_MODE4_IO37_LSCK0 (2 << 20)
|
|
#define GPIO_CTRL_MODE4_IO37_SFCK (3 << 20)
|
|
#define GPIO_CTRL_MODE4_IO37_BT_RGPIO2 (6 << 20)
|
|
#define GPIO_CTRL_MODE4_IO37_DEBUG1MON12 (7 << 20)
|
|
#define GPIO_CTRL_MODE4_IO38_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE4_IO38_GPIO38 (0 << 24)
|
|
#define GPIO_CTRL_MODE4_IO38_LRDB (1 << 24)
|
|
#define GPIO_CTRL_MODE4_IO38_LSDA0 (2 << 24)
|
|
#define GPIO_CTRL_MODE4_IO38_SFIN (3 << 24)
|
|
#define GPIO_CTRL_MODE4_IO38_BT_RGPIO3 (6 << 24)
|
|
#define GPIO_CTRL_MODE4_IO38_DEBUG1MON13 (7 << 24)
|
|
#define GPIO_CTRL_MODE4_IO39_MASK (0x7 << 28)
|
|
#define GPIO_CTRL_MODE4_IO39_GPIO39 (0 << 28)
|
|
#define GPIO_CTRL_MODE4_IO39_LPA0 (1 << 28)
|
|
#define GPIO_CTRL_MODE4_IO39_LSDI0 (2 << 28)
|
|
#define GPIO_CTRL_MODE4_IO39_SFOUT (3 << 28)
|
|
#define GPIO_CTRL_MODE4_IO39_BT_RGPIO4 (6 << 28)
|
|
#define GPIO_CTRL_MODE4_IO39_DEBUG1MON14 (7 << 28)
|
|
#define GPIO_CTRL_MODE5 (GPIO_CTRL_ADDR + 0x0c50)
|
|
#define GPIO_CTRL_MODE5_IO40_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE5_IO40_GPIO40 (0 << 0)
|
|
#define GPIO_CTRL_MODE5_IO40_LPCE0B (1 << 0)
|
|
#define GPIO_CTRL_MODE5_IO40_LSCE0B0 (2 << 0)
|
|
#define GPIO_CTRL_MODE5_IO40_SFHOLD (3 << 0)
|
|
#define GPIO_CTRL_MODE5_IO40_BT_RGPIO5 (5 << 0)
|
|
#define GPIO_CTRL_MODE5_IO40_DEBUG1MON15 (6 << 0)
|
|
#define GPIO_CTRL_MODE5_IO40_DEBUG1MON3 (7 << 0)
|
|
#define GPIO_CTRL_MODE5_IO41_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE5_IO41_GPIO41 (0 << 4)
|
|
#define GPIO_CTRL_MODE5_IO41_LSCE1B (1 << 4)
|
|
#define GPIO_CTRL_MODE5_IO41_LPCE2B (2 << 4)
|
|
#define GPIO_CTRL_MODE5_IO41_SCL (3 << 4)
|
|
#define GPIO_CTRL_MODE5_IO42_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE5_IO42_GPIO42 (0 << 8)
|
|
#define GPIO_CTRL_MODE5_IO42_LPCE1B (1 << 8)
|
|
#define GPIO_CTRL_MODE5_IO42_LPTE1 (2 << 8)
|
|
#define GPIO_CTRL_MODE5_IO42_SDA (3 << 8)
|
|
#define GPIO_CTRL_MODE5_IO43_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE5_IO43_GPIO43 (0 << 12)
|
|
#define GPIO_CTRL_MODE5_IO43_LSRSTB (1 << 12)
|
|
#define GPIO_CTRL_MODE5_IO43_EGND37 (7 << 12)
|
|
#define GPIO_CTRL_MODE5_IO44_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE5_IO44_GPIO44 (0 << 16)
|
|
#define GPIO_CTRL_MODE5_IO44_WATCHDOG (1 << 16)
|
|
#define GPIO_CTRL_MODE5_IO44_LPCE2B (2 << 16)
|
|
#define GPIO_CTRL_MODE5_IO44_EINT6 (3 << 16)
|
|
#define GPIO_CTRL_MODE5_IO45_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE5_IO45_GPIO45 (0 << 20)
|
|
#define GPIO_CTRL_MODE5_IO45_LPTE0 (1 << 20)
|
|
#define GPIO_CTRL_MODE5_IO45_CLKO1 (3 << 20)
|
|
#define GPIO_CTRL_MODE5_IO46_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE5_IO46_GPIO46 (0 << 24)
|
|
#define GPIO_CTRL_MODE5_IO46_LPRSTB (1 << 24)
|
|
#define GPIO_CTRL_MODE5_IO46_LSRSTB (2 << 24)
|
|
#define GPIO_CTRL_MODE5_IO46_LPTE1 (4 << 24)
|
|
#define GPIO_CTRL_MODE5_IO46_LPCE3B (5 << 24)
|
|
#define GPIO_CTRL_MODE5_IO47_MASK (0x7 << 28)
|
|
#define GPIO_CTRL_MODE5_IO47_GPIO47 (0 << 28)
|
|
#define GPIO_CTRL_MODE5_IO47_CMDAT0 (1 << 28)
|
|
#define GPIO_CTRL_MODE5_IO47_CMCSD0 (2 << 28)
|
|
#define GPIO_CTRL_MODE5_IO47_U2RTS (3 << 28)
|
|
#define GPIO_CTRL_MODE5_IO47_FMJTDI (4 << 28)
|
|
#define GPIO_CTRL_MODE5_IO47_JTDI (5 << 28)
|
|
#define GPIO_CTRL_MODE5_IO47_BTJTDI (6 << 28)
|
|
#define GPIO_CTRL_MODE6 (GPIO_CTRL_ADDR + 0x0c60)
|
|
#define GPIO_CTRL_MODE6_IO48_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE6_IO48_GPIO48 (0 << 0)
|
|
#define GPIO_CTRL_MODE6_IO48_CMDAT1 (1 << 0)
|
|
#define GPIO_CTRL_MODE6_IO48_CMCSD1 (2 << 0)
|
|
#define GPIO_CTRL_MODE6_IO48_U2CTS (3 << 0)
|
|
#define GPIO_CTRL_MODE6_IO48_FMJTMS (4 << 0)
|
|
#define GPIO_CTRL_MODE6_IO48_JTMS (5 << 0)
|
|
#define GPIO_CTRL_MODE6_IO48_BTJTMS (6 << 0)
|
|
#define GPIO_CTRL_MODE6_IO49_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE6_IO49_GPIO49 (0 << 4)
|
|
#define GPIO_CTRL_MODE6_IO49_CMDAT2 (1 << 4)
|
|
#define GPIO_CTRL_MODE6_IO49_SCL (2 << 4)
|
|
#define GPIO_CTRL_MODE6_IO49_FMJTCK (4 << 4)
|
|
#define GPIO_CTRL_MODE6_IO49_JTCK (5 << 4)
|
|
#define GPIO_CTRL_MODE6_IO49_BTJTCK (6 << 4)
|
|
#define GPIO_CTRL_MODE6_IO50_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE6_IO50_GPIO50 (0 << 8)
|
|
#define GPIO_CTRL_MODE6_IO50_CMDAT3 (1 << 8)
|
|
#define GPIO_CTRL_MODE6_IO50_LSRSTB (2 << 8)
|
|
#define GPIO_CTRL_MODE6_IO50_MC2CM (3 << 8)
|
|
#define GPIO_CTRL_MODE6_IO50_DAICLK (4 << 8)
|
|
#define GPIO_CTRL_MODE6_IO50_JRTCK (5 << 8)
|
|
#define GPIO_CTRL_MODE6_IO50_BTDBGACKN (6 << 8)
|
|
#define GPIO_CTRL_MODE6_IO51_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE6_IO51_GPIO51 (0 << 12)
|
|
#define GPIO_CTRL_MODE6_IO51_CMDAT4 (1 << 12)
|
|
#define GPIO_CTRL_MODE6_IO51_LSA0DA1 (2 << 12)
|
|
#define GPIO_CTRL_MODE6_IO51_MC2DA0 (3 << 12)
|
|
#define GPIO_CTRL_MODE6_IO51_FMJTRSTB (4 << 12)
|
|
#define GPIO_CTRL_MODE6_IO51_JTRST_B (5 << 12)
|
|
#define GPIO_CTRL_MODE6_IO51_BTJTRSTB (6 << 12)
|
|
#define GPIO_CTRL_MODE6_IO52_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE6_IO52_GPIO52 (0 << 16)
|
|
#define GPIO_CTRL_MODE6_IO52_CMDAT5 (1 << 16)
|
|
#define GPIO_CTRL_MODE6_IO52_LSCK1 (2 << 16)
|
|
#define GPIO_CTRL_MODE6_IO52_MC2DA1 (3 << 16)
|
|
#define GPIO_CTRL_MODE6_IO52_FMJTDO (4 << 16)
|
|
#define GPIO_CTRL_MODE6_IO52_JTDO (5 << 16)
|
|
#define GPIO_CTRL_MODE6_IO52_BTJTDO (6 << 16)
|
|
#define GPIO_CTRL_MODE6_IO53_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE6_IO53_GPIO53 (0 << 20)
|
|
#define GPIO_CTRL_MODE6_IO53_CMDAT6 (1 << 20)
|
|
#define GPIO_CTRL_MODE6_IO53_LSDA1 (2 << 20)
|
|
#define GPIO_CTRL_MODE6_IO53_MC2DA2 (3 << 20)
|
|
#define GPIO_CTRL_MODE6_IO53_DAIPCMIN (4 << 20)
|
|
#define GPIO_CTRL_MODE6_IO53_BTDBGIN (6 << 20)
|
|
#define GPIO_CTRL_MODE6_IO54_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE6_IO54_GPIO54 (0 << 24)
|
|
#define GPIO_CTRL_MODE6_IO54_CMDAT7 (1 << 24)
|
|
#define GPIO_CTRL_MODE6_IO54_LSDI1 (2 << 24)
|
|
#define GPIO_CTRL_MODE6_IO54_MC2DA3 (3 << 24)
|
|
#define GPIO_CTRL_MODE6_IO54_DAIPCMOUT (4 << 24)
|
|
#define GPIO_CTRL_MODE6_IO54_DEBUG2MIN0 (6 << 24)
|
|
#define GPIO_CTRL_MODE6_IO54_DEBUG2MON0 (7 << 24)
|
|
#define GPIO_CTRL_MODE6_IO55_MASK (0x7 << 28)
|
|
#define GPIO_CTRL_MODE6_IO55_GPIO55 (0 << 28)
|
|
#define GPIO_CTRL_MODE6_IO55_CMHREF (1 << 28)
|
|
#define GPIO_CTRL_MODE6_IO55_LSCE0B1 (2 << 28)
|
|
#define GPIO_CTRL_MODE6_IO55_MC2CK (3 << 28)
|
|
#define GPIO_CTRL_MODE6_IO55_DAISYNC (4 << 28)
|
|
#define GPIO_CTRL_MODE6_IO55_DEBUG2MIN1 (6 << 28)
|
|
#define GPIO_CTRL_MODE6_IO55_DEBUG2MON1 (7 << 28)
|
|
#define GPIO_CTRL_MODE7 (GPIO_CTRL_ADDR + 0x0c70)
|
|
#define GPIO_CTRL_MODE7_IO56_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE7_IO56_GPIO56 (0 << 0)
|
|
#define GPIO_CTRL_MODE7_IO56_CMVREF (1 << 0)
|
|
#define GPIO_CTRL_MODE7_IO56_SDA (2 << 0)
|
|
#define GPIO_CTRL_MODE7_IO56_EINT7 (3 << 0)
|
|
#define GPIO_CTRL_MODE7_IO56_DAIRST (4 << 0)
|
|
#define GPIO_CTRL_MODE7_IO56_LPTE0 (5 << 0)
|
|
#define GPIO_CTRL_MODE7_IO56_DEBUG2MIN2 (6 << 0)
|
|
#define GPIO_CTRL_MODE7_IO56_DEBUG2MON2 (7 << 0)
|
|
#define GPIO_CTRL_MODE7_IO57_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE7_IO57_GPIO57 (0 << 4)
|
|
#define GPIO_CTRL_MODE7_IO57_CMPDN (1 << 4)
|
|
#define GPIO_CTRL_MODE7_IO57_DEBUG2MIN3 (6 << 4)
|
|
#define GPIO_CTRL_MODE7_IO57_DEBUG2MON3 (7 << 4)
|
|
#define GPIO_CTRL_MODE7_IO58_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE7_IO58_GPIO58 (0 << 8)
|
|
#define GPIO_CTRL_MODE7_IO58_CMMCLK (1 << 8)
|
|
#define GPIO_CTRL_MODE7_IO58_DEBUG2MIN4 (6 << 8)
|
|
#define GPIO_CTRL_MODE7_IO58_DEBUG2MON4 (7 << 8)
|
|
#define GPIO_CTRL_MODE7_IO59_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE7_IO59_GPIO59 (0 << 12)
|
|
#define GPIO_CTRL_MODE7_IO59_CMPCLK (1 << 12)
|
|
#define GPIO_CTRL_MODE7_IO59_CMCSK (2 << 12)
|
|
#define GPIO_CTRL_MODE7_IO59_DEBUG2MIN5 (6 << 12)
|
|
#define GPIO_CTRL_MODE7_IO59_DEBUG2MON5 (7 << 12)
|
|
#define GPIO_CTRL_MODE7_IO60_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE7_IO60_GPIO60 (0 << 16)
|
|
#define GPIO_CTRL_MODE7_IO60_CMRST (1 << 16)
|
|
#define GPIO_CTRL_MODE7_IO60_DEBUG2MIN6 (6 << 16)
|
|
#define GPIO_CTRL_MODE7_IO60_DEBUG2MON6 (7 << 16)
|
|
#define GPIO_CTRL_MODE7_IO61_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE7_IO61_GPIO61 (0 << 20)
|
|
#define GPIO_CTRL_MODE7_IO61_EDIDAT (1 << 20)
|
|
#define GPIO_CTRL_MODE7_IO61_PWM (2 << 20)
|
|
#define GPIO_CTRL_MODE7_IO61_EINT8 (3 << 20)
|
|
#define GPIO_CTRL_MODE7_IO62_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE7_IO62_GPIO62 (0 << 24)
|
|
#define GPIO_CTRL_MODE7_IO62_BPI_BU3 (1 << 24)
|
|
#define GPIO_CTRL_MODE7_IO63_MASK (0x7 << 28)
|
|
#define GPIO_CTRL_MODE7_IO63_GPIO63 (0 << 28)
|
|
#define GPIO_CTRL_MODE7_IO63_BPI_BUS2 (1 << 28)
|
|
#define GPIO_CTRL_MODE8 (GPIO_CTRL_ADDR + 0x0c80)
|
|
#define GPIO_CTRL_MODE8_IO64_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE8_IO64_GPIO64 (0 << 0)
|
|
#define GPIO_CTRL_MODE8_IO64_BPI_BUS1 (1 << 0)
|
|
#define GPIO_CTRL_MODE8_IO65_MASK (0x7 << 4)
|
|
#define GPIO_CTRL_MODE8_IO65_GPIO65 (0 << 4)
|
|
#define GPIO_CTRL_MODE8_IO65_BPI_BUS0 (1 << 4)
|
|
#define GPIO_CTRL_MODE8_IO66_MASK (0x7 << 8)
|
|
#define GPIO_CTRL_MODE8_IO66_GPIO66 (0 << 8)
|
|
#define GPIO_CTRL_MODE8_IO66_SFCS1 (1 << 8)
|
|
#define GPIO_CTRL_MODE8_IO67_MASK (0x7 << 12)
|
|
#define GPIO_CTRL_MODE8_IO67_GPIO67 (0 << 12)
|
|
#define GPIO_CTRL_MODE8_IO67_SFWP (1 << 12)
|
|
#define GPIO_CTRL_MODE8_IO67_MC2CK (2 << 12)
|
|
#define GPIO_CTRL_MODE8_IO68_MASK (0x7 << 16)
|
|
#define GPIO_CTRL_MODE8_IO68_GPIO68 (0 << 16)
|
|
#define GPIO_CTRL_MODE8_IO68_SFCS0 (1 << 16)
|
|
#define GPIO_CTRL_MODE8_IO68_MC2DA1 (2 << 16)
|
|
#define GPIO_CTRL_MODE8_IO69_MASK (0x7 << 20)
|
|
#define GPIO_CTRL_MODE8_IO69_GPIO69 (0 << 20)
|
|
#define GPIO_CTRL_MODE8_IO69_SFCK (1 << 20)
|
|
#define GPIO_CTRL_MODE8_IO69_MC2DA0 (2 << 20)
|
|
#define GPIO_CTRL_MODE8_IO70_MASK (0x7 << 24)
|
|
#define GPIO_CTRL_MODE8_IO70_GPIO70 (0 << 24)
|
|
#define GPIO_CTRL_MODE8_IO70_SFIN (1 << 24)
|
|
#define GPIO_CTRL_MODE8_IO70_MC2DA2 (2 << 24)
|
|
#define GPIO_CTRL_MODE8_IO71_MASK (0x7 << 28)
|
|
#define GPIO_CTRL_MODE8_IO71_GPIO71 (0 << 28)
|
|
#define GPIO_CTRL_MODE8_IO71_SFOUT (1 << 28)
|
|
#define GPIO_CTRL_MODE8_IO71_MC2CM (2 << 28)
|
|
#define GPIO_CTRL_MODE9 (GPIO_CTRL_ADDR + 0x0c90)
|
|
#define GPIO_CTRL_MODE9_IO72_MASK (0x7 << 0)
|
|
#define GPIO_CTRL_MODE9_IO72_GPIO72 (0 << 0)
|
|
#define GPIO_CTRL_MODE9_IO72_SFSHOLD (1 << 0)
|
|
#define GPIO_CTRL_MODE9_IO72_MC2DA3 (2 << 0)
|
|
#define GPIO_CTRL_MODE9_IO72_EGND68 (7 << 0)
|
|
|
|
/* Duty control (tx and rx) */
|
|
#define GPIO_CTRL_RDSEL (GPIO_CTRL_ADDR + 0x0d00)
|
|
#define GPIO_CTRL_TDSEL (GPIO_CTRL_ADDR + 0x0d10)
|
|
|
|
/* Clock output */
|
|
#define GPIO_CTRL_CLK_OUT0 (GPIO_CTRL_ADDR + 0x0e00)
|
|
#define GPIO_CTRL_CLK_OUT1 (GPIO_CTRL_ADDR + 0x0e10)
|
|
|
|
#endif /* __FV_GPIO_H__ */
|