f7207812b4
The set-plls script was running too quickly, and could sometimes finish before the PLLs were stable. This patch fixes this problem, in addition to making it clearer what the various settings do. Signed-off-by: Sean Cross <xobs@kosagi.com>
35 lines
810 B
ArmAsm
35 lines
810 B
ArmAsm
#include "scriptic.h"
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#include "fernvale-pll.h"
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sc_new "set_plls", 1, 0, 0
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sc_write16 0, 0, PLL_CTRL_CON2
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sc_write16 0, 0, PLL_CTRL_CON3
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sc_write16 0, 0, PLL_CTRL_CON0
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sc_usleep 3
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sc_write16 1, 1, PLL_CTRL_UPLL_CON0
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/* Run EIM at 166 MHz */
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sc_write16 0x1840, 0, PLL_CTRL_EPLL_CON0
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sc_write16 0x100, 0x100, PLL_CTRL_EPLL_CON1
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sc_write16 1, 0, PLL_CTRL_MDDS_CON0
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sc_write16 1, 1, PLL_CTRL_MPLL_CON0
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sc_usleep 1
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sc_write16 1, 0, PLL_CTRL_EDDS_CON0
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sc_write16 1, 1, PLL_CTRL_EPLL_CON0
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sc_usleep 70
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sc_write16 0x4000, 0x4000, PLL_CTRL_CLK_CONDB
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sc_usleep 1
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/* Enable digital frequency divider */
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sc_write32 0x8048, 0, PLL_CTRL_CLK_CONDC
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/* Run the SPI clock at 104 MHz and EMI at 166 MHz */
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sc_write32 0xd002, 0, PLL_CTRL_CLK_CONDH
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sc_write32 0xb6a0, 0, PLL_CTRL_CLK_CONDC
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sc_end
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