212 lines
8.2 KiB
ArmAsm
212 lines
8.2 KiB
ArmAsm
#define MODE_MASK 0x0000001f /* Bits 0-4: Mode bits */
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# define USR26_MODE 0x00000000 /* 26-bit User mode */
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# define FIQ26_MODE 0x00000001 /* 26-bit FIQ mode */
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# define IRQ26_MODE 0x00000002 /* 26-bit IRQ mode */
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# define SVC26_MODE 0x00000003 /* 26-bit Supervisor mode */
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# define MODE32_BIT 0x00000010 /* Bit 4: 32-bit mode */
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# define USR_MODE 0x00000010 /* 32-bit User mode */
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# define FIQ_MODE 0x00000011 /* 32-bit FIQ mode */
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# define IRQ_MODE 0x00000012 /* 32-bit IRQ mode */
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# define SVC_MODE 0x00000013 /* 32-bit Supervisor mode */
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# define ABT_MODE 0x00000017 /* 32-bit Abort mode */
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# define UND_MODE 0x0000001b /* 32-bit Undefined mode */
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# define SYSTEM_MODE 0x0000001f /* 32-bit System mode */
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#define PSR_T_BIT 0x00000020 /* Bit 5: Thumb state */
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#define PSR_F_BIT 0x00000040 /* Bit 6: FIQ disable */
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#define PSR_I_BIT 0x00000080 /* Bit 7: IRQ disable */
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/* Bits 8-23: Reserved */
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#define PSR_J_BIT 0x01000000 /* Bit 24: Jazelle state bit */
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/* Bits 25-26: Reserved */
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#define PSR_Q_BIT 0x08000000 /* Bit 27: Sticky overflow */
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#define PSR_V_BIT 0x10000000 /* Bit 28: Overflow */
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#define PSR_C_BIT 0x20000000 /* Bit 29: Carry/Borrow/Extend */
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#define PSR_Z_BIT 0x40000000 /* Bit 30: Zero */
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#define PSR_N_BIT 0x80000000 /* Bit 31: Negative/Less than */
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/* CR1 bits (CP#15 CR1) */
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#define CR_M 0x00000001 /* MMU enable */
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#define CR_A 0x00000002 /* Alignment abort enable */
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#define CR_C 0x00000004 /* Dcache enable */
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#define CR_W 0x00000008 /* Write buffer enable */
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#define CR_P 0x00000010 /* 32-bit exception handler */
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#define CR_D 0x00000020 /* 32-bit data address range */
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#define CR_L 0x00000040 /* Implementation defined */
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#define CR_B 0x00000080 /* Big endian */
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#define CR_S 0x00000100 /* System MMU protection */
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#define CR_R 0x00000200 /* ROM MMU protection */
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#define CR_F 0x00000400 /* Implementation defined */
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#define CR_Z 0x00000800 /* Implementation defined */
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#define CR_I 0x00001000 /* Icache enable */
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#define CR_V 0x00002000 /* Vectors relocated to 0xffff0000 */
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#define CR_RR 0x00004000 /* Round Robin cache replacement */
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#define CR_L4 0x00008000 /* LDR pc can set T bit */
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#define CR_DT 0x00010000
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#define CR_IT 0x00040000
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#define CR_ST 0x00080000
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#define CR_FI 0x00200000 /* Fast interrupt (lower latency mode) */
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#define CR_U 0x00400000 /* Unaligned access operation */
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#define CR_XP 0x00800000 /* Extended page tables */
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#define CR_VE 0x01000000 /* Vectored interrupts */
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#define REG_R0 (0)
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#define REG_R1 (1)
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#define REG_R2 (2)
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#define REG_R3 (3)
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#define REG_R4 (4)
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#define REG_R5 (5)
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#define REG_R6 (6)
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#define REG_R7 (7)
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#define REG_R8 (8)
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#define REG_R9 (9)
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#define REG_R10 (10)
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#define REG_R11 (11)
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#define REG_R12 (12)
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#define REG_R13 (13)
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#define REG_R14 (14)
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#define REG_R15 (15)
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#define REG_CPSR (16)
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#define XCPTCONTEXT_REGS (17)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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#define REG_A1 REG_R0
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#define REG_A2 REG_R1
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#define REG_A3 REG_R2
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#define REG_A4 REG_R3
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#define REG_V1 REG_R4
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#define REG_V2 REG_R5
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#define REG_V3 REG_R6
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#define REG_V4 REG_R7
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#define REG_V5 REG_R8
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#define REG_V6 REG_R9
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#define REG_V7 REG_R10
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#define REG_SB REG_R9
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#define REG_SL REG_R10
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#define REG_FP REG_R11
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#define REG_IP REG_R12
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#define REG_SP REG_R13
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#define REG_LR REG_R14
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#define REG_PC REG_R15
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.section data
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g_irqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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g_undeftmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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g_aborttmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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.section text
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.global irq_handler
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irq_handler:
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/* On entry, we are in IRQ mode. We are free to use
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* the IRQ mode r13 and r14.
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*/
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ldr r13, .Lirqtmp
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sub lr, lr, #4
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str lr, [r13] @ save lr_IRQ
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mrs lr, spsr
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str lr, [r13, #4] @ save spsr_IRQ
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/* Then switch back to SVC mode */
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bic lr, lr, #MODE_MASK /* Keep F and T bits */
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orr lr, lr, #(SVC_MODE | PSR_I_BIT)
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msr cpsr_c, lr /* Switch to SVC mode */
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
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*/
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lirqtmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
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stmia r0, {r1-r4}
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/* Then call the IRQ handler with interrupts disabled. */
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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ldr sp, .Lirqstackbase /* SP = interrupt stack base */
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str r0, [sp] /* Save the user stack pointer */
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bl irq_handler_c /* Call the handler */
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ldr sp, [sp] /* Restore the user stack pointer */
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#else
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bl irq_handler_c /* Call the handler */
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/* Restore the CPSR, SVC mode registers and return */
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.Lnoirqset:
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r0
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#endif
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ldmia sp, {r0-r15}^ /* Return */
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.Lirqtmp:
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.word g_irqtmp
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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.Lirqstackbase:
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.word g_intstackbase
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#endif
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.size irq_handler, . - irq_handler
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.align 5
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.globl swi_handler
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.type swi_handler, %function
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swi_handler:
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/* Create a context structure. First set aside a stack frame
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* and store r0-r12 into the frame.
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*/
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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/* Get the correct values of r13(sp), r14(lr), r15(pc)
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* and CPSR in r1-r4 */
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14 /* R14 is altered on return from SWI */
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mov r3, r14 /* Save r14 as the PC as well */
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mrs r4, spsr /* Get the saved CPSR */
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add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
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stmia r0, {r1-r4}
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/* Then call the SWI handler with interrupts disabled.
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* void up_syscall(struct xcptcontext *xcp)
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*/
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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/*bl swi_handler_c*/ /* Call the handler */
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/* Restore the CPSR, SVC mode registers and return */
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r0
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ldmia sp, {r0-r15}^ /* Return */
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.size swi_handler, . - swi_handler
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.align 5
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