fe826f6e1d
We used to while(1) wait for EMI to calibrate, but sometimes EMI never returns from calibration. Break if it hasn't finished after 256 tries. Signed-off-by: Sean Cross <xobs@kosagi.com>
155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
#include <string.h>
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#include "bionic.h"
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#include "memio.h"
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#include "fernvale-emi.h"
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#include "fernvale-pmic.h"
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#define PSRAM_TEST_SHOULD_INVERT (1 << 0)
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#define PSRAM_TEST_SHOULD_RANDOMIZE (1 << 1)
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/* Use the built-in memory self test to check calibration */
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static int psram_test_run(uint32_t addr, uint32_t length, uint16_t pattern)
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{
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int run;
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uint32_t test_range;
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uint32_t params;
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int tries;
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test_range = (addr << 8) & 0xffff0000;
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test_range |= (length >> 8) - 1;
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for (run = 0; run < 4; run++) {
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/* Params contains the "start key", plus some other flags */
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params = EMI_CTRL_MBISTB_START_KEY;
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/* On some runs, invert the pattern */
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if (run & PSRAM_TEST_SHOULD_INVERT)
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params |= EMI_CTRL_MBISTB_INVERT;
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/* On some runs, randomize the data */
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if (run & PSRAM_TEST_SHOULD_RANDOMIZE)
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params |= EMI_CTRL_MBISTB_RANDOMIZE;
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/* Reset MBIST engine */
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writel(0, EMI_CTRL_MBISTA);
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/* Set range (start and length) */
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writel(test_range, EMI_CTRL_MBISTB);
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/* Kick off the test */
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writel(params, EMI_CTRL_MBISTA);
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/* Wait for it to finish */
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for (tries = 0; tries < 256; tries++)
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if (readl(EMI_CTRL_MBISTD) & EMI_CTRL_MBISTD_FINISHED)
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break;
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/* If it didn't finis, try again */
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if (!(readl(EMI_CTRL_MBISTD) & EMI_CTRL_MBISTD_FINISHED))
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continue;
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/* If the test failed, return false */
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if ( readl(EMI_CTRL_MBISTD) & EMI_CTRL_MBISTD_FAILURE )
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return 0;
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}
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return 1;
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}
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static int psram_test(void)
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{
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int i;
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uint32_t test_start = 0x100000;
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uint32_t test_length = 0x8000;
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uint16_t patterns[] = {0xffff, 0xa55a};
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for (i = 0; i < sizeof(patterns)/sizeof(*patterns); i++)
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if (!psram_test_run(test_start, test_length, patterns[i]))
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return 0;
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/* All tests passed */
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return 1;
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}
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/* Set all 16 DQY delays to the same value */
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static void psram_set_ganged_dqy(uint8_t delay)
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{
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uint32_t vals = (delay << 0) |
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(delay << 8) |
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(delay << 16) |
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(delay << 24);
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writel(vals, EMI_CTRL_IDLA);
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writel(vals, EMI_CTRL_IDLB);
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writel(vals, EMI_CTRL_IDLC);
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writel(vals, EMI_CTRL_IDLD);
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}
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static void psram_set_ganged_dqs(uint8_t delay)
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{
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uint32_t vals = (delay << 24) |
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(delay << 16);
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writel(vals, EMI_CTRL_IDLE);
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}
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int calibrate_psram(void)
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{
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int dqy_delay;
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int dqy_delay_upper = -1;
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int dqy_delay_lower = -1;
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int dqs_delay;
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int dqs_delay_upper = -1;
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int dqs_delay_lower = -1;
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for (dqy_delay = 0; dqy_delay < 32; dqy_delay++) {
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/*
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* Since this chip is probably routed properly, assume
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* all trace lengths require the same delay.
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*/
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psram_set_ganged_dqy(dqy_delay);
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if (psram_test()) {
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if (dqy_delay_lower == -1)
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dqy_delay_lower = dqy_delay;
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else
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dqy_delay_upper = dqy_delay;
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}
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}
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if (-1 == dqy_delay_upper)
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dqy_delay_upper = dqy_delay_lower;
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if (dqy_delay_upper != -1) {
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dqy_delay = (dqy_delay_lower + dqy_delay_upper) / 2;
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psram_set_ganged_dqy(dqy_delay);
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return 1;
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}
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/* If DQY delays fail, try DQS instead */
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psram_set_ganged_dqy(0);
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for (dqs_delay = 1; dqs_delay <= 31; dqs_delay++) {
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psram_set_ganged_dqs(dqs_delay);
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if (psram_test()) {
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if (dqs_delay_lower == -1)
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dqs_delay_lower = dqs_delay;
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else
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dqs_delay_upper = dqs_delay;
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return 1;
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}
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}
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if (-1 == dqs_delay_upper)
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dqs_delay_upper = dqs_delay_lower;
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if (dqs_delay_upper != -1) {
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dqs_delay = (dqs_delay_upper + dqs_delay_lower) / 2;
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psram_set_ganged_dqs(dqs_delay);
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return 1;
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}
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/* Failure */
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return 0;
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}
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