a7ff5acb5d
Rather than completely rewriting everything on each runthrough, we now only refill the command buffer before toggling the RUN bit. This will improve performance by eliminating excessive register writes. Signed-off-by: Sean Cross <xobs@kosagi.com>
240 lines
8.7 KiB
C
240 lines
8.7 KiB
C
#ifndef __FV_LCD_H__
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#define __FV_LCD_H__
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// don't take values in here as gospel. some may be incorrect due to
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// misinterpertation of reverse engineered values
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#define LCD_CTRL_ADDR 0xa0450000
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#define LCD_STATUS_REG (LCD_CTRL_ADDR+0x0000)
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#define LCD_STATUS_RUN_BIT (0x1)
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#define LCD_STATUS_WAIT_CMDQ_BIT (0x2)
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#define LCD_STATUS_WAIT_HTT_BIT (0x8)
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#define LCD_STATUS_TE_PENDING_BIT (0x10)
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#define LCD_STATUS_BUSY_BIT (0x20)
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#define LCD_STATUS_GMC_REQ_BIT (0x40)
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#define LCD_INT_ENA_REG (LCD_CTRL_ADDR+0x0004)
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#define LCD_INT_ENA_TRIG_BIT (0x1)
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#define LCD_INT_ENA_REG_TRIG_BIT (0x2)
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#define LCD_INT_ENA_CMD_TRIG_BIT (0x4)
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#define LCD_INT_ENA_HTT_TRIG_BIT (0x10)
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#define LCD_INT_ENA_HSYNC_TRIG_BIT (0x20)
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#define LCD_INT_ENA_VSYNC_TRIG_BIT (0x20)
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#define LCD_INT_STAT_REG (LCD_CTRL_ADDR+0x0008)
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#define LCD_INT_STAT_DONE_BIT (0x1)
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#define LCD_RUN_REG (LCD_CTRL_ADDR+0x000C)
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#define LCD_RUN_BIT (0x8000)
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#define LCD_RESET_REG (LCD_CTRL_ADDR+0x0010)
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#define LCD_RESET_MASK (1 << 0)
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#define LCD_RESET_SET (0 << 0)
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#define LCD_RESET_CLEAR (1 << 0)
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#define LCD_PAR0_CFG_REG (LCD_CTRL_ADDR+0x0030)
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#define LCD_PAR1_CFG_REG (LCD_CTRL_ADDR+0x0034)
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#define LCD_PAR_CFG_WR_WAIT_CYC_MASK (0x3F)
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#define LCD_PAR_CFG_WR_WAIT_CYC_BIT (0)
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#define LCD_PAR_CFG_WR_TSU_MASK (0xF00)
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#define LCD_PAR_CFG_WR_TSU_BIT (8)
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#define LCD_PAR_CFG_WR_TH_MASK (0xF000)
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#define LCD_PAR_CFG_WR_TH_BIT (12)
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#define LCD_PAR_CFG_RD_LATENCY_CYC_MASK (0x3F0000)
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#define LCD_PAR_CFG_RD_LATENCY_CYC_BIT (16)
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#define LCD_PAR_CFG_RD_TSU_MASK (0xF000000)
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#define LCD_PAR_CFG_RD_TSU_BIT (24)
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#define LCD_PAR_CFG_RD_TH_MASK (0xF0000000)
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#define LCD_PAR_CFG_RD_TH_BIT (28)
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#define LCD_PAR_DATA_WIDTH_REG (LCD_CTRL_ADDR+0x003C)
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#define LCD_PAR_BUS_WIDTH0_MASK (0x7)
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#define LCD_PAR_BUS_WIDTH0_BIT (0)
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#define LCD_PAR_BUS_WIDTH1_MASK (0x70)
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#define LCD_PAR_BUS_WIDTH1_BIT (4)
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#define LCD_PAR_W2W_WAIT0_MASK (0xF0000)
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#define LCD_PAR_W2W_WAIT0_BIT (16)
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#define LCD_PAR_W2W_WAIT1_MASK (0xF00000)
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#define LCD_PAR_W2W_WAIT1_BIT (20)
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#define LCD_PAR_BUS_WIDTH_8BIT (0)
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#define LCD_PAR_BUS_WIDTH_9BIT (1)
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#define LCD_PAR_BUS_WIDTH_16BIT (2)
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#define LCD_PAR_BUS_WIDTH_18BIT (3)
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#define LCD_TEARING_SYNC_CALC_REG (LCD_CTRL_ADDR+0x0044)
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#define LCD_TEARING_LCD_SIZE_REG (LCD_CTRL_ADDR+0x0048)
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#define LCD_TEARING_LCD_SIZE_HTIME_SHIFT 0
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#define LCD_TEARING_LCD_SIZE_HTIME_MASK 0x3ff
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#define LCD_TEARING_LCD_SIZE_VTIME_SHIFT 16
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#define LCD_TEARING_LCD_SIZE_VTIME_MASK 0x0fff0000
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#define LCD_TEARING_SYNC_CNT_REG (LCD_CTRL_ADDR+0x004C)
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#define LCD_TEARING_REG (LCD_CTRL_ADDR+0x0050)
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#define LCD_TEARING_ENABLE (1 << 0)
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#define LCD_TEARING_POLARITY (1 << 1)
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#define LCD_TEARING_MODE_VSYNC (1 << 2) /* Might be inverted */
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#define LCD_TEARING_MODE_HSYNC (0 << 2) /* Might be inverted */
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#define LCD_TEARING_SW_FORCE_BIT (1 << 15)
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#define LCD_GMC_CTRL_REG (LCD_CTRL_ADDR+0x0054)
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#define LCD_GMC_CTRL_BURST_4BYTE (0 << 0)
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#define LCD_GMC_CTRL_BURST_16BYTE (2 << 0)
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#define LCD_GMC_CTRL_BURST_32BYTE (3 << 0)
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#define LCD_GMC_CTRL_BURST_64BYTE (4 << 0)
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#define LCD_GMC_CTRL_ENABLE (1 << 4)
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#define LCD_GMC_CTRL_PERIOD_MASK (0xffff0000)
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#define LCD_GMC_CTRL_PERIOD_SHIFT 16
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#define LCD_AUTOCOPY_CTRL_REG (LCD_CTRL_ADDR+0x0080)
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// should be:
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// 0 - BGR
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// 0 - significance (?)
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// 1 - padding on MSBs
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// 010 - RGB565 (100 for RGB888, 011 for RGB66)
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// 10 - 9-bit interface
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// 000000 - command (no commands now)
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// 0 -- disable W2M
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// 0 -- enable commands
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// 00000010 -- 2 cycle waiting period (may be ok to set 0 but for now set to 2)
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// 1 -- send residue mode, residue per frame
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// 0
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// 1 -- enable frame update counter. why not?
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// 0
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// 1000 -- enable layer 0 only
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// 1000 0101 0000 0010 1000 0000 1001 0100 = 0x85028094
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#define LCD_AUTOCOPY_CTRL_FORMAT_MASK 0x020000FF
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/* Pixel ordering */
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#define LCD_AUTOCOPY_CTRL_FORMAT_RGB (0 << 0)
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#define LCD_AUTOCOPY_CTRL_FORMAT_BGR (1 << 0)
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/* Format when sending across wire */
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#define LCD_AUTOCOPY_CTRL_FORMAT_MSB (0 << 1)
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#define LCD_AUTOCOPY_CTRL_FORMAT_LSB (1 << 1)
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/* If padding is needed, where to add padding */
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#define LCD_AUTOCOPY_CTRL_FORMAT_PAD_LSB (0 << 2)
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#define LCD_AUTOCOPY_CTRL_FORMAT_PAD_MSB (1 << 2)
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#define LCD_AUTOCOPY_CTRL_FORMAT_RGB332 (0b000 << 3)
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#define LCD_AUTOCOPY_CTRL_FORMAT_RGB444 (0b001 << 3)
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#define LCD_AUTOCOPY_CTRL_FORMAT_RGB565 (0b010 << 3)
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#define LCD_AUTOCOPY_CTRL_FORMAT_RGB666 (0b011 << 3)
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#define LCD_AUTOCOPY_CTRL_FORMAT_RGB888 (0b100 << 3)
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#define LCD_AUTOCOPY_CTRL_FORMAT_IFACE_8BIT (0b00 << 6)
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#define LCD_AUTOCOPY_CTRL_FORMAT_IFACE_16BIT (0b01 << 6)
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#define LCD_AUTOCOPY_CTRL_FORMAT_IFACE_9BIT (0b10 << 6)
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#define LCD_AUTOCOPY_CTRL_FORMAT_IFACE_18BIT (0b11 << 6)
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/* Support prefixing LCD data with command/data bytes */
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#define LCD_AUTOCOPY_CTRL_CMD_COUNT_SHIFT 8
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#define LCD_AUTOCOPY_CTRL_CMD_COUNT_MASK 0x00003f00
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/* Enable writing to memory, in addition to writing to LCD module */
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#define LCD_AUTOCOPY_CTRL_W2M (1 << 14)
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/* Enable sending command bytes. */
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#define LCD_AUTOCOPY_CTRL_ENC (1 << 15)
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/* Waiting period between two consecutive data/command transfers */
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#define LCD_AUTOCOPY_CTRL_PERIOD_SHIFT 16
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#define LCD_AUTOCOPY_CTRL_PERIOD_MASK 0x00ff0000
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/* Send residue per frame */
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#define LCD_AUTOCOPY_CTRL_SEND_RESIDUE (1 << 24)
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#define LCD_AUTOCOPY_CTRL_COLOR_MODE (1 << 26)
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#define LCD_AUTOCOPY_CTRL_EN3 (1 << 28)
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#define LCD_AUTOCOPY_CTRL_EN2 (1 << 29)
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#define LCD_AUTOCOPY_CTRL_EN1 (1 << 30)
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#define LCD_AUTOCOPY_CTRL_EN0 (1 << 31)
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#define LCD_AUTOCOPY_CTRL_LAYER_MASK 0xf0000000
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/* Set to 0, uint 32 */
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#define LCD_AUTOCOPY_OFFSET_REG (LCD_CTRL_ADDR+0x0084)
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/* Address to write commands to, when running with LCD_AUTOCOPY_CTRL_ENC */
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#define LCD_AUTOCOPY_CMD_ADDR_REG (LCD_CTRL_ADDR+0x0088)
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/* Address to write data to, when running with LCD_AUTOCOPY_CTRL_ENC */
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#define LCD_AUTOCOPY_DATA_ADDR_REG (LCD_CTRL_ADDR+0x008C)
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/* Set to 0x014000F0, uint32 (320x240) */
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#define LCD_AUTOCOPY_SIZE_REG (LCD_CTRL_ADDR+0x0090)
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/* Set to 0x80008000 (slight greenish) */
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#define LCD_AUTOCOPY_BG_COLOR_REG (LCD_CTRL_ADDR+0x009C)
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#define LCD_LAYER0_CTRL_REG (LCD_CTRL_ADDR+0x00B0)
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#define LCD_LAYER_CTRL_OPA_MASK (0xff)
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#define LCD_LAYER_CTRL_OPA_SHIFT 0
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#define LCD_LAYER_CTRL_OPA_EN (1 << 8)
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#define LCD_LAYER_CTRL_ROT0 (0 << 11)
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#define LCD_LAYER_CTRL_ROT90 (1 << 11)
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#define LCD_LAYER_CTRL_ROT180 (2 << 11)
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#define LCD_LAYER_CTRL_ROT270 (3 << 11)
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#define LCD_LAYER_CTRL_HFLIP (1 << 13)
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#define LCD_LAYER_CTRL_SRC_KEY_EN (1 << 14)
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#define LCD_LAYER_CTRL_DST_KEY_EN (1 << 14)
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#define LCD_LAYER_CTRL_DATA_SWAP_EN (1 << 16)
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#define LCD_LAYER_CTRL_DITHER_EN (1 << 18)
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#define LCD_LAYER_CTRL_CLRDPT_8BPP (0 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_RGB565 (1 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_UYVY422 (2 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_RGB888 (3 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_ARGB8888 (4 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_PARGB8888 (5 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_XRGB (6 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_ARGB6666 (7 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_PARGB6666 (8 << 20)
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#define LCD_LAYER_CTRL_CLRDPT_MONO (9 << 20)
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#define LCD_LAYER_CTRL_SWP (1 << 24)
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#define LCD_LAYER0_SRC_KEY_REG (LCD_CTRL_ADDR+0x00B4)
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#define LCD_LAYER0_OFFSET_REG (LCD_CTRL_ADDR+0x00B8)
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#define LCD_LAYER0_SRC_ADDR_REG (LCD_CTRL_ADDR+0x00BC)
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#define LCD_LAYER0_SIZE_REG (LCD_CTRL_ADDR+0x00C0)
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#define LCD_LAYER0_MEM_OFFSET_REG (LCD_CTRL_ADDR+0x00C8)
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#define LCD_LAYER0_PITCH_REG (LCD_CTRL_ADDR+0x00CC)
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// there's 3 more layers, but I'm happy to just get one working for now...
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#define LCD_FRAME_COUNTER_CON_REG (LCD_CTRL_ADDR+0x0220)
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#define LCD_FRAME_COUNTER_CON_START (1 << 0)
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#define LCD_FRAME_COUNTER_CON_STOP (1 << 1)
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#define LCD_FRAME_COUNTER_REG (LCD_CTRL_ADDR+0x0224)
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#define LCD_FREERUN_CTRL_REG (LCD_CTRL_ADDR+0x0240)
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#define LCD_FREERUN_CTRL_ENABLE_DBI (1 << 0)
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#define LCD_FREERUN_CTRL_ENABLE_GMC (1 << 1)
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#define LCD_FREERUN_RATE_REG (LCD_CTRL_ADDR+0x0244)
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#define LCD_FREERUN_RATE_MASK (0x3ff)
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#define LCD_FREERUN_DBI_THRESH_REG (LCD_CTRL_ADDR+0x0248)
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#define LCD_FREERUN_DBI_THRESH_LOW_SHIFT 0
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#define LCD_FREERUN_DBI_THRESH_LOW_MASK (0xffff)
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#define LCD_FREERUN_DBI_THRESH_HIGH_SHIFT 16
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#define LCD_FREERUN_DBI_THRESH_HIGH_MASK (0xffff0000)
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#define LCD_FREERUN_GMC_THRESH_REG (LCD_CTRL_ADDR+0x0248)
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#define LCD_FREERUN_GMC_THRESH_LOW_SHIFT 0
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#define LCD_FREERUN_GMC_THRESH_LOW_MASK (0xffff)
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#define LCD_FREERUN_GMC_THRESH_HIGH_SHIFT 16
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#define LCD_FREERUN_GMC_THRESH_HIGH_MASK (0xffff0000)
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#define LCD_CMD_LIST_ADDR (LCD_CTRL_ADDR+0x0C00)
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#define LCD_PAR0_CMD_PORT_REG (LCD_CTRL_ADDR+0x0F00)
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#define LCD_PAR0_DAT_PORT_REG (LCD_CTRL_ADDR+0x0F10)
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#define LCD_PAR1_CMD_PORT_REG (LCD_CTRL_ADDR+0x0F20)
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#define LCD_PAR1_DAT_PORT_REG (LCD_CTRL_ADDR+0x0F30)
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#endif /* __FV_LCD_H__ */
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