101 lines
3.6 KiB
C
101 lines
3.6 KiB
C
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#ifndef __FV_SPI_H__
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#define __FV_SPI_H__
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#define SPI_ADDR 0xa0140000
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#define SPI_BLOCKMODE (SPI_ADDR + 0x00)
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#define SPI_BLOCKMODE_BUSY (1 << 0)
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#define SPI_BLOCKMODE_PREP (1 << 1)
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#define SPI_BLOCKMODE_TRIGGER (1 << 2)
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#define SPI_BLOCKMODE_ENABLE (1 << 3)
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#define SPI_BLOCKMODE_QUAD (1 << 4)
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#define SPI_BLOCKMODE_RELEASE (1 << 16)
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#define SPI_BLOCKMODE_CS (0 << 28)
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#define SPI_BLOCKMODE_CS0 (0 << 28)
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#define SPI_BLOCKMODE_CS1 (1 << 28)
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#define SPI_PIO_CS0 (SPI_ADDR + 0x04)
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#define SPI_PIO_QUAD_ENABLE (1 << 0)
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#define SPI_PIO_CMD1_WIDE (1 << 1)
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#define SPI_PIO_CMD2_ON (1 << 2)
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#define SPI_PIO_CMD2_WIDE (1 << 3)
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#define SPI_PIO_MODE (7 << 4)
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#define SPI_PIO_MODE_SLOW (0 << 4)
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#define SPI_PIO_MODE_FAST (1 << 4)
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#define SPI_PIO_MODE_QUAD (7 << 4)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_0 (0 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_1 (1 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_2 (2 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_3 (3 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_4 (4 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_5 (5 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_6 (6 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_7 (7 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_8 (8 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_9 (9 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_10 (10 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_11 (11 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_12 (12 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_13 (13 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_14 (14 << 8)
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#define SPI_PIO_CMD1_DUMMY_CYCLES_15 (15 << 8)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_0 (0 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_1 (1 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_2 (2 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_3 (3 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_4 (4 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_5 (5 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_6 (6 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_7 (7 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_8 (8 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_9 (9 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_10 (10 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_11 (11 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_12 (12 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_13 (13 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_14 (14 << 12)
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#define SPI_PIO_CMD2_DUMMY_CYCLES_15 (15 << 12)
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#define SPI_PIO_CMD1_SHIFT 16
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#define SPI_PIO_CMD1_MASK (255 << 16)
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#define SPI_PIO_CMD2_SHIFT 24
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#define SPI_PIO_CMD2_MASK (255 << 24)
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#define SPI_CTRL1 (SPI_ADDR + 0x08)
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#define SPI_CTRL1_LATCH_DELAY_0 (0 << 0)
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#define SPI_CTRL1_LATCH_DELAY_1 (1 << 0)
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#define SPI_CTRL1_LATCH_DELAY_2 (2 << 0)
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#define SPI_CTRL1_LATCH_DELAY_3 (3 << 0)
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#define SPI_CTRL1_BUS_IDLE (1 << 8)
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#define SPI_CTRL2 (SPI_ADDR + 0x0c)
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#define SPI_CTRL2_DDR_ENABLE (1 << 1)
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#define SPI_WRITE_COUNT (SPI_ADDR + 0x10)
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#define SPI_READ_COUNT (SPI_ADDR + 0x14)
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#define SPI_RESET (SPI_ADDR + 0x18)
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#define SPI_STATUS (SPI_ADDR + 0x1c)
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#define SPI_DELAY1 (SPI_ADDR + 0x20)
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#define SPI_DELAY2 (SPI_ADDR + 0x24)
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#define SPI_DELAY3 (SPI_ADDR + 0x28)
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#define SPI_DELAY4 (SPI_ADDR + 0x2c)
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#define SPI_DELAY5 (SPI_ADDR + 0x30)
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#define SPI_DELAY6 (SPI_ADDR + 0x34)
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#define SPI_DELAY7 (SPI_ADDR + 0x38)
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#define SPI_DELAY8 (SPI_ADDR + 0x3c)
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#define SPI_PIO_CS1 (SPI_ADDR + 0x40) /* Same map as SPI_PIO_CS0 */
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#define SPI_CTRL3 (SPI_ADDR + 0x44)
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#define SPI_CTRL3_CHANNEL1_MASK (1 << 8)
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#define SPI_CTRL3_CHANNEL2_MASK (1 << 9)
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#define SPI_CTRL3_CHANNEL3_MASK (1 << 10)
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#define SPI_CTRL3_CHANNEL4_MASK (1 << 11)
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#define SPI_CTRL3_CHANNEL1_IDLE (1 << 12)
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#define SPI_CTRL3_CHANNEL2_IDLE (1 << 13)
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#define SPI_CTRL3_CHANNEL3_IDLE (1 << 14)
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#define SPI_CTRL3_CHANNEL4_IDLE (1 << 15)
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/* Dedicated buffer for SPI data */
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#define SPI_DATA ((void *)(SPI_ADDR + 0x800))
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#endif /* __FV_SPI_H__ */
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