145 lines
5.3 KiB
C
145 lines
5.3 KiB
C
#ifndef __FV_USB_H__
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#define __FV_USB_H__
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#define USB_CTRL_ADDR 0xa0900000
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#define USB_CTRL_FADDR (USB_CTRL_ADDR + 0x00)
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#define USB_CTRL_POWER (USB_CTRL_ADDR + 0x01)
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#define USB_CTRL_POWER_SUSPENAB (1 << 0)
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#define USB_CTRL_POWER_SUSPMODE (1 << 1)
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#define USB_CTRL_POWER_RESUME (1 << 2)
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#define USB_CTRL_POWER_RESET (1 << 3)
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#define USB_CTRL_POWER_SWRSTENAB (1 << 4)
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#define USB_CTRL_POWER_ISOUPDATE (1 << 7)
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#define USB_CTRL_INTRIN (USB_CTRL_ADDR + 0x02)
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#define USB_CTRL_INTRIN_EP0 (1 << 0)
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#define USB_CTRL_INTRIN_EP1_IN (1 << 1)
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#define USB_CTRL_INTRIN_EP2_IN (1 << 2)
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#define USB_CTRL_INTRIN_EP3_IN (1 << 3)
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#define USB_CTRL_INTRIN_EP4_IN (1 << 4)
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#define USB_CTRL_INTROUT (USB_CTRL_ADDR + 0x04)
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#define USB_CTRL_INTROUT_EP1_OUT (1 << 1)
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#define USB_CTRL_INTROUT_EP2_OUT (1 << 2)
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#define USB_CTRL_INTRUSB (USB_CTRL_ADDR + 0x06)
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#define USB_CTRL_INTRUSB_SUSPEND (1 << 0)
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#define USB_CTRL_INTRUSB_RESUME (1 << 1)
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#define USB_CTRL_INTRUSB_RESET (1 << 2)
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#define USB_CTRL_INTRUSB_SOF (1 << 3)
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#define USB_CTRL_INTRUSB_POWERDWN (1 << 4)
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/* IN interrupt enable */
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#define USB_CTRL_INTRINE (USB_CTRL_ADDR + 0x07)
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#define USB_CTRL_INTRINE_EP0_ENABLE (1 << 0)
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#define USB_CTRL_INTRINE_EP1_IN_ENABLE (1 << 1)
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#define USB_CTRL_INTRINE_EP2_IN_ENABLE (1 << 2)
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#define USB_CTRL_INTRINE_EP3_IN_ENABLE (1 << 3)
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#define USB_CTRL_INTRINE_EP4_IN_ENABLE (1 << 4)
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#define USB_CTRL_INTROUTE (USB_CTRL_ADDR + 0x09)
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#define USB_CTRL_INTROUTE_EP1_OUT_ENABLE (1 << 1)
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#define USB_CTRL_INTROUTE_EP2_OUT_ENABLE (1 << 2)
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#define USB_CTRL_INTRUSBE (USB_CTRL_ADDR + 0x0b)
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#define USB_CTRL_INTRUSBE_SUSPEND_ENABLE (1 << 0)
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#define USB_CTRL_INTRUSBE_RESUME_ENABLE (1 << 1)
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#define USB_CTRL_INTRUSBE_RESET_ENABLE (1 << 2)
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#define USB_CTRL_INTRUSBE_SOF_ENABLE (1 << 3)
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#define USB_CTRL_INTRUSBE_POWERDWN_ENABLE (1 << 4)
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#define USB_CTRL_FRAME_COUNT1 (USB_CTRL_ADDR + 0x0c)
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#define USB_CTRL_FRAME_COUNT2 (USB_CTRL_ADDR + 0x0d)
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#define USB_CTRL_INDEX (USB_CTRL_ADDR + 0x0e)
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#define USB_CTRL_RSTCTRL (USB_CTRL_ADDR + 0x0f)
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#define USB_CTRL_EP_INMAXP (USB_CTRL_ADDR + 0x10)
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#define USB_CTRL_EP0_CSR (USB_CTRL_ADDR + 0x11)
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#define USB_CTRL_EP0_CSR_OUTPKTRDY (1 << 0)
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#define USB_CTRL_EP0_CSR_INPKTRDY (1 << 1)
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#define USB_CTRL_EP0_CSR_SENTSTALL (1 << 2)
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#define USB_CTRL_EP0_CSR_DATAEND (1 << 3)
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#define USB_CTRL_EP0_CSR_SETUPEND (1 << 4)
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#define USB_CTRL_EP0_CSR_SENDSTALL (1 << 5)
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#define USB_CTRL_EP0_CSR_SOUTPKTRDY (1 << 6)
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#define USB_CTRL_EP0_CSR_SSETUPEND (1 << 7)
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#define USB_CTRL_EP_INCSR1 (USB_CTRL_ADDR + 0x11)
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#define USB_CTRL_EP_INCSR1_INPKTRDY (1 << 0)
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#define USB_CTRL_EP_INCSR1_FIFONOTEMPTY (1 << 1)
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#define USB_CTRL_EP_INCSR1_UNDERRUN (1 << 2)
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#define USB_CTRL_EP_INCSR1_FLUSHFIFO (1 << 3)
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#define USB_CTRL_EP_INCSR1_SENDSTALL (1 << 4)
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#define USB_CTRL_EP_INCSR1_SENTSTALL (1 << 5)
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#define USB_CTRL_EP_INCSR1_CLRDATATOG (1 << 6)
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#define USB_CTRL_EP_INCSR1_ABORTPKT_ENABLE (1 << 7)
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#define USB_CTRL_EP_INCSR2 (USB_CTRL_ADDR + 0x12)
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#define USB_CTRL_EP_INCSR2_FRCDATATOG (1 << 3)
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#define USB_CTRL_EP_INCSR2_DMAENAB (1 << 4)
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#define USB_CTRL_EP_INCSR2_MODE (1 << 5)
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#define USB_CTRL_EP_INCSR2_ISO (1 << 6)
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#define USB_CTRL_EP_INCSR2_AUTOSET (1 << 7)
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#define USB_CTRL_EP_OUTMAXP (USB_CTRL_ADDR + 0x13)
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#define USB_CTRL_EP_OUTCSR1 (USB_CTRL_ADDR + 0x14)
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#define USB_CTRL_EP_OUTCSR1_RXPKTRDY (1 << 0)
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#define USB_CTRL_EP_OUTCSR1_FIFOFULL (1 << 1)
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#define USB_CTRL_EP_OUTCSR1_OVERRUN (1 << 2)
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#define USB_CTRL_EP_OUTCSR1_DATAERROR (1 << 3)
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#define USB_CTRL_EP_OUTCSR1_FLUSHFIFO (1 << 4)
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#define USB_CTRL_EP_OUTCSR1_SENDSTALL (1 << 5)
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#define USB_CTRL_EP_OUTCSR1_SENTSTALL (1 << 6)
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#define USB_CTRL_EP_OUTCSR1_CLRDTATOG (1 << 7)
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#define USB_CTRL_EP_OUTCSR2 (USB_CTRL_ADDR + 0x15)
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#define USB_CTRL_EP_OUTCSR2_DMAMODE (1 << 4)
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#define USB_CTRL_EP_OUTCSR2_DMAENAB (1 << 5)
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#define USB_CTRL_EP_OUTCSR2_ISO (1 << 6)
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#define USB_CTRL_EP_OUTCSR2_AUTOCLEAR (1 << 7)
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#define USB_CTRL_EP0_COUNT (USB_CTRL_ADDR + 0x16)
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#define USB_CTRL_EP_COUNT1 (USB_CTRL_ADDR + 0x16)
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#define USB_CTRL_EP_COUNT2 (USB_CTRL_ADDR + 0x17)
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#define USB_CTRL_EP0_FIFO_DB0 (USB_CTRL_ADDR + 0x20)
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#define USB_CTRL_EP0_FIFO_DB1 (USB_CTRL_ADDR + 0x21)
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#define USB_CTRL_EP0_FIFO_DB2 (USB_CTRL_ADDR + 0x22)
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#define USB_CTRL_EP0_FIFO_DB3 (USB_CTRL_ADDR + 0x23)
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#define USB_CTRL_EP1_FIFO_DB0 (USB_CTRL_ADDR + 0x24)
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#define USB_CTRL_EP1_FIFO_DB1 (USB_CTRL_ADDR + 0x25)
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#define USB_CTRL_EP1_FIFO_DB2 (USB_CTRL_ADDR + 0x26)
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#define USB_CTRL_EP1_FIFO_DB3 (USB_CTRL_ADDR + 0x27)
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#define USB_CTRL_EP2_FIFO_DB0 (USB_CTRL_ADDR + 0x28)
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#define USB_CTRL_EP2_FIFO_DB1 (USB_CTRL_ADDR + 0x29)
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#define USB_CTRL_EP2_FIFO_DB2 (USB_CTRL_ADDR + 0x2a)
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#define USB_CTRL_EP2_FIFO_DB3 (USB_CTRL_ADDR + 0x2b)
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#define USB_CTRL_EP3_FIFO_DB0 (USB_CTRL_ADDR + 0x2c)
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#define USB_CTRL_EP3_FIFO_DB1 (USB_CTRL_ADDR + 0x2d)
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#define USB_CTRL_EP3_FIFO_DB2 (USB_CTRL_ADDR + 0x2e)
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#define USB_CTRL_EP3_FIFO_DB3 (USB_CTRL_ADDR + 0x2f)
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#define USB_CTRL_EP4_FIFO_DB0 (USB_CTRL_ADDR + 0x30)
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#define USB_CTRL_EP4_FIFO_DB1 (USB_CTRL_ADDR + 0x31)
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#define USB_CTRL_EP4_FIFO_DB2 (USB_CTRL_ADDR + 0x32)
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#define USB_CTRL_EP4_FIFO_DB3 (USB_CTRL_ADDR + 0x33)
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#define USB_CTRL_CON (USB_CTRL_ADDR + 0x240)
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/* Enable 1.5k pullup on D+ pin */
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#define USB_CTRL_CON_DPPULLUP (1 << 0)
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/* Enable 1.5k pullup on D- pin */
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#define USB_CTRL_CON_DNPULLUP (1 << 1)
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/* Don't issue a DMA request when a null packet is received */
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#define USB_CTRL_CON_NULLPKT_FIX (1 << 5)
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#endif /* __FV_USB_H__ */
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