yetangitu/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2025-10-06 12:00:04 +02:00
Code Issues Releases Wiki Activity

GT-3202: Sparcv9, corrected pcode for 32-bit std instruction.

Browse source
This commit is contained in:
ghidorahrex 2019-10-07 09:27:58 -04:00
parent 9fb4dc4459
commit 087216607a
1 changed files with 8 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

17
Ghidra/Processors/Sparc/data/languages/SparcV9.sinc
View file

@ -537,20 +537,19 @@ macro unpackflags(ccr) {
# size = 4, but this extended store insn needs to write 8 bytes # size = 4, but this extended store insn needs to write 8 bytes
:stx RD,ea is op=3 & RD & rd_d & op3=0x0e & ea :stx RD,ea is op=3 & RD & rd_d & op3=0x0e & ea
{ {
# There is a bug in the sleigh compiler that implements the tmp_hi:4 = rd_d[32,32] instruction incorrectly tmp_lo:4 = rd_d[0,32];
#tmp_lo:4 = rd_d[0,32]; tmp_hi:4 = rd_d[32,32];
#tmp_hi:4 = rd_d[32,32]; tmp:8 = zext(tmp_lo) + (zext(tmp_hi) << 32);
#tmp:8 = zext(tmp_lo) + zext(tmp_hi << 32); *ea = tmp;
*ea = rd_d;#tmp;
} }
:clrx ea is op=3 & rd=0 & op3=0x0e & ea { *ea = 0:8; } :clrx ea is op=3 & rd=0 & op3=0x0e & ea { *ea = 0:8; }
:std RD,ea is op=3 & RD & rd_d & op3=0x07 & ea :std RD,ea is op=3 & RD & rd_d & op3=0x07 & ea
{ {
#tmp_lo:4 = rd_d[0,32]; tmp_lo:4 = rd_d[0,32];
#tmp_hi:4 = rd_d[32,32]; tmp_hi:4 = rd_d[32,32];
#tmp:8 = zext(tmp_lo) + zext(tmp_hi << 32); tmp:8 = zext(tmp_lo) + (zext(tmp_hi) << 32);
*ea = rd_d;#tmp; *ea = tmp;
} }
:clrd ea is op=3 & rd=0 & op3=0x07 & ea { *ea = 0:8; } :clrd ea is op=3 & rd=0 & op3=0x07 & ea { *ea = 0:8; }