From 239106a356ef8555575a64cc2cfd3fd71b415406 Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Sat, 3 Aug 2019 17:35:24 +0100 Subject: [PATCH 1/2] x86: Restore the use of SAHF/LAHF in 64bit mode The SAHF/LAHF instructions date from the 32bit x86 days, and where initially marked as obsolete in the AMD 64bit spec. All processors have the requisite logic, as they are backwards compatible in 32bit mode. The original 64bit CPUs from Intel and AMD would raise #UD for these instructions, per the AMD64 spec. However, they were were sufficiently critical for software emulators that the instructions were "reintroduced" into the AMD64 spec, with a new CPUID bit indicating that the they were now usable in 64bit mode. In practice, every 64bit capable processor since 2005 has supported them. Fixes #837 --- Ghidra/Processors/x86/data/languages/ia.sinc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index 41b66681bf..5b146faa62 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -3437,7 +3437,8 @@ enterFrames: low5 is low5 { tmp:1 = low5; export tmp; } :JMPF Mem is vexMode=0 & opsize=2 & byte=0xff; Mem & reg_opcode=5 ... { target:$(SIZE) = *:8 Mem; goto [target]; } @endif -:LAHF is vexMode=0 & byte=0x9f & bit64=0 { AH=(SF<<7)|(ZF<<6)|(AF<<4)|(PF<<2)|2|CF; } +# Initially disallowed in 64bit mode, but later reintroduced +:LAHF is vexMode=0 & byte=0x9f { AH=(SF<<7)|(ZF<<6)|(AF<<4)|(PF<<2)|2|CF; } :LAR Reg16,rm16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x2; rm16 & Reg16 ... { Reg16 = rm16 & 0xff00; ZF=1; } :LAR Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x2; rm32 & Reg32 ... & check_Reg32_dest ... { Reg32 = rm32 & 0xffff00; build check_Reg32_dest; ZF=1; } @@ -4089,7 +4090,8 @@ define pcodeop rdtsc; define pcodeop smm_restore_state; :RSM is vexMode=0 & byte=0xf; byte=0xaa { tmp:4 = smm_restore_state(); return [tmp]; } -:SAHF is vexMode=0 & byte=0x9e & bit64=0 { SF = (AH & 0x80) != 0; +# Initially disallowed in 64bit mode, but later reintroduced +:SAHF is vexMode=0 & byte=0x9e { SF = (AH & 0x80) != 0; ZF = (AH & 0x40) != 0; AF = (AH & 0x10) != 0; PF = (AH & 0x04) != 0; From c0a81c8bd3599152c62c82534cd19e96aafb46b3 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Tue, 20 Aug 2019 08:31:25 -0400 Subject: [PATCH 2/2] GT-3095: Accepting pull request Pulled-from: Andrew Cooper