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Merge remote-tracking branch 'origin/patch'

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This commit is contained in:
Ryan Kurtz 2023-11-30 08:23:00 -05:00
commit 0e9c36b513
3 changed files with 18 additions and 12 deletions
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4
Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/sleigh/PcodeEmit.java
View file

@ -505,6 +505,10 @@ public abstract class PcodeEmit {
VarnodeTpl vn, outvn; VarnodeTpl vn, outvn;
int isize = opt.getInput().length; int isize = opt.getInput().length;
if (isize > incache.length) {
incache = new VarnodeData[isize];
}
// First build all the inputs // First build all the inputs
for (int i = 0; i < isize; ++i) { for (int i = 0; i < isize; ++i) {
vn = opt.getInput()[i]; vn = opt.getInput()[i];

18
Ghidra/Processors/68000/data/languages/68000.sinc
View file

@ -335,6 +335,8 @@ define pcodeop saveFPUStateFrame;
define pcodeop restoreFPUStateFrame; define pcodeop restoreFPUStateFrame;
define pcodeop pushInvalidateCaches; define pcodeop pushInvalidateCaches;
define pcodeop fint;
define pcodeop bcdAdjust; define pcodeop bcdAdjust;
define pcodeop sin; define pcodeop sin;
@ -2463,15 +2465,15 @@ fdivrnd: "d" is fopmode=0x64 {}
:fgetman.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1f; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl :fgetman.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1f; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:fgetman fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1f unimpl :fgetman fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1f unimpl
:fint.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x01; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2l); fdst = int2float(tmp); } :fint.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x01; e2l [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fint(e2l, FPCR); }
:fint.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x01; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2x); fdst = int2float(tmp); } :fint.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x01; e2x [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fint(e2x, FPCR); }
:fint.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x01; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2d); fdst = int2float(tmp); } :fint.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x01; e2d [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fint(e2d, FPCR); }
:fint fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x01 { tmp:8 = trunc(fsrc); fdst = int2float(tmp); } :fint fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x01 { fdst = fint(fsrc); }
:fintrz.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x03; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl :fintrz.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x03; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2l); fdst = int2float(tmp); }
:fintrz.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x03; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl :fintrz.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x03; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2x); fdst = int2float(tmp); }
:fintrz.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x03; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl :fintrz.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x03; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2d); fdst = int2float(tmp); }
:fintrz fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x03 unimpl :fintrz fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x03 { tmp:8 = trunc(fsrc); fdst = int2float(tmp); }
:flog10.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x15; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl :flog10.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x15; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:flog10.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x15; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl :flog10.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x15; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl

8
Ghidra/Processors/RISCV/data/languages/riscv.custom.sinc
View file

@ -28,7 +28,7 @@ define pcodeop custom3.rd;
define pcodeop custom3.rd.rs1; define pcodeop custom3.rd.rs1;
define pcodeop custom3.rd.rs1.rs2; define pcodeop custom3.rd.rs1.rs2;
:custom0 is op0001=0x3 & op0204=0x2 & op0506=0x0 & op1214=0x0 :custom0 is op0001=0x3 & op0204=0x2 & op0506=0x0 & (op1214=0x0 | op1214=0x1 | op1214=0x5)
{ {
custom0(); custom0();
} }
@ -59,7 +59,7 @@ define pcodeop custom3.rd.rs1.rs2;
} }
:custom1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & op1214=0x0 :custom1 is op0001=0x3 & op0204=0x2 & op0506=0x1 & (op1214=0x0 | op1214=0x1 | op1214=0x5)
{ {
custom1(); custom1();
} }
@ -92,7 +92,7 @@ define pcodeop custom3.rd.rs1.rs2;
#TODO handle RV128 for custom-2/custom-3 #TODO handle RV128 for custom-2/custom-3
:custom2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & op1214=0x0 :custom2 is op0001=0x3 & op0204=0x6 & op0506=0x2 & (op1214=0x0 | op1214=0x1 | op1214=0x5)
{ {
custom2(); custom2();
} }
@ -123,7 +123,7 @@ define pcodeop custom3.rd.rs1.rs2;
} }
:custom3 is op0001=0x3 & op0204=0x6 & op0506=0x3 & op1214=0x0 :custom3 is op0001=0x3 & op0204=0x6 & op0506=0x3 & (op1214=0x0 | op1214=0x1 | op1214=0x5)
{ {
custom3(); custom3();
} }