From 8936bf9d55fb27823851d869f976b497f0a33bd5 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 14 Aug 2023 16:38:16 +0000 Subject: [PATCH 01/15] GP-3211: Initial commit of Loongarch Processor Module --- Ghidra/Processors/Loongarch/Module.manifest | 0 Ghidra/Processors/Loongarch/build.gradle | 27 + .../Loongarch/certification.manifest | 26 + .../languages/Loongarch32_Instructions.sinc | 1242 ++++ .../languages/Loongarch64_Instructions.sinc | 730 ++ .../data/languages/double_Instructions.sinc | 387 ++ .../data/languages/float_Instructions.sinc | 489 ++ .../Loongarch/data/languages/ilp32d.cspec | 130 + .../Loongarch/data/languages/ilp32f.cspec | 145 + .../Loongarch/data/languages/lasx.sinc | 5851 +++++++++++++++++ .../Loongarch/data/languages/lbt.sinc | 1417 ++++ .../Loongarch/data/languages/loongarch.ldefs | 60 + .../data/languages/loongarch.opinion | 23 + .../data/languages/loongarch32.pspec | 10 + .../data/languages/loongarch32_f32.slaspec | 14 + .../data/languages/loongarch32_f64.slaspec | 13 + .../data/languages/loongarch64.pspec | 10 + .../data/languages/loongarch64_f32.slaspec | 21 + .../data/languages/loongarch64_f64.slaspec | 17 + .../data/languages/loongarch_main.sinc | 564 ++ .../Loongarch/data/languages/lp64d.cspec | 128 + .../Loongarch/data/languages/lp64f.cspec | 131 + .../Loongarch/data/languages/lsx.sinc | 5706 ++++++++++++++++ .../Loongarch/data/languages/lvz.sinc | 59 + .../data/languages/privileged-32.sinc | 172 + .../data/languages/privileged-64.sinc | 14 + .../Loongarch/data/manuals/loongarch.idx | 181 + .../Loongarch64_O0_EmulatorTest.java | 40 + .../Loongarch64_O3_EmulatorTest.java | 40 + .../Loongarch64f_O0_EmulatorTest.java | 40 + .../Loongarch64f_O3_EmulatorTest.java | 40 + 31 files changed, 17727 insertions(+) create mode 100644 Ghidra/Processors/Loongarch/Module.manifest create mode 100644 Ghidra/Processors/Loongarch/build.gradle create mode 100644 Ghidra/Processors/Loongarch/certification.manifest create mode 100644 Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/lasx.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/lbt.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch.opinion create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch32.pspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch64.pspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/lp64d.cspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/lp64f.cspec create mode 100644 Ghidra/Processors/Loongarch/data/languages/lsx.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/lvz.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc create mode 100644 Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc create mode 100644 Ghidra/Processors/Loongarch/data/manuals/loongarch.idx create mode 100644 Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java create mode 100644 Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java create mode 100644 Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64f_O0_EmulatorTest.java create mode 100644 Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64f_O3_EmulatorTest.java diff --git a/Ghidra/Processors/Loongarch/Module.manifest b/Ghidra/Processors/Loongarch/Module.manifest new file mode 100644 index 0000000000..e69de29bb2 diff --git a/Ghidra/Processors/Loongarch/build.gradle b/Ghidra/Processors/Loongarch/build.gradle new file mode 100644 index 0000000000..4c3d1333b5 --- /dev/null +++ b/Ghidra/Processors/Loongarch/build.gradle @@ -0,0 +1,27 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" +apply from: "$rootProject.projectDir/gradle/javaProject.gradle" +apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle" +apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle" +apply from: "$rootProject.projectDir/gradle/processorProject.gradle" +apply plugin: 'eclipse' + +eclipse.project.name = 'Processors Loongarch' + +dependencies { + api project(':Base') +} diff --git a/Ghidra/Processors/Loongarch/certification.manifest b/Ghidra/Processors/Loongarch/certification.manifest new file mode 100644 index 0000000000..bd59f7714c --- /dev/null +++ b/Ghidra/Processors/Loongarch/certification.manifest @@ -0,0 +1,26 @@ +##VERSION: 2.0 +Module.manifest||GHIDRA||||END| +data/languages/Loongarch32_Instructions.sinc||GHIDRA||||END| +data/languages/Loongarch64_Instructions.sinc||GHIDRA||||END| +data/languages/double_Instructions.sinc||GHIDRA||||END| +data/languages/float_Instructions.sinc||GHIDRA||||END| +data/languages/ilp32d.cspec||GHIDRA||||END| +data/languages/ilp32f.cspec||GHIDRA||||END| +data/languages/lasx.sinc||GHIDRA||||END| +data/languages/lbt.sinc||GHIDRA||||END| +data/languages/loongarch.ldefs||GHIDRA||||END| +data/languages/loongarch.opinion||GHIDRA||||END| +data/languages/loongarch32.pspec||GHIDRA||||END| +data/languages/loongarch32_f32.slaspec||GHIDRA||||END| +data/languages/loongarch32_f64.slaspec||GHIDRA||||END| +data/languages/loongarch64.pspec||GHIDRA||||END| +data/languages/loongarch64_f32.slaspec||GHIDRA||||END| +data/languages/loongarch64_f64.slaspec||GHIDRA||||END| +data/languages/loongarch_main.sinc||GHIDRA||||END| +data/languages/lp64d.cspec||GHIDRA||||END| +data/languages/lp64f.cspec||GHIDRA||||END| +data/languages/lsx.sinc||GHIDRA||||END| +data/languages/lvz.sinc||GHIDRA||||END| +data/languages/privileged-32.sinc||GHIDRA||||END| +data/languages/privileged-64.sinc||GHIDRA||||END| +data/manuals/loongarch.idx||GHIDRA||||END| diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc new file mode 100644 index 0000000000..946ef94cc1 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc @@ -0,0 +1,1242 @@ + +#################### +# Base Instructions +#################### + + +#la-base-32.txt add.w mask=0x00100000 [@la32, @primary, @qemu] +#0x00100000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:add.w RD, RJ32src, RK32src is op15_31=0x20 & RD & RJ32src & RK32src { + local add1:4 = RJ32src; + local add2:4 = RK32src; + local result = add1 + add2; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + +#la-base-32.txt addi.w mask=0x02800000 [@la32, @primary, @qemu] +#0x02800000 0xffc00000 r0:5,r5:5,s10:12 ['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] +:addi.w RD, RJ32src, simm10_12 is op22_31=0xa & RD & RJ32src & simm10_12 { + local add1:4 = RJ32src; + local add2:4 = simm10_12; + local result = add1 + add2; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + + +#la-bitops-32.txt sladd.w mask=0x00040000 [@orig_name=alsl.w, @orig_fmt=DJKUa2pp1, @la32] +#0x00040000 0xfffe0000 r0:5,r5:5,r10:5,u15:2+1 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0'] +:alsl.w RD, RJ32src, RK32src, alsl_shift is op17_31=0x2 & RD & RJ32src & RK32src & alsl_shift { + local result:4 = (RJ32src << alsl_shift) + RK32src; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + + +#la-base-32.txt and mask=0x00148000 [@la32, @primary, @qemu] +#0x00148000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:and RD, RJsrc, RKsrc is op15_31=0x29 & RD & RJsrc & RKsrc { + RD = RJsrc & RKsrc; +} + +#la-base-32.txt andi mask=0x03400000 [@la32, @primary, @qemu] +#0x03400000 0xffc00000 r0:5,r5:5,u10:12 ['reg0_5_s0', 'reg5_5_s0', 'imm10_12_s0'] +:andi RD, RJsrc, imm10_12 is op22_31=0xd & RD & RJsrc & imm10_12 { + RD = RJsrc & imm10_12; +} + +# alias of andi r0, r0, 0 +:nop is op22_31=0xd & rD=0 & rJ=0 & imm10_12=0 { +} + +#la-base-32.txt andn mask=0x00168000 [@la32, @primary, @qemu] +#0x00168000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:andn RD, RJsrc, RKsrc is op15_31=0x2d & RD & RJsrc & RKsrc { + RD = RJsrc & ~(RKsrc); +} + + +#la-base-32.txt break mask=0x002a0000 [@la32, @primary] +#0x002a0000 0xffff8000 u0:15 ['imm0_15_s0'] +:break imm0_15 is op15_31=0x54 & imm0_15 { + local code:2 = imm0_15; + break(code); +} + + +#la-base-32.txt cpucfg mask=0x00006c00 [@la32] +#0x00006c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:cpucfg RD, RJ32src is op10_31=0x1b & RD & RJ32src { + RD = cpucfg(RJ32src); +} + + +#la-base-32.txt dbgcall mask=0x002a8000 [@orig_name=dbcl] +#0x002a8000 0xffff8000 u0:15 ['imm0_15_s0'] +:dbcl imm0_15 is op15_31=0x55 & imm0_15 { + local code:2 = imm0_15; + dbcl(code); +} + + +#la-mul-32.txt div.w mask=0x00200000 [@la32, @primary, @qemu] +#0x00200000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:div.w RD, RJ32src, RK32src is op15_31=0x40 & RD & RJ32src & RK32src { + tmp:4 = RJ32src s/ RK32src; + RD = sext(tmp); +} + +#la-mul-32.txt div.wu mask=0x00210000 [@la32, @primary, @qemu] +#0x00210000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:div.wu RD, RJ32src, RK32src is op15_31=0x42 & RD & RJ32src & RK32src { + tmp:4 = RJ32src / RK32src; + RD = sext(tmp); +} + + +#la-base-32.txt sext.b mask=0x00005c00 [@orig_name=ext.w.b, @la32, @qemu] +#0x00005c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:ext.w.b RD, RJsrc is op10_31=0x17 & RD & RJsrc { + local tmp:1 = RJsrc(0); + RD = sext(tmp); +} + +#la-base-32.txt sext.h mask=0x00005800 [@orig_name=ext.w.h, @la32, @qemu] +#0x00005800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:ext.w.h RD, RJsrc is op10_31=0x16 & RD & RJsrc { + local tmp:2 = RJsrc(0); + RD = sext(tmp); +} + + +#la-base-32.txt lu12i.w mask=0x14000000 [@la32, @primary, @qemu] +#0x14000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] +:lu12i.w RD, simm12i is op25_31=0xa & RD & simm12i { +@ifdef LA64 + RD = sext(simm12i); +@else + RD = simm12i; +@endif +} + + +#la-base-32.txt maskeqz mask=0x00130000 [@la32, @qemu] +#0x00130000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:maskeqz RD, RJsrc, RKsrc is op15_31=0x26 & RD & RJsrc & RKsrc { + RD = (zext(RKsrc == 0) * 0) + (zext(RKsrc != 0) * RJsrc); +} + + +#la-base-32.txt masknez mask=0x00138000 [@la32, @qemu] +#0x00138000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:masknez RD, RJsrc, RKsrc is op15_31=0x27 & RD & RJsrc & RKsrc { + RD = (zext(RKsrc != 0) * 0) + (zext(RKsrc == 0) * RJsrc); +} + + +#la-mul-32.txt mod.w mask=0x00208000 [@la32, @primary, @qemu] +#0x00208000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mod.w RD, RJ32src, RK32src is op15_31=0x41 & RD & RJ32src & RK32src { + tmp:4 = RJ32src s% RK32src; + RD = sext(tmp); +} + + + +#la-mul-32.txt mod.wu mask=0x00218000 [@la32, @primary, @qemu] +#0x00218000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mod.wu RD, RJ32src, RK32src is op15_31=0x43 & RD & RJ32src & RK32src { + tmp:4 = RJ32src % RK32src; + RD = sext(tmp); +} + + +#la-mul-32.txt mul.w mask=0x001c0000 [@la32, @primary, @qemu] +#0x001c0000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mul.w RD, RJ32src, RK32src is op15_31=0x38 & RD & RJ32src & RK32src { + tmp1:8 = sext( RJ32src ); + tmp2:8 = sext( RK32src ); + prod:8 = tmp1 * tmp2; + RD = sext( prod:4 ); +} + +#la-mul-32.txt mulh.w mask=0x001c8000 [@la32, @primary, @qemu] +#0x001c8000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mulh.w RD, RJ32src, RK32src is op15_31=0x39 & RD & RJ32src & RK32src { + tmp1:8 = sext( RJ32src ); + tmp2:8 = sext( RK32src ); + prod:8 = tmp1 * tmp2; + prod = prod >> 32; + RD = sext( prod:4 ); +} + +#la-mul-32.txt mulh.wu mask=0x001d0000 [@la32, @primary, @qemu] +#0x001d0000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mulh.wu RD, RJ32src, RK32src is op15_31=0x3a & RD & RJ32src & RK32src { + tmp1:8 = zext( RJ32src ); + tmp2:8 = zext( RK32src ); + prod:8 = tmp1 * tmp2; + prod = prod >> 32; + RD = sext( prod:4 ); +} + + +#la-base-32.txt nor mask=0x00140000 [@la32, @primary, @qemu] +#0x00140000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:nor RD, RJsrc, RKsrc is op15_31=0x28 & RD & RJsrc & RKsrc { + RD = ~(RJsrc | RKsrc); +} + + +#la-base-32.txt or mask=0x00150000 [@la32, @primary, @qemu] +#0x00150000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:or RD, RJsrc, RKsrc is op15_31=0x2a & RD & RJsrc & RKsrc { + RD = RJsrc | RKsrc; +} + +# alias of or rd, rj, zero +:move RD, RJsrc is op15_31=0x2a & RD & RJsrc & rK=0 { + RD = RJsrc; +} + +#la-base-32.txt ori mask=0x03800000 [@la32, @primary, @qemu] +#0x03800000 0xffc00000 r0:5,r5:5,u10:12 ['reg0_5_s0', 'reg5_5_s0', 'imm10_12_s0'] +:ori RD, RJsrc, imm10_12 is op22_31=0xe & RD & RJsrc & imm10_12 { + RD = RJsrc | imm10_12; +} + + +#la-base-32.txt orn mask=0x00160000 [@la32, @primary, @qemu] +#0x00160000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:orn RD, RJsrc, RKsrc is op15_31=0x2c & RD & RJsrc & RKsrc { + RD = RJsrc | ~(RKsrc); +} + + +#la-base-32.txt pcaddu2i mask=0x18000000 [@orig_name=pcaddi, @la32, @primary, @qemu] +#0x18000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] +:pcaddi RD,pcadd2 is op25_31=0xc & RD & pcadd2 { + RD = pcadd2; +} + +#la-base-32.txt pcalau12i mask=0x1a000000 [@la32, @qemu] +#0x1a000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] +:pcalau12i RD, pcala12 is op25_31=0xd & RD & pcala12 { + RD = pcala12; +} + + +#la-base-32.txt pcaddu12i mask=0x1c000000 [@la32, @primary, @qemu] +#0x1c000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] +:pcaddu12i RD, pcadd12 is op25_31=0xe & RD & pcadd12 { + RD = pcadd12; +} + + +#la-base-32.txt pcaddu18i mask=0x1e000000 [@qemu] +#0x1e000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] +:pcaddu18i RD, pcadd18 is op25_31=0xf & RD & pcadd18 { + RD = pcadd18; +} + + +#la-base-32.txt rdtimel.w mask=0x00006000 [@la32, @primary] +#0x00006000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:rdtimel.w RD32, RJ32 is op10_31=0x18 & RD32 & RJ32 { + local tmp:1 = 0; + RD32 = rdtime.counter(tmp); + RJ32 = rdtime.counterid(tmp); +} + + +#la-base-32.txt rdtimeh.w mask=0x00006400 [@la32, @primary] +#0x00006400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:rdtimeh.w RD32, RJ32 is op10_31=0x19 & RD32 & RJ32 { + local tmp:1 = 1; + RD32 = rdtime.counter(tmp); + RJ32 = rdtime.counterid(tmp); +} + + +#la-base-32.txt rotr.w mask=0x001b0000 [@la32, @qemu] +#0x001b0000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:rotr.w RD, RJ32src, RK32src is op15_31=0x36 & RD & RJ32src & RK32src { + local shift:1 = RK32src(0) & 0x1f; + local tmp1:4 = RJ32src s>> shift; + local tmp2:4 = RJ32src << (32 - shift); + local result = tmp1 + tmp2; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + +#la-base-32.txt rotri.w mask=0x004c8000 [@la32, @qemu] +#0x004c8000 0xffff8000 r0:5,r5:5,u10:5 ['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0'] +:rotri.w RD, RJ32src, imm10_5 is op15_31=0x99 & RD & RJ32src & imm10_5 { + local shift:1 = imm10_5; + local tmp1:4 = RJ32src s>> shift; + local tmp2:4 = RJ32src << (32 - shift); + local result = tmp1 + tmp2; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + + +#la-base-32.txt sll.w mask=0x00170000 [@la32, @primary, @qemu] +#0x00170000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sll.w RD, RJ32src, RK32src is op15_31=0x2e & RD & RJ32src & RK32src { + local shift:1 = RK32src(0) & 0x1f; + local result:4 = RJ32src << shift; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + +#la-base-32.txt slli.w mask=0x00408000 [@la32, @primary, @qemu] +#0x00408000 0xffff8000 r0:5,r5:5,u10:5 ['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0'] +:slli.w RD, RJ32src, imm10_5 is op15_31=0x81 & RD & RJ32src& imm10_5 { + local shift:1 = imm10_5 & 0x1f; + local result:4 = RJ32src << shift; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + + +#la-base-32.txt slt mask=0x00120000 [@la32, @primary, @qemu] +#0x00120000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:slt RD, RJsrc, RKsrc is op15_31=0x24 & RD & RJsrc & RKsrc { + RD = zext( RJsrc s< RKsrc ); +} + +#la-base-32.txt sltu mask=0x00128000 [@la32, @primary, @qemu] +#0x00128000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sltu RD, RJsrc, RKsrc is op15_31=0x25 & RD & RJsrc & RKsrc { + RD = zext( RJsrc < RKsrc ); +} + +#la-base-32.txt slti mask=0x02000000 [@la32, @primary, @qemu] +#0x02000000 0xffc00000 r0:5,r5:5,s10:12 ['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] +:slti RD, RJsrc, simm10_12 is op22_31=0x8 & RD & RJsrc & simm10_12 { + RD = zext( RJsrc s< simm10_12 ); +} + +#la-base-32.txt sltui mask=0x02400000 [@la32, @primary, @qemu] +#0x02400000 0xffc00000 r0:5,r5:5,s10:12 ['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] +:sltui RD, RJsrc, simm10_12 is op22_31=0x9 & RD & RJsrc & simm10_12 { + RD = zext( RJsrc < simm10_12 ); +} + + +#la-base-32.txt srl.w mask=0x00178000 [@la32, @primary, @qemu] +#0x00178000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:srl.w RD, RJ32src, RK32src is op15_31=0x2f & RD & RJ32src & RK32src { + local shift:1 = RK32src(0) & 0x1f; + local result:4 = RJ32src >> shift; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + +#la-base-32.txt srli.w mask=0x00448000 [@la32, @primary, @qemu] +#0x00448000 0xffff8000 r0:5,r5:5,u10:5 ['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0'] +:srli.w RD, RJ32src, imm10_5 is op15_31=0x89 & RD & RJ32src & imm10_5 { + local shift:1 = imm10_5 & 0x1f; + local result:4 = RJ32src >> shift; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + + +#la-base-32.txt sra.w mask=0x00180000 [@la32, @primary, @qemu] +#0x00180000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sra.w RD, RJ32src, RK32src is op15_31=0x30 & RD & RJ32src & RK32src { + local shift:1 = RK32src(0) & 0x1f; + local result:4 = RJ32src s>> shift; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + +#la-base-32.txt srai.w mask=0x00488000 [@la32, @primary, @qemu] +#0x00488000 0xffff8000 r0:5,r5:5,u10:5 ['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0'] +:srai.w RD, RJ32src, imm10_5 is op15_31=0x91 & RD & RJ32src & imm10_5 { + local shift:1 = imm10_5 & 0x1f; + local result:4 = RJ32src s>> shift; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + + +#la-base-32.txt sub.w mask=0x00110000 [@la32, @primary, @qemu] +#0x00110000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sub.w RD, RJ32src, RK32src is op15_31=0x22 & RD & RJ32src & RK32src { + local sub1:4 = RJ32src; + local sub2:4 = RK32src; + local result = sub1 - sub2; +@ifdef LA64 + RD = sext(result); +@else + RD = result; +@endif +} + + +#la-base-32.txt syscall mask=0x002b0000 [@la32, @primary] +#0x002b0000 0xffff8000 u0:15 ['imm0_15_s0'] +:syscall imm0_15 is op15_31=0x56 & imm0_15 { + local code:2 = imm0_15; + syscall(code); +} + + +#la-base-32.txt xor mask=0x00158000 [@la32, @primary, @qemu] +#0x00158000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:xor RD, RJsrc, RKsrc is op15_31=0x2b & RD & RJsrc & RKsrc { + RD = RJsrc ^ RKsrc; +} + +#la-base-32.txt xori mask=0x03c00000 [@la32, @primary, @qemu] +#0x03c00000 0xffc00000 r0:5,r5:5,u10:12 ['reg0_5_s0', 'reg5_5_s0', 'imm10_12_s0'] +:xori RD, RJsrc, imm10_12 is op22_31=0xf & RD & RJsrc & imm10_12 { + RD = RJsrc ^ imm10_12; +} + + +########################## +# Load/Store Instructions +########################## + +#la-base-32.txt ldox4.w mask=0x24000000 [@orig_name=ldptr.w, @orig_fmt=DJSk14ps2] +#0x24000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] +:ldptr.w RD, ldstptr_addr is op24_31=0x24 & RD & RJsrc & ldstptr_addr { + local data:4 = *[ram]:4 ldstptr_addr; +@ifdef LA64 + RD = sext(data); +@else + RD = data; +@endif +} + + +#la-base-32.txt stox4.w mask=0x25000000 [@orig_name=stptr.w, @orig_fmt=DJSk14ps2] +#0x25000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] +:stptr.w RD, ldstptr_addr is op24_31=0x25 & RD32 & RD & ldstptr_addr { + *[ram]:4 ldstptr_addr = RD32; +} + + +#la-base-32.txt ld.b mask=0x28000000 [@la32, @primary, @qemu] +#0x28000000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:ld.b RD, ldst_addr is op22_31=0xa0 & RD & RJsrc & ldst_addr { + RD = sext(*[ram]:1 ldst_addr); +} + + +#la-base-32.txt ld.h mask=0x28400000 [@la32, @primary, @qemu] +#0x28400000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:ld.h RD, ldst_addr is op22_31=0xa1 & RD & RJsrc & ldst_addr { + RD = sext(*[ram]:2 ldst_addr); +} + + +#la-base-32.txt ld.w mask=0x28800000 [@la32, @primary, @qemu] +#0x28800000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:ld.w RD, ldst_addr is op22_31=0xa2 & RD & RJsrc & ldst_addr { + local data:4 = *[ram]:4 ldst_addr; +@ifdef LA64 + RD = sext(data); +@else + RD = data; +@endif +} + + +#la-base-32.txt st.b mask=0x29000000 [@la32, @primary, @qemu] +#0x29000000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:st.b RDsrc, ldst_addr is op22_31=0xa4 & RDsrc & ldst_addr { + *[ram]:1 ldst_addr = RDsrc:1; +} + +#la-base-32.txt st.h mask=0x29400000 [@la32, @primary, @qemu] +#0x29400000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:st.h RDsrc, ldst_addr is op22_31=0xa5 & RDsrc & ldst_addr { + *[ram]:2 ldst_addr = RDsrc:2; +} + +#la-base-32.txt st.w mask=0x29800000 [@la32, @primary, @qemu] +#0x29800000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:st.w RDsrc, ldst_addr is op22_31=0xa6 & RDsrc & ldst_addr { + *[ram]:4 ldst_addr = RDsrc:4; +} + + +#la-base-32.txt ld.bu mask=0x2a000000 [@la32, @primary, @qemu] +#0x2a000000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:ld.bu RD, ldst_addr is op22_31=0xa8 & RD & RJsrc & ldst_addr { + RD = zext(*[ram]:1 ldst_addr); +} + + +#la-base-32.txt ld.hu mask=0x2a400000 [@la32, @primary, @qemu] +#0x2a400000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:ld.hu RD, ldst_addr is op22_31=0xa9 & RD & RJsrc & ldst_addr { + RD = zext(*[ram]:2 ldst_addr); +} + +#la-base-32.txt preld mask=0x2ac00000 [@orig_fmt=Ud5JSk12, @la32, @primary] +#0x2ac00000 0xffc00000 u0:5,r5:5,so10:12 ['imm0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:preld imm0_5, ldst_addr is op22_31=0xab & imm0_5 & op0_4=0 & ldst_addr { + preld_loadl1cache(0:1, ldst_addr); +} + +:preld imm0_5, ldst_addr is op22_31=0xab & imm0_5 & op0_4=8 & ldst_addr { + local hint:1 = imm0_5; + preld_storel1cache(8:1, ldst_addr); +} + +:preld imm0_5, ldst_addr is op22_31=0xab & imm0_5 & ldst_addr { + preld_nop(); +} + + +#la-base-32.txt preldx mask=0x382c0000 [@orig_fmt=Ud5JK] +#0x382c0000 0xffff8000 u0:5,r5:5,r10:5 ['imm0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:preldx imm0_5, RJsrc, RKsrc is op15_31=0x7058 & RJsrc & RKsrc & imm0_5 & op0_4=0 { + preldx_loadl1cache(0:1, RJsrc, RKsrc); +} + +:preldx imm0_5, RJsrc, RKsrc is op15_31=0x7058 & RJsrc & RKsrc & imm0_5 & op0_4=8 { + preldx_storel1cache(8:1, RJsrc, RKsrc); +} + +:preldx imm0_5, RJsrc, RKsrc is op15_31=0x7058 & RJsrc & RKsrc & imm0_5 { + preldx_nop(imm0_5:1, RJsrc, RJsrc); +} +#la-base-32.txt ldx.b mask=0x38000000 [@qemu] +#0x38000000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldx.b RD, ldstx_addr is op15_31=0x7000 & RD & ldstx_addr { + RD = sext(*[ram]:1 ldstx_addr); +} + + +#la-base-32.txt ldx.h mask=0x38040000 [@qemu] +#0x38040000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldx.h RD, ldstx_addr is op15_31=0x7008 & RD & ldstx_addr { + RD = sext(*[ram]:2 ldstx_addr); +} + + +#la-base-32.txt ldx.w mask=0x38080000 [@qemu] +#0x38080000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldx.w RD, ldstx_addr is op15_31=0x7010 & RD & ldstx_addr { + local data:4 = *[ram]:4 ldstx_addr; +@ifdef LA64 + RD = sext(data); +@else + RD = data; +@endif +} + + +#la-base-32.txt stx.b mask=0x38100000 [@qemu] +#0x38100000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stx.b RDsrc, ldstx_addr is op15_31=0x7020 & RDsrc & ldstx_addr { + *[ram]:1 ldstx_addr = RDsrc:1; +} + + +#la-base-32.txt stx.h mask=0x38140000 [@qemu] +#0x38140000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stx.h RDsrc, ldstx_addr is op15_31=0x7028 & RDsrc & ldstx_addr { + *[ram]:2 ldstx_addr = RDsrc:2; +} + + +#la-base-32.txt stx.w mask=0x38180000 [@qemu] +#0x38180000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stx.w RDsrc, ldstx_addr is op15_31=0x7030 & RDsrc & RD32src & ldstx_addr { + *[ram]:4 ldstx_addr = RD32src; +} + + +#la-base-32.txt ldx.bu mask=0x38200000 [@qemu] +#0x38200000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldx.bu RD, ldstx_addr is op15_31=0x7040 & RD & ldstx_addr { + RD = zext(*[ram]:1 ldstx_addr); +} + + +#la-base-32.txt ldx.hu mask=0x38240000 [@qemu] +#0x38240000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldx.hu RD, ldstx_addr is op15_31=0x7048 & RD & ldstx_addr { + RD = zext(*[ram]:2 ldstx_addr); +} + + +#la-base-32.txt dbar mask=0x38720000 [@la32, @primary, @qemu] +#0x38720000 0xffff8000 u0:15 ['imm0_15_s0'] +:dbar imm0_15 is op15_31=0x70e4 & imm0_15 { + local code:2 = imm0_15; + dbar(code); +} + + +#la-base-32.txt ibar mask=0x38728000 [@la32, @primary] +#0x38728000 0xffff8000 u0:15 ['imm0_15_s0'] +:ibar imm0_15 is op15_31=0x70e5 & imm0_15 { + local code:2 = imm0_15; + ibar(code); +} + + +###################### +# Branch Instructions +###################### + + +#la-base-32.txt b mask=0x50000000 [@orig_fmt=Sd10k16ps2, @la32, @primary, @qemu] +#0x50000000 0xfc000000 sb0:10|10:16<<2 ['sbranch0_0_s2'] +:b Rel26 is op26_31=0x14 & Rel26 { + goto Rel26; +} + +#la-base-32.txt bl mask=0x54000000 [@orig_fmt=Sd10k16ps2, @la32, @primary, @qemu] +#0x54000000 0xfc000000 sb0:10|10:16<<2 ['sbranch0_0_s2'] +:bl Rel26 is op26_31=0x15 & Rel26 { + ra = inst_next; + call Rel26; +} + + +#la-base-32.txt beq mask=0x58000000 [@orig_fmt=JDSk16ps2, @la32, @primary, @qemu] +#0x58000000 0xfc000000 r5:5,r0:5,sb10:16<<2 ['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0'] +:beq RDsrc, RJsrc, Rel16 is op26_31=0x16 & RDsrc & RJsrc & Rel16 { + if(RJsrc == RDsrc) goto Rel16; +} + +#la-base-32.txt beqz mask=0x40000000 [@orig_fmt=JSd5k16ps2, @la32] +#0x40000000 0xfc000000 r5:5,sb0:5|10:16<<2 ['reg5_5_s0', 'sbranch0_0_s2'] +:beqz RJsrc, Rel21 is op26_31=0x10 & RJsrc & Rel21 { + if (RJsrc == 0) goto Rel21; +} + + +#la-base-32.txt ble mask=0x64000000 [@orig_name=bge, @orig_fmt=JDSk16ps2, @la32, @primary, @qemu] +#0x64000000 0xfc000000 r5:5,r0:5,sb10:16<<2 ['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0'] +:bge RDsrc, RJsrc, Rel16 is op26_31=0x19 & RDsrc & RJsrc & Rel16 { + if(RJsrc s>= RDsrc) goto Rel16; +} + +:bgez RJsrc, Rel16 is op26_31=0x19 & rD=0 & RJsrc & Rel16 { + if(RJsrc s>= 0) goto Rel16; +} + +:blez RDsrc, Rel16 is op26_31=0x19 & RDsrc & rJ=0 & Rel16 { + if(0 s>= RDsrc) goto Rel16; +} + +#la-base-32.txt bleu mask=0x6c000000 [@orig_name=bgeu, @orig_fmt=JDSk16ps2, @la32, @primary, @qemu] +#0x6c000000 0xfc000000 r5:5,r0:5,sb10:16<<2 ['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0'] +:bgeu RDsrc, RJsrc, Rel16 is op26_31=0x1b & RDsrc & RJsrc & Rel16 { + if(RJsrc >= RDsrc) goto Rel16; +} + + +#la-base-32.txt bgt mask=0x60000000 [@orig_name=blt, @orig_fmt=JDSk16ps2, @la32, @primary, @qemu] +#0x60000000 0xfc000000 r5:5,r0:5,sb10:16<<2 ['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0'] +:blt RDsrc, RJsrc, Rel16 is op26_31=0x18 & RDsrc & RJsrc & Rel16 { + if(RJsrc s< RDsrc) goto Rel16; +} + +:bltz RJsrc, Rel16 is op26_31=0x18 & rD=0 & RJsrc & Rel16 { + if(RJsrc s< 0) goto Rel16; +} + +:bgtz RDsrc, Rel16 is op26_31=0x18 & RDsrc & rJ=0 & Rel16 { + if(0 s< RDsrc) goto Rel16; +} +#la-base-32.txt bgtu mask=0x68000000 [@orig_name=bltu, @orig_fmt=JDSk16ps2, @la32, @primary, @qemu] +#0x68000000 0xfc000000 r5:5,r0:5,sb10:16<<2 ['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0'] +:bltu RDsrc, RJsrc, Rel16 is op26_31=0x1a & RDsrc & RJsrc & Rel16 { + if(RJsrc < RDsrc) goto Rel16; +} + + +#la-base-32.txt bne mask=0x5c000000 [@orig_fmt=JDSk16ps2, @la32, @primary, @qemu] +#0x5c000000 0xfc000000 r5:5,r0:5,sb10:16<<2 ['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0'] +:bne RDsrc, RJsrc, Rel16 is op26_31=0x17 & RDsrc & RJsrc & Rel16 { + if(RJsrc != RDsrc) goto Rel16; +} + +#la-base-32.txt bnez mask=0x44000000 [@orig_fmt=JSd5k16ps2, @la32] +#0x44000000 0xfc000000 r5:5,sb0:5|10:16<<2 ['reg5_5_s0', 'sbranch0_0_s2'] +:bnez RJsrc, Rel21 is op26_31=0x11 & RJsrc & Rel21 { + if (RJsrc != 0) goto Rel21; +} + + +#la-base-32.txt jirl mask=0x4c000000 [@orig_fmt=DJSk16ps2, @la32, @primary, @qemu] +#0x4c000000 0xfc000000 r0:5,r5:5,so10:16<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_16_s0'] +:jirl RD, RelJ16 is op26_31=0x13 & RD & RJsrc & offs16 & RelJ16 { + RD = inst_next; + local addr:$(ADDRSIZE) = RJsrc + (offs16 << 2); + call [RelJ16]; +} + +# alias of jirl zero, ra, 0 +:ret is op26_31=0x13 & rD=0x0 & rJ=0x1 & RJsrc & offs16=0 { + local retAddr = RJsrc; + return [retAddr]; +} + +# alias of jirl zer, rj, 0 +:jr RJsrc is op26_31=0x13 & rD=0x0 & RJsrc & offs16=0 { + local retAddr = RJsrc; + return [retAddr]; +} + + +###################### +# Atomic Instructions +###################### + + +#la-atomics-32.txt ll.w mask=0x20000000 [@orig_fmt=DJSk14ps2, @la32, @primary] +#0x20000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] +#TODO: FIX RELATIVE OFFSET +:ll.w RD, ldstptr_addr is op24_31=0x20 & RD & ldstptr_addr { + local data:4 = *[ram]:4 ldstptr_addr; +@ifdef LA64 + RD = sext(data); +@else + RD = data; +@endif +} + + +#la-atomics-32.txt sc.w mask=0x21000000 [@orig_fmt=DJSk14ps2, @la32, @primary] +#0x21000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] +#TODO: FIX RELATIVE OFFSET +:sc.w RD, ldstptr_addr is op24_31=0x21 & RD & ldstptr_addr { + *[ram]:4 ldstptr_addr = RD:4; +} + + +#la-atomics-32.txt amswap.w mask=0x38600000 [@orig_fmt=DKJ] +#0x38600000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amswap.w RD, RJsrc, RK32src is op15_31=0x70c0 & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = RK32src; +} + + +#la-atomics-32.txt amadd.w mask=0x38610000 [@orig_fmt=DKJ] +#0x38610000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amadd.w RD, RJsrc, RK32src is op15_31=0x70c2 & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (RK32src + val); +} + + +#la-atomics-32.txt amand.w mask=0x38620000 [@orig_fmt=DKJ] +#0x38620000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amand.w RD, RJsrc, RK32src is op15_31=0x70c4 & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (RK32src & val); +} + + +#la-atomics-32.txt amor.w mask=0x38630000 [@orig_fmt=DKJ] +#0x38630000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amor.w RD, RJsrc, RK32src is op15_31=0x70c6 & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (RK32src | val); +} + + +#la-atomics-32.txt amxor.w mask=0x38640000 [@orig_fmt=DKJ] +#0x38640000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amxor.w RD, RJsrc, RK32src is op15_31=0x70c8 & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (RK32src ^ val); +} + + +#la-atomics-32.txt ammax.w mask=0x38650000 [@orig_fmt=DKJ] +#0x38650000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammax.w RD, RJsrc, RK32src is op15_31=0x70ca & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (zext(RK32src s>= val) * RK32src) + (zext(RK32src s< val) * val); +} + + +#la-atomics-32.txt ammin.w mask=0x38660000 [@orig_fmt=DKJ] +#0x38660000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammin.w RD, RJsrc, RK32src is op15_31=0x70cc & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (zext(RK32src s<= val) * RK32src) + (zext(RK32src s> val) * val); +} + + +#la-atomics-32.txt amswap_db.w mask=0x38690000 [@orig_fmt=DKJ] +#0x38690000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amswap_db.w RD, RJsrc, RK32src is op15_31=0x70d2 & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = zext(val); + *[ram]:4 RJsrc = RK32src; +} + + +#la-atomics-32.txt amadd_db.w mask=0x386a0000 [@orig_fmt=DKJ] +#0x386a0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amadd_db.w RD, RJsrc, RK32src is op15_31=0x70d4 & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (RK32src + val); +} + + +#la-atomics-32.txt amand_db.w mask=0x386b0000 [@orig_fmt=DKJ] +#0x386b0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amand_db.w RD, RJsrc, RK32src is op15_31=0x70d6 & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (RK32src & val); +} + + +#la-atomics-32.txt amor_db.w mask=0x386c0000 [@orig_fmt=DKJ] +#0x386c0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amor_db.w RD, RJsrc, RK32src is op15_31=0x70d8 & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (RK32src | val); +} + + +#la-atomics-32.txt amxor_db.w mask=0x386d0000 [@orig_fmt=DKJ] +#0x386d0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amxor_db.w RD, RJsrc, RK32src is op15_31=0x70da & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (RK32src ^ val); +} + + +#la-atomics-32.txt ammax_db.w mask=0x386e0000 [@orig_fmt=DKJ] +#0x386e0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammax_db.w RD, RJsrc, RK32src is op15_31=0x70dc & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (zext(RK32src s>= val) * RK32src) + (zext(RK32src s< val) * val); +} + + +#la-atomics-32.txt ammin_db.w mask=0x386f0000 [@orig_fmt=DKJ] +#0x386f0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammin_db.w RD, RJsrc, RK32src is op15_31=0x70de & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = sext(val); + *[ram]:4 RJsrc = (zext(RK32src s<= val) * RK32src) + (zext(RK32src s> val) * val); +} + + +################################ +# Bit-manipulation Instructions +################################ + + +#la-bitops-32.txt clo.w mask=0x00001000 [@la32] +#0x00001000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:clo.w RD, RJ32src is op10_31=0x4 & RD & RJ32src { + RD = lzcount( ~RJ32src ); +} + + +#la-bitops-32.txt clz.w mask=0x00001400 [@la32, @qemu] +#0x00001400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:clz.w RD, RJ32src is op10_31=0x5 & RD & RJ32src { + RD = lzcount( RJ32src ); +} + + + +#define pcodeop tzcount; +#la-bitops-32.txt cto.w mask=0x00001800 [@la32] +#0x00001800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:cto.w RD, RJ32src is op10_31=0x6 & RD & RJ32src { + local tmp:4 = 0; + tzcount32(~RJ32src, tmp); +@ifdef LA64 + RD = zext(tmp); +@else + RD = tmp; +@endif +} + +#la-bitops-32.txt ctz.w mask=0x00001c00 [@la32, @qemu] +#0x00001c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:ctz.w RD, RJ32src is op10_31=0x7 & RD & RJ32src { + local tmp:4 = 0; + tzcount32(RJ32src, tmp); +@ifdef LA64 + RD = zext(tmp); +@else + RD = tmp; +@endif +} + + +#la-bitops-32.txt revb.2h mask=0x00003000 [@la32, @qemu] +#0x00003000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:revb.2h RD, RJ32src is op10_31=0xc & RD & RJ32src { + tmp0:4 = (zext(RJ32src[0,8]) << 8) + zext(RJ32src[8,8]); + tmp1:4 = (zext(RJ32src[16,8]) << 8) + zext(RJ32src[24,8]); +@ifdef LA64 + RD = sext((tmp1 << 16) + tmp0); +@else + RD = (tmp1 << 16) + tmp0; +@endif +} + + +#la-bitops-32.txt revbit.4b mask=0x00004800 [@orig_name=bitrev.4b, @la32] +#0x00004800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:bitrev.4b RD, RJ32src is op10_31=0x12 & RD & RJ32src { + local v:4 = 0; + byterev32(RJ32src, v); +@ifdef LA64 + RD = sext(v); +@else + RD = v; +@endif +} + + +#la-bitops-32.txt revbit.w mask=0x00005000 [@orig_name=bitrev.w, @la32] +#0x00005000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:bitrev.w RD, RJ32src is op10_31=0x14 & RD & RJ32src { + local v:4 = 0; + bitrev32(RJ32src, v); +@ifdef LA64 + RD = sext(v); +@else + RD = v; +@endif +} + + +#la-bitops-32.txt catpick.w mask=0x00080000 [@orig_name=bytepick.w, @la32] +#0x00080000 0xfffe0000 r0:5,r5:5,r10:5,u15:2 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2_s0'] +:bytepick.w RD, RJ32src, RK32src, imm15_2 is op17_31=0x4 & RD & RJ32src & RK32src & imm15_2 { + local bitstop:1 = 8 * (4 - imm15_2); + local mask:4 = (1 << bitstop) - 1; + local tmp_hi:4 = RK32src & ~mask; + local tmp_lo:4 = (RJ32src & (mask << (32-bitstop)) >> (32-bitstop)); +@ifdef LA64 + RD = sext(tmp_hi + tmp_lo); +@else + RD = tmp_hi + tmp_lo; +@endif +} + +define pcodeop crc.w.b.w; + +#la-bitops-32.txt crc.w.b.w mask=0x00240000 +#0x00240000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:crc.w.b.w RD, RJ32src, RK32src is op15_31=0x48 & RD & RJ32src & RK32src { + local val:1 = RJ32src(0); + RD = crc_ieee802.3(RK32src, val, 16:1, 0xedb88320:4); +} + +define pcodeop crc.w.h.w; + +#la-bitops-32.txt crc.w.h.w mask=0x00248000 +#0x00248000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:crc.w.h.w RD, RJ32src, RK32src is op15_31=0x49 & RD & RJ32src & RK32src { + local val:2 = RJ32src(0); + RD = crc_ieee802.3(RK32src, val, 16:1, 0xedb88320:4); +} + +define pcodeop crc.w.w.w; + +#la-bitops-32.txt crc.w.w.w mask=0x00250000 +#0x00250000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:crc.w.w.w RD, RJ32src, RK32src is op15_31=0x4a & RD & RJ32src & RK32src { + RD = crc_ieee802.3(RK32src, RJ32src, 32:1, 0xedb88320:4); +} + +define pcodeop crcc.w.b.w; + +#la-bitops-32.txt crcc.w.b.w mask=0x00260000 +#0x00260000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:crcc.w.b.w RD, RJ32src, RK32src is op15_31=0x4c & RD & RJ32src & RK32src { + local val:1 = RJ32src(0); + RD = crc_castagnoli(RK32src, val, 8:1, 0x82f63b78:4); +} + +define pcodeop crcc.w.h.w; + +#la-bitops-32.txt crcc.w.h.w mask=0x00268000 +#0x00268000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:crcc.w.h.w RD, RJ32src, RK32src is op15_31=0x4d & RD & RJ32src & RK32src { + local val:2 = RJ32src(0); + RD = crc_castagnoli(RK32src, val, 16:1, 0x82f63b78:4); +} + +define pcodeop crcc.w.w.w; + +#la-bitops-32.txt crcc.w.w.w mask=0x00270000 +#0x00270000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:crcc.w.w.w RD, RJ32src, RK32src is op15_31=0x4e & RD & RJ32src & RK32src { + RD = crc_castagnoli(RK32src, RJ32src, 32:1, 0x82f63b78:4); +} + +define pcodeop bstrins.w; + +#la-bitops-32.txt bstrins.w mask=0x00600000 [@orig_fmt=DJUm5Uk5, @la32, @qemu] +#0x00600000 0xffe08000 r0:5,r5:5,u16:5,u10:5 ['reg0_5_s0', 'reg5_5_s0', 'imm16_5_s0', 'imm10_5_s0'] +:bstrins.w RD, RJ32src, imm16_5, imm10_5 is op21_31=0x3 & op15_15=0x0 & RD & RD32 & RJ32src & imm10_5 & imm16_5 { + local msb:1 = imm16_5; + local lsb:1 = imm10_5; + local len:1 = msb + 1 - lsb; + local mask:4 = (1 << len) - 1; + local repl:4 = (RJ32src & (mask << lsb)) >> lsb; +@ifdef LA64 + RD = sext((RD32 & (~mask)) | repl); +@else + RD = (RD & (~mask)) | repl; +@endif +} + + +#la-bitops-32.txt bstrpick.w mask=0x00608000 [@orig_fmt=DJUm5Uk5, @la32, @qemu] +#0x00608000 0xffe08000 r0:5,r5:5,u16:5,u10:5 ['reg0_5_s0', 'reg5_5_s0', 'imm16_5_s0', 'imm10_5_s0'] +:bstrpick.w RD, RJ32src, imm16_5, imm10_5, is op21_31=0x3 & op15_15=0x1 & RD & RJ32src & imm10_5 & imm16_5 { + local msb:1 = imm16_5; + local lsb:1 = imm10_5; + local len:1 = msb + 1 - lsb; + local mask:4 = (1 << len) - 1; + local repl:4 = (RJ32src & (mask << lsb)) >> lsb; +@ifdef LA64 + RD = sext(repl); +@else + RD = repl; +@endif +} + + +############################### +# Bounds-checking Instructions +############################### + + +#la-bound.txt asrtle mask=0x00010000 [@orig_name=asrtle.d] +#0x00010000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:asrtle.d RJsrc, RKsrc is op15_31=0x2 & op0_4=0x0 & RJsrc & RKsrc { + if (RJsrc <= RKsrc) goto ; + addr_bound_exception(RJsrc, RKsrc); + +} + +#la-bound.txt asrtgt mask=0x00018000 [@orig_name=asrtgt.d] +#0x00018000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:asrtgt.d RJsrc, RKsrc is op15_31=0x3 & op0_4=0x0 & RJsrc & RKsrc { + if (RJsrc > RKsrc) goto ; + addr_bound_exception(RJsrc, RKsrc); + +} + + +#la-bound.txt ldgt.b mask=0x38780000 +#0x38780000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldgt.b RD, RJsrc, RKsrc is op15_31=0x70f0 & RD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + RD = sext(*[ram]:1 vaddr); + +} + +#la-bound.txt ldgt.h mask=0x38788000 +#0x38788000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldgt.h RD, RJsrc, RKsrc is op15_31=0x70f1 & RD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + RD = sext(*[ram]:2 vaddr); + +} + +#la-bound.txt ldgt.w mask=0x38790000 +#0x38790000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldgt.w RD, RJsrc, RKsrc is op15_31=0x70f2 & RD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + RD = sext(*[ram]:4 vaddr); + +} + + +#la-bound.txt ldle.b mask=0x387a0000 +#0x387a0000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldle.b RD, RJsrc, RKsrc is op15_31=0x70f4 & RD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + RD = sext(*[ram]:1 vaddr); + +} + +#la-bound.txt ldle.h mask=0x387a8000 +#0x387a8000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldle.h RD, RJsrc, RKsrc is op15_31=0x70f5 & RD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + RD = sext(*[ram]:2 vaddr); + +} + +#la-bound.txt ldle.w mask=0x387b0000 +#0x387b0000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldle.w RD, RJsrc, RKsrc is op15_31=0x70f6 & RD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + RD = sext(*[ram]:4 vaddr); + +} + + +#la-bound.txt stgt.b mask=0x387c0000 +#0x387c0000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stgt.b RDsrc, RJsrc, RKsrc is op15_31=0x70f8 & RDsrc & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(vaddr, RKsrc); + goto ; + + *[ram]:1 RJsrc = RDsrc:1; + +} + +#la-bound.txt stgt.h mask=0x387c8000 +#0x387c8000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stgt.h RDsrc, RJsrc, RKsrc is op15_31=0x70f9 & RDsrc & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(vaddr, RKsrc); + goto ; + + *[ram]:2 vaddr = RDsrc:2; + +} + +#la-bound.txt stgt.w mask=0x387d0000 +#0x387d0000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stgt.w RDsrc, RJsrc, RKsrc is op15_31=0x70fa & RDsrc & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:4 vaddr = RDsrc:4; + +} + +#la-bound.txt stle.b mask=0x387e0000 +#0x387e0000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stle.b RDsrc, RJsrc, RKsrc is op15_31=0x70fc & RDsrc & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:1 vaddr = RDsrc:1; + +} + +#la-bound.txt stle.h mask=0x387e8000 +#0x387e8000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stle.h RDsrc, RJsrc, RKsrc is op15_31=0x70fd & RDsrc & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:2 vaddr = RDsrc:2; + +} + +#la-bound.txt stle.w mask=0x387f0000 +#0x387f0000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stle.w RDsrc, RJsrc, RKsrc is op15_31=0x70fe & RDsrc & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:4 vaddr = RDsrc:4; + +} + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc new file mode 100644 index 0000000000..15859141ed --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc @@ -0,0 +1,730 @@ +################### +# Base Instructions +################### + +#la-base-64.txt add.d mask=0x00108000 [@qemu] +#0x00108000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:add.d RD, RJsrc, RKsrc is op15_31=0x21 & RD & RJsrc & RKsrc { + RD = RJsrc + RKsrc; +} + +#la-base-64.txt addi.d mask=0x02c00000 [@qemu] +#0x02c00000 0xffc00000 r0:5,r5:5,s10:12 ['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] +:addi.d RD, RJsrc,simm10_12 is op22_31=0xb & RD & RJsrc & simm10_12 { + RD = RJsrc + simm10_12; +} + +#la-base-64.txt addu16i.d mask=0x10000000 [@qemu] +#0x10000000 0xfc000000 r0:5,r5:5,s10:16 ['reg0_5_s0', 'reg5_5_s0', 'simm10_16_s0'] +:addu16i.d RD, RJsrc, addu16_imm is op26_31=0x4 & RD & RJsrc & addu16_imm { + RD = RJsrc + addu16_imm; +} + + +#la-bitops-64.txt sladd.d mask=0x002c0000 [@orig_name=alsl.d, @orig_fmt=DJKUa2pp1] +#0x002c0000 0xfffe0000 r0:5,r5:5,r10:5,u15:2+1 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0'] +:alsl.d RD, RJsrc, RKsrc, alsl_shift is op17_31=0x16 & RD & RJsrc & RKsrc & alsl_shift { + RD = (RJsrc << alsl_shift) + RKsrc; +} + +#la-bitops-64.txt sladd.wu mask=0x00060000 [@orig_name=alsl.wu, @orig_fmt=DJKUa2pp1] +#0x00060000 0xfffe0000 r0:5,r5:5,r10:5,u15:2+1 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0'] +:alsl.wu RD, RJ32src, RK32src, alsl_shift is op17_31=0x3 & RD & RJ32src & RK32src & alsl_shift { + local result:4 = (RJ32src << alsl_shift) + RK32src; +@ifdef LA64 + RD = zext(result); +@else + RD = result; +@endif +} + + +#la-mul-64.txt div.d mask=0x00220000 [@qemu] +#0x00220000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:div.d RD, RJsrc, RKsrc is op15_31=0x44 & RD & RJsrc & RKsrc { + RD = RJsrc s/ RKsrc; +} + + + + +#la-mul-64.txt div.du mask=0x00230000 [@qemu] +#0x00230000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:div.du RD, RJsrc, RKsrc is op15_31=0x46 & RD & RJsrc & RKsrc { + RD = RJsrc / RKsrc; +} + + +#la-mul-64.txt mod.d mask=0x00228000 [@qemu] +#0x00228000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mod.d RD, RJsrc, RKsrc is op15_31=0x45 & RD & RJsrc & RKsrc { + RD = RJsrc s% RKsrc; +} + +#la-mul-64.txt mod.du mask=0x00238000 [@qemu] +#0x00238000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mod.du RD, RJsrc, RKsrc is op15_31=0x47 & RD & RJsrc & RKsrc { + RD = RJsrc % RKsrc; +} + + +#la-mul-64.txt mul.d mask=0x001d8000 [@qemu] +#0x001d8000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mul.d RD, RJsrc, RKsrc is op15_31=0x3b & RD & RJsrc & RKsrc { + tmp1:16 = sext( RJsrc ); + tmp2:16 = sext( RKsrc ); + prod:16 = tmp1 * tmp2; + RD = prod:8; +} + +#la-mul-64.txt mulh.d mask=0x001e0000 [@qemu] +#0x001e0000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mulh.d RD, RJsrc, RKsrc is op15_31=0x3c & RD & RJsrc & RKsrc { + tmp1:16 = sext( RJsrc ); + tmp2:16 = sext( RKsrc ); + prod:16 = tmp1 * tmp2; + prod = prod >> 64; + RD = prod:8; +} + +#la-mul-64.txt mulh.du mask=0x001e8000 [@qemu] +#0x001e8000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mulh.du RD, RJsrc, RKsrc is op15_31=0x3d & RD & RJsrc & RKsrc { + tmp1:16 = zext( RJsrc ); + tmp2:16 = zext( RKsrc ); + prod:16 = tmp1 * tmp2; + prod = prod >> 64; + RD = prod:8; +} + + +#la-mul-64.txt mulw.d.w mask=0x001f0000 +#0x001f0000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mulw.d.w RD, RJ32src, RK32src is op15_31=0x3e & RD & RJ32src & RK32src { + tmp1:8 = sext( RJ32src ); + tmp2:8 = sext( RK32src ); + prod:8 = tmp1 * tmp2; + RD = prod; +} + +#la-mul-64.txt mulw.d.wu mask=0x001f8000 +#0x001f8000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:mulw.d.wu RD, RJ32src, RK32src is op15_31=0x3f & RD & RJ32src & RK32src { + tmp1:8 = zext( RJ32src ); + tmp2:8 = zext( RK32src ); + prod:8 = tmp1 * tmp2; + RD = prod; +} + + +#la-base-64.txt rdtime.d mask=0x00006800 +#0x00006800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:rdtime.d RD, RJ is op10_31=0x1a & RD & RJ { + local tmp:1 = 2; + RD = rdtime.counter(tmp); + RJ = rdtime.counterid(tmp); +} + + +#la-base-64.txt rotr.d mask=0x001b8000 [@qemu] +#0x001b8000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:rotr.d RD, RJsrc, RKsrc is op15_31=0x37 & RD & RJsrc & RKsrc { + local shift:1 = RKsrc(0) & 0x3f; + local tmp1:8 = RJsrc s>> shift; + local tmp2:8 = RJsrc << (64 - shift); + RD = tmp1 + tmp2; +} + +#la-base-64.txt rotri.d mask=0x004d0000 [@qemu] +#0x004d0000 0xffff0000 r0:5,r5:5,u10:6 ['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0'] +:rotri.d RD, RJsrc, imm10_6 is op16_31=0x4d & RD & RJsrc & imm10_6 { + local shift:1 = imm10_6 & 0x3f; + local tmp1:8 = RJsrc s>> shift; + local tmp2:8 = RJsrc << (64 - shift); + RD = tmp1 + tmp2; +} + + +#la-base-64.txt sll.d mask=0x00188000 [@qemu] +#0x00188000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sll.d RD, RJsrc, RKsrc is op15_31=0x31 & RD & RJsrc & RKsrc { + local shift:1 = RKsrc(0) & 0x3f; + RD = RJsrc << shift; +} + +#la-base-64.txt slli.d mask=0x00410000 [@qemu] +#0x00410000 0xffff0000 r0:5,r5:5,u10:6 ['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0'] +:slli.d RD, RJsrc, imm10_6 is op16_31=0x41 & RD & RJsrc & imm10_6 { + local shift:1 = imm10_6 & 0x1f; + RD = RJsrc << shift; +} + + +#la-base-64.txt sra.d mask=0x00198000 [@qemu] +#0x00198000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sra.d RD, RJsrc, RKsrc is op15_31=0x33 & RD & RJsrc & RKsrc { + local shift:1 = RKsrc(0) & 0x3f; + RD = RJsrc s>> shift; +} + +#la-base-64.txt srai.d mask=0x00490000 [@qemu] +#0x00490000 0xffff0000 r0:5,r5:5,u10:6 ['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0'] +:srai.d RD, RJsrc, imm10_6 is op16_31=0x49 & RD & RJsrc & imm10_6 { + local shift:1 = imm10_6 & 0x1f; + RD = RJsrc s>> shift; +} + + +#la-base-64.txt srl.d mask=0x00190000 [@qemu] +#0x00190000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:srl.d RD, RJsrc, RKsrc is op15_31=0x32 & RD & RJsrc & RKsrc { + local shift:1 = RKsrc(0) & 0x3f; + RD = RJsrc >> shift; +} + +#la-base-64.txt srli.d mask=0x00450000 [@qemu] +#0x00450000 0xffff0000 r0:5,r5:5,u10:6 ['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0'] +:srli.d RD, RJsrc, imm10_6 is op16_31=0x45 & RD & RJsrc & imm10_6 { + local shift:1 = imm10_6 & 0x1f; + RD = RJsrc >> shift; +} + + +#la-base-64.txt sub.d mask=0x00118000 [@qemu] +#0x00118000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sub.d RD, RJsrc, RKsrc is op15_31=0x23 & RD & RJsrc & RKsrc { + RD = RJsrc - RKsrc; +} + + +########################## +# Load/Store Instructions +########################## + + +#la-base-64.txt cu52i.d mask=0x03000000 [@orig_name=lu52i.d, @qemu] +#0x03000000 0xffc00000 r0:5,r5:5,s10:12 ['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] +:lu52i.d RD, RJsrc, simm10_12 is op22_31=0xc & RD & RJsrc & simm10_12 { + local simm52i:$(REGSIZE) = (simm10_12 << 52) + (RJsrc & 0xfffffffffffff); + RD = simm52i; +} + + +#la-base-64.txt cu32i.d mask=0x16000000 [@orig_name=lu32i.d, @qemu] +#0x16000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] +:lu32i.d RD, simm5_20 is op25_31=0xb & RD & RD32 & simm5_20 { + RD = (simm5_20 << 32) + zext(RD32); +} + + +#la-base-64.txt ldox4.d mask=0x26000000 [@orig_name=ldptr.d, @orig_fmt=DJSk14ps2] +#0x26000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] +:ldptr.d RD, ldstptr_addr is op24_31=0x26 & RD & ldstptr_addr { + RD = *[ram]:8 ldstptr_addr; +} + + +#la-base-64.txt stox4.d mask=0x27000000 [@orig_name=stptr.d, @orig_fmt=DJSk14ps2] +#0x27000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] +:stptr.d RDsrc, ldstptr_addr is op24_31=0x27 & RDsrc & ldstptr_addr { + *[ram]:8 ldstptr_addr = RDsrc; +} + + +#la-base-64.txt ld.d mask=0x28c00000 [@qemu] +#0x28c00000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:ld.d RD, ldst_addr is op22_31=0xa3 & RD & ldst_addr { + RD = *[ram]:8 ldst_addr; +} + + +#la-base-64.txt st.d mask=0x29c00000 [@qemu] +#0x29c00000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:st.d RDsrc, ldst_addr is op22_31=0xa7 & RDsrc & ldst_addr { + *[ram]:8 ldst_addr = RDsrc; +} + + +#la-base-64.txt ld.wu mask=0x2a800000 [@qemu] +#0x2a800000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:ld.wu RD, ldst_addr is op22_31=0xaa & RD & ldst_addr { + RD = zext(*[ram]:4 ldst_addr); +} + + +#la-base-64.txt ldx.d mask=0x380c0000 [@qemu] +#0x380c0000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldx.d RD, ldstx_addr is op15_31=0x7018 & RD & ldstx_addr { + RD = *[ram]:8 ldstx_addr; +} + + +#la-base-64.txt stx.d mask=0x381c0000 [@qemu] +#0x381c0000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stx.d RDsrc, ldstx_addr is op15_31=0x7038 & RDsrc & ldstx_addr { + *[ram]:8 ldstx_addr = RDsrc; +} + + +#la-base-64.txt ldx.wu mask=0x38280000 [@qemu] +#0x38280000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldx.wu RD, ldstx_addr is op15_31=0x7050 & RD & ldstx_addr { + RD = zext(*[ram]:4 ldstx_addr); +} + + +###################### +# Atomic Instructions +###################### + + +#la-atomics-64.txt ll.d mask=0x22000000 [@orig_fmt=DJSk14ps2] +#0x22000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] +#TODO: FIX RELATIVE OFFSET +:ll.d RD, ldstptr_addr is op24_31=0x22 & RD & ldstptr_addr { + RD = *[ram]:8 ldstptr_addr; +} + + +#la-atomics-64.txt sc.d mask=0x23000000 [@orig_fmt=DJSk14ps2] +#0x23000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] +#TODO: FIX RELATIVE OFFSET +:sc.d RD, ldstptr_addr is op24_31=0x23 & RD & ldstptr_addr { + *[ram]:8 ldstptr_addr = RD; +} + + +#la-atomics-64.txt amswap.d mask=0x38608000 [@orig_fmt=DKJ] +#0x38608000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amswap.d RD, RJsrc, RKsrc is op15_31=0x70c1 & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = RKsrc; +} + + +#la-atomics-64.txt amadd.d mask=0x38618000 [@orig_fmt=DKJ] +#0x38618000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amadd.d RD, RJsrc, RKsrc is op15_31=0x70c3 & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (RKsrc + val); +} + + +#la-atomics-64.txt amand.d mask=0x38628000 [@orig_fmt=DKJ] +#0x38628000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amand.d RD, RJsrc, RKsrc is op15_31=0x70c5 & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (RKsrc & val); +} + + +#la-atomics-64.txt amor.d mask=0x38638000 [@orig_fmt=DKJ] +#0x38638000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amor.d RD, RJsrc, RKsrc is op15_31=0x70c7 & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (RKsrc | val); +} + + +#la-atomics-64.txt amxor.d mask=0x38648000 [@orig_fmt=DKJ] +#0x38648000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amxor.d RD, RJsrc, RKsrc is op15_31=0x70c9 & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (RKsrc ^ val); +} + + +#la-atomics-64.txt ammax.d mask=0x38658000 [@orig_fmt=DKJ] +#0x38658000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammax.d RD, RJsrc, RKsrc is op15_31=0x70cb & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (zext(RKsrc s>= val) * RKsrc) + (zext(RKsrc s< val) * val); +} + + +#la-atomics-64.txt ammin.d mask=0x38668000 [@orig_fmt=DKJ] +#0x38668000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammin.d RD, RJsrc, RKsrc is op15_31=0x70cd & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (zext(RKsrc s<= val) * RKsrc) + (zext(RKsrc s> val) * val); +} + + +#la-atomics-64.txt ammax.wu mask=0x38670000 [@orig_fmt=DKJ] +#0x38670000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammax.wu RD, RJsrc, RK32src is op15_31=0x70ce & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = zext(val); + *[ram]:4 RJsrc = (zext(RK32src >= val) * RK32src) + (zext(RK32src < val) * val); +} + + +#la-atomics-64.txt ammax.du mask=0x38678000 [@orig_fmt=DKJ] +#0x38678000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammax.du RD, RJsrc, RKsrc is op15_31=0x70cf & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (zext(RKsrc >= val) * RKsrc) + (zext(RKsrc < val) * val); +} + + +#la-atomics-64.txt ammin.wu mask=0x38680000 [@orig_fmt=DKJ] +#0x38680000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammin.wu RD, RJsrc, RK32src is op15_31=0x70d0 & RD & RJsrc & RK32src { + local val:4 = *[ram]:4 RJsrc; + RD = zext(val); + *[ram]:4 RJsrc = (zext(RK32src <= val) * RK32src) + (zext(RK32src > val) * val); +} + + +#la-atomics-64.txt ammin.du mask=0x38688000 [@orig_fmt=DKJ] +#0x38688000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammin.du RD, RJsrc, RKsrc is op15_31=0x70d1 & RD & RJsrc & RKsrc { + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (zext(RKsrc <= val) * RKsrc) + (zext(RKsrc > val) * val); +} + + +#la-atomics-64.txt amswap_db.d mask=0x38698000 [@orig_fmt=DKJ] +#0x38698000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amswap_db.d RD, RJsrc, RKsrc is op15_31=0x70d3 & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = RKsrc; +} + + +#la-atomics-64.txt amadd_db.d mask=0x386a8000 [@orig_fmt=DKJ] +#0x386a8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amadd_db.d RD, RJsrc, RKsrc is op15_31=0x70d5 & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (RKsrc + val); +} + + +#la-atomics-64.txt amand_db.d mask=0x386b8000 [@orig_fmt=DKJ] +#0x386b8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amand_db.d RD, RJsrc, RKsrc is op15_31=0x70d7 & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (RKsrc & val); +} + + +#la-atomics-64.txt amor_db.d mask=0x386c8000 [@orig_fmt=DKJ] +#0x386c8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amor_db.d RD, RJsrc, RKsrc is op15_31=0x70d9 & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (RKsrc | val); +} + + +#la-atomics-64.txt amxor_db.d mask=0x386d8000 [@orig_fmt=DKJ] +#0x386d8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:amxor_db.d RD, RJsrc, RKsrc is op15_31=0x70db & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (RKsrc ^ val); +} + + +#la-atomics-64.txt ammax_db.d mask=0x386e8000 [@orig_fmt=DKJ] +#0x386e8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammax_db.d RD, RJsrc, RKsrc is op15_31=0x70dd & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (zext(RKsrc s>= val) * RKsrc) + (zext(RKsrc s< val) * val); +} + + +#la-atomics-64.txt ammin_db.d mask=0x386f8000 [@orig_fmt=DKJ] +#0x386f8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammin_db.d RD, RJsrc, RKsrc is op15_31=0x70df & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (zext(RKsrc s<= val) * RKsrc) + (zext(RKsrc s> val) * val); +} + + +#la-atomics-64.txt ammax_db.wu mask=0x38700000 [@orig_fmt=DKJ] +#0x38700000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammax_db.wu RD, RJsrc, RK32src is op15_31=0x70e0 & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = zext(val); + *[ram]:4 RJsrc = (zext(RK32src >= val) * RK32src) + (zext(RK32src < val) * val); +} + + +#la-atomics-64.txt ammax_db.du mask=0x38708000 [@orig_fmt=DKJ] +#0x38708000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammax_db.du RD, RJsrc, RKsrc is op15_31=0x70e1 & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (zext(RKsrc >= val) * RKsrc) + (zext(RKsrc < val) * val); +} + + +#la-atomics-64.txt ammin_db.wu mask=0x38710000 [@orig_fmt=DKJ] +#0x38710000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammin_db.wu RD, RJsrc, RK32src is op15_31=0x70e2 & RD & RJsrc & RK32src { + dbar(0:1); + local val:4 = *[ram]:4 RJsrc; + RD = zext(val); + *[ram]:4 RJsrc = (zext(RK32src <= val) * RK32src) + (zext(RK32src > val) * val); +} + + +#la-atomics-64.txt ammin_db.du mask=0x38718000 [@orig_fmt=DKJ] +#0x38718000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] +:ammin_db.du RD, RJsrc, RKsrc is op15_31=0x70e3 & RD & RJsrc & RKsrc { + dbar(0:1); + local val:8 = *[ram]:8 RJsrc; + RD = val; + *[ram]:8 RJsrc = (zext(RKsrc <= val) * RKsrc) + (zext(RKsrc > val) * val); +} + + +################################ +# Bit-manipulation Instructions +################################ + + +#la-bitops-64.txt clo.d mask=0x00002000 +#0x00002000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:clo.d RD, RJsrc is op10_31=0x8 & RD & RJsrc { + RD = lzcount( ~RJsrc ); +} + + +#la-bitops-64.txt clz.d mask=0x00002400 [@qemu] +#0x00002400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:clz.d RD, RJsrc is op10_31=0x9 & RD & RJsrc { + RD = lzcount( RJsrc ); +} + + +#la-bitops-64.txt cto.d mask=0x00002800 +#0x00002800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:cto.d RD, RJsrc is op10_31=0xa & RD & RJsrc { + local tmp:8 = 0; + tzcount64(~RJsrc, tmp); + RD = tmp; +} + + +#la-bitops-64.txt ctz.d mask=0x00002c00 [@qemu] +#0x00002c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:ctz.d RD, RJsrc is op10_31=0xb & RD & RJsrc { + local tmp:8 = 0; + tzcount64(RJsrc, tmp); + RD = tmp; +} + + +#la-bitops-64.txt revb.4h mask=0x00003400 +#0x00003400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:revb.4h RD, RJsrc is op10_31=0xd & RD & RJsrc { + tmp0:8 = (zext(RJsrc[0,8]) << 8) + zext(RJsrc[8,8]); + tmp1:8 = (zext(RJsrc[16,8]) << 8) + zext(RJsrc[24,8]); + tmp2:8 = (zext(RJsrc[32,8]) << 8) + zext(RJsrc[40,8]); + tmp3:8 = (zext(RJsrc[48,8]) << 8) + zext(RJsrc[56,8]); + + RD = (tmp3 << 48) + (tmp2 << 32) + (tmp1 << 16) + tmp0; +} + + +#la-bitops-64.txt revb.2w mask=0x00003800 [@qemu] +#0x00003800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:revb.2w RD, RJsrc is op10_31=0xe & RD & RJsrc { + tmp0:8 = (zext(RJsrc[0,8]) << 24) + (zext(RJsrc[8,8]) << 16) + (zext(RJsrc[16,8]) << 8) + zext(RJsrc[24,8]); + tmp1:8 = (zext(RJsrc[32,8]) << 24) + (zext(RJsrc[40,8]) << 16) + (zext(RJsrc[48,8]) << 8) + zext(RJsrc[56,8]); + + RD = (tmp1 << 32) + tmp0; +} + + +#la-bitops-64.txt revb.d mask=0x00003c00 [@qemu] +#0x00003c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:revb.d RD, RJsrc is op10_31=0xf & RD & RJsrc { + tmp0:8 = zext(RJsrc[0,8]); + tmp1:8 = zext(RJsrc[8,8]); + tmp2:8 = zext(RJsrc[16,8]); + tmp3:8 = zext(RJsrc[24,8]); + tmp4:8 = zext(RJsrc[32,8]); + tmp5:8 = zext(RJsrc[40,8]); + tmp6:8 = zext(RJsrc[48,8]); + tmp7:8 = zext(RJsrc[56,8]); + + RD = (tmp0 << 56) + (tmp1 << 48) + (tmp2 << 40) + (tmp3 << 32) + (tmp4 << 24) + (tmp5 << 16) + (tmp6 << 8) + tmp7; +} + + +#la-bitops-64.txt revh.2w mask=0x00004000 +#0x00004000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:revh.2w RD, RJsrc is op10_31=0x10 & RD & RJsrc { + tmp0:8 = (zext(RJsrc[0,16]) << 16) + zext(RJsrc[16,16]); + tmp1:8 = (zext(RJsrc[32,16]) << 8) + zext(RJsrc[48,16]); + + RD = (tmp1 << 32) + tmp0; +} + + +#la-bitops-64.txt revh.d mask=0x00004400 +#0x00004400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:revh.d RD, RJsrc is op10_31=0x11 & RD & RJsrc { + tmp0:8 = zext(RJsrc[0,16]); + tmp1:8 = zext(RJsrc[16,16]); + tmp2:8 = zext(RJsrc[32,16]); + tmp3:8 = zext(RJsrc[48,16]); + + RD = (tmp3 << 48) + (tmp2 << 32) + (tmp1 << 16) + tmp0; +} + + +#la-bitops-64.txt revbit.8b mask=0x00004c00 [@orig_name=bitrev.8b] +#0x00004c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:bitrev.8b RD, RJsrc is op10_31=0x13 & RD & RJsrc { + local v:8 = 0; + byterev64(RJsrc, v); + RD = v; +} + + +#la-bitops-64.txt revbit.d mask=0x00005400 [@orig_name=bitrev.d] +#0x00005400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:bitrev.d RD, RJsrc is op10_31=0x15 & RD & RJsrc { + local v:8 = 0; + bitrev64(RJsrc, v); + RD = v; +} + +define pcodeop bytepick.d; + +#la-bitops-64.txt catpick.d mask=0x000c0000 [@orig_name=bytepick.d] +#0x000c0000 0xfffc0000 r0:5,r5:5,r10:5,u15:3 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_3_s0'] +:bytepick.d RD, RJsrc, RKsrc, imm15_3 is op18_31=0x3 & RD & RJsrc & RKsrc & imm15_3 { + local bitstop:1 = 8 * (8 - imm15_3); + local mask:8 = (1 << bitstop) - 1; + local tmp_hi:8 = RKsrc & ~mask; + local tmp_lo:8 = (RJsrc & (mask << (64-bitstop)) >> (64-bitstop)); + RD = tmp_hi + tmp_lo; +} + +define pcodeop crc.w.d.w; + +#la-bitops-64.txt crc.w.d.w mask=0x00258000 +#0x00258000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:crc.w.d.w RD, RJsrc, RKsrc is op15_31=0x4b & RD & RJsrc & RKsrc { + RD = crc_ieee802.3(RKsrc, RJsrc, 64:1, 0xedb88320:4); +} + +define pcodeop crcc.w.d.w; + +#la-bitops-64.txt crcc.w.d.w mask=0x00278000 +#0x00278000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:crcc.w.d.w RD, RJsrc, RKsrc is op15_31=0x4f & RD & RJsrc & RKsrc { + RD = crc_castagnoli(RKsrc, RJsrc, 64:1, 0x82f63b78:4); +} + + +#la-bitops-64.txt bstrins.d mask=0x00800000 [@orig_fmt=DJUm6Uk6, @qemu] +#0x00800000 0xffc00000 r0:5,r5:5,u16:6,u10:6 ['reg0_5_s0', 'reg5_5_s0', 'imm16_6_s0', 'imm10_6_s0'] +:bstrins.d RD, RJsrc, imm16_6, imm10_6 is op22_31=0x2 & RD & RJsrc & imm10_6 & imm16_6 { + local msb:1 = imm16_6; + local lsb:1 = imm10_6; + local len:1 = msb + 1 - lsb; + local mask:8 = (1 << len) - 1; + local repl:8 = (RJsrc & (mask << lsb)) >> lsb; + + RD = (RD & (~mask)) | repl; +} + + +#la-bitops-64.txt bstrpick.d mask=0x00c00000 [@orig_fmt=DJUm6Uk6, @qemu] +#0x00c00000 0xffc00000 r0:5,r5:5,u16:6,u10:6 ['reg0_5_s0', 'reg5_5_s0', 'imm16_6_s0', 'imm10_6_s0'] +:bstrpick.d RD, RJsrc, imm16_6, imm10_6 is op22_31=0x3 & RD & RJsrc & imm10_6 & imm16_6 { + local msb:1 = imm16_6; + local lsb:1 = imm10_6; + local len:1 = msb + 1 - lsb; + local mask:8 = (1 << len) - 1; + local repl:8 = (RJsrc & (mask << lsb)) >> lsb; + + RD = repl; +} + + +############################### +# Bounds-checking Instructions +############################### + + +#la-bound-64.txt ldgt.d mask=0x38798000 +#0x38798000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldgt.d RD, RJsrc, RKsrc is op15_31=0x70f3 & RD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + RD = sext(*[ram]:8 vaddr); + +} + +#la-bound-64.txt ldle.d mask=0x387b8000 +#0x387b8000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:ldle.d RD, RJsrc, RKsrc is op15_31=0x70f7 & RD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + RD = sext(*[ram]:1 vaddr); + +} + + +#la-bound-64.txt stgt.d mask=0x387d8000 +#0x387d8000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stgt.d RDsrc, RJsrc, RKsrc is op15_31=0x70fb & RDsrc & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:8 vaddr = RDsrc:8; + +} + +#la-bound-64.txt stle.d mask=0x387f8000 +#0x387f8000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:stle.d RDsrc, RJsrc, RKsrc is op15_31=0x70ff & RDsrc & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:8 vaddr = RDsrc:8; + +} + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc new file mode 100644 index 0000000000..adc639eb1e --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc @@ -0,0 +1,387 @@ + + + +#la-fp-d.txt fadd.d mask=0x01010000 +#0x01010000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fadd.d drD, drJ, drK is op15_31=0x202 & drD & drJ & drK { + drD = drJ f+ drK; +} + + +#la-fp-d.txt fsub.d mask=0x01030000 +#0x01030000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fsub.d drD, drJ, drK is op15_31=0x206 & drD & drJ & drK { + drD = drJ f- drK; +} + + +#la-fp-d.txt fmul.d mask=0x01050000 +#0x01050000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmul.d drD, drJ, drK is op15_31=0x20a & drD & drJ & drK { + drD = drJ f* drK; +} + + +#la-fp-d.txt fdiv.d mask=0x01070000 +#0x01070000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fdiv.d drD, drJ, drK is op15_31=0x20e & drD & drJ & drK { + drD = drJ f/ drK; +} + + +#la-fp-d.txt fmax.d mask=0x01090000 +#0x01090000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmax.d drD, drJ, drK is op15_31=0x212 & drD & drJ & drK { + local jval = drJ; + local kval = drK; + drD = (zext(jval f>= kval) * jval) + (zext(jval f< kval) * jval); +} + + +#la-fp-d.txt fmin.d mask=0x010b0000 +#0x010b0000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmin.d drD, drJ, drK is op15_31=0x216 & drD & drJ & drK { + local jval = drJ; + local kval = drK; + drD = (zext(jval f<= kval) * jval) + (zext(jval f> kval) * jval); +} + + +#la-fp-d.txt fmaxa.d mask=0x010d0000 +#0x010d0000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmaxa.d drD, drJ, drK is op15_31=0x21a & drD & drJ & drK { + local jval = drJ; + local kval = drK; + drD = (zext(abs(jval) f>= abs(kval)) * jval) + (zext(abs(jval) f< abs(kval)) * jval); +} + + +#la-fp-d.txt fmina.d mask=0x010f0000 +#0x010f0000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmina.d drD, drJ, drK is op15_31=0x21e & drD & drJ & drK { + local jval = drJ; + local kval = drK; + drD = (zext(abs(jval) f<= abs(kval)) * jval) + (zext(abs(jval) f> abs(kval)) * jval); +} + + +#la-fp-d.txt fscaleb.d mask=0x01110000 +#0x01110000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fscaleb.d drD, drJ, drK is op15_31=0x222 & drD & drJ & drK { + drD = f_scaleb(drJ, drK); +} + + +#la-fp-d.txt fcopysign.d mask=0x01130000 +#0x01130000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fcopysign.d drD, drJ, drK is op15_31=0x226 & drD & drJ & drK { + local kval = drK; + drD = drJ f* (kval/abs(kval)); +} + + +#la-fp-d.txt fabs.d mask=0x01140800 +#0x01140800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fabs.d drD, drJ is op10_31=0x4502 & drD & drJ { + drD = abs(drJ); +} + + +#la-fp-d.txt fneg.d mask=0x01141800 +#0x01141800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fneg.d drD, drJ is op10_31=0x4506 & drD & drJ { + drD = f- drJ; +} + + +#la-fp-d.txt flogb.d mask=0x01142800 +#0x01142800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:flogb.d drD, drJ is op10_31=0x450a & drD & drJ { + drD = f_logb(drJ); +} + + +#la-fp-d.txt fclass.d mask=0x01143800 +#0x01143800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fclass.d drD, drJ is op10_31=0x450e & drD & drJ { + drD = f_class(drD, drJ); +} + + +#la-fp-d.txt fsqrt.d mask=0x01144800 +#0x01144800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fsqrt.d drD, drJ is op10_31=0x4512 & drD & drJ { + drD = sqrt(drJ); +} + + +#la-fp-d.txt frecip.d mask=0x01145800 +#0x01145800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:frecip.d drD, drJ is op10_31=0x4516 & drD & drJ { + local one:4 = 1; + drD = int2float(one) f/ drJ; +} + +#la-fp-d.txt frsqrt.d mask=0x01146800 +#0x01146800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:frsqrt.d drD, drJ is op10_31=0x451a & drD & drJ { + local one:4 = 1; + drD = int2float(one) f/ sqrt(drJ); +} + +#la-fp-d.txt fmov.d mask=0x01149800 +#0x01149800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fmov.d drD, drJ is op10_31=0x4526 & drD & drJ { + drD = drJ; +} + +@ifdef LA64 +#la-fp-d.txt movgr2fr.d mask=0x0114a800 +#0x0114a800 0xfffffc00 f0:5, r5:5 ['freg0_5_s0', 'reg5_5_s0'] +:movgr2fr.d drD, RJsrc is op10_31=0x452a & drD & RJsrc { + drD = RJsrc; +} + + +#la-fp-d.txt movfr2gr.d mask=0x0114b800 +#0x0114b800 0xfffffc00 r0:5, f5:5 ['reg0_5_s0', 'freg5_5_s0'] +:movfr2gr.d RD, drJ is op10_31=0x452e & RD & drJ { + RD = drJ; +} + +@endif + +#la-fp-d.txt fcvt.s.d mask=0x01191800 +#0x01191800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fcvt.s.d drD, drJ is op10_31=0x4646 & drD & drJ & frD { + frD = float2float(drJ); +} + +#la-fp-d.txt fcvt.d.s mask=0x01192400 +#0x01192400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fcvt.d.s drD, drJ is op10_31=0x4649 & drD & drJ & frJ { + drD = float2float(frJ); +} + + +#la-fp-d.txt ftintrm.w.d mask=0x011a0800 +#0x011a0800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrm.w.d drD, drJ is op10_31=0x4682 & drD & drJ { + local val:4 = trunc(drJ); + drD = zext(val); +} + +#la-fp-d.txt ftintrm.l.d mask=0x011a2800 +#0x011a2800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrm.l.d drD, drJ is op10_31=0x468a & drD & drJ { + drD = trunc(drJ); +} + + +#la-fp-d.txt ftintrp.w.d mask=0x011a4800 +#0x011a4800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrp.w.d drD, drJ is op10_31=0x4692 & drD & drJ { + local val:4 = trunc(drJ); + drD = zext(val); +} + +#la-fp-d.txt ftintrp.l.d mask=0x011a6800 +#0x011a6800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrp.l.d drD, drJ is op10_31=0x469a & drD & drJ { + drD = trunc(drJ); +} + + +#la-fp-d.txt ftintrz.w.d mask=0x011a8800 +#0x011a8800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrz.w.d drD, drJ is op10_31=0x46a2 & drD & drJ { + local val:4 = trunc(drJ); + drD = zext(val); +} + +#la-fp-d.txt ftintrz.l.d mask=0x011aa800 +#0x011aa800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrz.l.d drD, drJ is op10_31=0x46aa & drD & drJ { + drD = trunc(drJ); +} + + +#la-fp-d.txt ftintrne.w.d mask=0x011ac800 +#0x011ac800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrne.w.d drD, drJ is op10_31=0x46b2 & drD & drJ { + local val:4 = round_even(drJ); + drD = zext(val); +} + +#la-fp-d.txt ftintrne.l.d mask=0x011ae800 +#0x011ae800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrne.l.d drD, drJ is op10_31=0x46ba & drD & drJ { + drD = round_even(drJ); +} + + +#la-fp-d.txt ftint.w.d mask=0x011b0800 +#0x011b0800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftint.w.d drD, drJ is op10_31=0x46c2 & drD & drJ { + local val:4 = trunc(drJ); + drD = zext(val); +} + +#la-fp-d.txt ftint.l.d mask=0x011b2800 +#0x011b2800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftint.l.d drD, drJ is op10_31=0x46ca & drD & drJ { + drD = trunc(drJ); +} + + +#la-fp-d.txt ffint.d.w mask=0x011d2000 +#0x011d2000 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ffint.d.w drD, drJ is op10_31=0x4748 & drD & drJ & frJ { + drD = int2float(frJ); +} + +#la-fp-d.txt ffint.d.l mask=0x011d2800 +#0x011d2800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ffint.d.l drD, drJ is op10_31=0x474a & drD & drJ { + drD = int2float(drJ); +} + + +#la-fp-d.txt frint.d mask=0x011e4800 +#0x011e4800 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:frint.d drD, drJ is op10_31=0x4792 & drD & drJ { + local val:8 = trunc(drJ); + drD = int2float(val); +} + + +#la-fp-d.txt fmadd.d mask=0x08200000 +#0x08200000 0xfff00000 f0:5, f5:5, f10:5, f15:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0'] +:fmadd.d drD, drJ, drK, drA is op20_31=0x82 & drD & drJ & drK & drA { + drD = (drJ f* drK) f+ drA; +} + +#la-fp-d.txt fmsub.d mask=0x08600000 +#0x08600000 0xfff00000 f0:5, f5:5, f10:5, f15:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0'] +:fmsub.d drD, drJ, drK, drA is op20_31=0x86 & drD & drJ & drK & drA { + drD = (drJ f* drK) f- drA; +} + +#la-fp-d.txt fnmadd.d mask=0x08a00000 +#0x08a00000 0xfff00000 f0:5, f5:5, f10:5, f15:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0'] +:fnmadd.d drD, drJ, drK, drA is op20_31=0x8a & drD & drJ & drK & drA { + drD = f- ((drJ f* drK) f+ drA); +} + +#la-fp-d.txt fnmsub.d mask=0x08e00000 +#0x08e00000 0xfff00000 f0:5, f5:5, f10:5, f15:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0'] +:fnmsub.d drD, drJ, drK, drA is op20_31=0x8e & drD & drJ & drK & drA { + drD = f- ((drJ f* drK) f- drA); +} + +dSNaN: "c" is cond_s = 0 { } +dSNaN: "s" is cond_s = 1 { } + +dcond: dSNaN^"af" is cond=0x0 & dSNaN { DCMPR = 0; } +dcond: dSNaN^"lt" is cond=0x1 & dSNaN { DCMPR = DCMP1 f< DCMP2; } +dcond: dSNaN^"eq" is cond=0x2 & dSNaN { DCMPR = DCMP1 f== DCMP2; } +dcond: dSNaN^"le" is cond=0x3 & dSNaN { DCMPR = DCMP1 f<= DCMP2; } +dcond: dSNaN^"un" is cond=0x4 & dSNaN { DCMPR = nan(DCMP1) || nan(DCMP2); } +dcond: dSNaN^"ult" is cond=0x5 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f< DCMP2); } +dcond: dSNaN^"ueq" is cond=0x6 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f== DCMP2); } +dcond: dSNaN^"ule" is cond=0x7 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f<= DCMP2); } +dcond: dSNaN^"ne" is cond=0x8 & dSNaN { DCMPR = DCMP1 f!= DCMP2; } +dcond: dSNaN^"or" is cond=0xa & dSNaN { DCMPR = !(nan(DCMP1) || nan(DCMP2)); } +dcond: dSNaN^"une" is cond=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f!= DCMP2); } + +#la-fp-d.txt fcmp.caf.d mask=0x0c200000 +#0x0c200000 0xffff8018 c0:3, f5:5, f10:5 ['fcc0_3_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fcmp.^dcond^".d" fccD, drJ, drK is op20_31=0xc2 & dcond & op3_4 = 0 & fccD & drJ & drK { + DCMP1 = drJ; + DCMP2 = drK; + build dcond; + fccD = DCMPR; +} + + +#la-fp-d.txt fld.d mask=0x2b800000 +#0x2b800000 0xffc00000 f0:5, r5:5, so10:12 ['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:fld.d drD, ldst_addr is op22_31=0xae & drD & ldst_addr { + drD = sext(*[ram]:8 ldst_addr); +} + + +#la-fp-d.txt fst.d mask=0x2bc00000 +#0x2bc00000 0xffc00000 f0:5, r5:5, so10:12 ['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:fst.d drD, ldst_addr is op22_31=0xaf & drD & ldst_addr { + *[ram]:8 ldst_addr = drD; +} + + +#la-fp-d.txt fldx.d mask=0x38340000 +#0x38340000 0xffff8000 f0:5, r5:5, r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fldx.d drD, ldstx_addr is op15_31=0x7068 & drD & ldstx_addr { + drD = *[ram]:8 ldstx_addr; +} + + +#la-fp-d.txt fstx.d mask=0x383c0000 +#0x383c0000 0xffff8000 f0:5, r5:5, r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fstx.d drD, ldstx_addr is op15_31=0x7078 & drD & ldstx_addr { + *[ram]:8 ldstx_addr = drD; +} + +#la-bound-fp-d.txt fldgt.d mask=0x38748000 +#0x38748000 0xffff8000 f0:5,r5:5,r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fldgt.d drD, RJsrc, RKsrc is op15_31=0x70e9 & drD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + drD = sext(*[ram]:8 vaddr); + +} + + +#la-bound-fp-d.txt fldle.d mask=0x38758000 +#0x38758000 0xffff8000 f0:5,r5:5,r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fldle.d drD, RJsrc, RKsrc is op15_31=0x70eb & drD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + drD = sext(*[ram]:8 vaddr); + +} + +define pcodeop fstgt.d; + +#la-bound-fp-d.txt fstgt.d mask=0x38768000 +#0x38768000 0xffff8000 f0:5,r5:5,r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fstgt.d drD, RJsrc, RKsrc is op15_31=0x70ed & drD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:8 vaddr = drD; + +} + +define pcodeop fstle.d; + +#la-bound-fp-d.txt fstle.d mask=0x38778000 +#0x38778000 0xffff8000 f0:5,r5:5,r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fstle.d drD, RJsrc, RKsrc is op15_31=0x70ef & drD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:8 vaddr = drD; + +} + + diff --git a/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc new file mode 100644 index 0000000000..72662a462a --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc @@ -0,0 +1,489 @@ +#### +# General Floating-Point Instructions +#### + + +#la-fp.txt fcsrwr mask=0x0114c000 [@orig_name=movgr2fcsr, @orig_fmt=DJ] +#0x0114c000 0xfffffc1c fc0:2,r5:5 ['fcreg0_2_s0', 'reg5_5_s0'] +:movgr2fcsr fcsr, RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5=0 { + fcsr = RJ32src; +} + +:movgr2fcsr fcsr^".enables", RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5=1 { + local mask:4 = 0x1f; + fcsr = (fcsr & ~mask) + (RJ32src & mask); +} + +:movgr2fcsr fcsr^".flags_cause", RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5=2 { + local mask:4 = 0x1f1f0000; + fcsr = (fcsr & ~mask) + (RJ32src & mask); +} + +:movgr2fcsr fcsr^".rm", RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5=3 { + local mask:4 = 0x300; + fcsr = (fcsr & ~mask) + (RJ32src & mask); +} + +define pcodeop uncertain_fcsr; + +# per the manual: if the fcsr does not exist, the result is uncertain +:movgr2fcsr fcsr, RJ32 is op10_31=0x4530 & RJ32 & RJ32src & fcsr & imm0_5 { + uncertain_fcsr(imm0_5:1); + fcsr = RJ32src; +} + +#la-fp.txt fcsrrd mask=0x0114c800 [@orig_name=movfcsr2gr, @orig_fmt=DJ] +#0x0114c800 0xffffff80 r0:5,fc5:2 ['reg0_5_s0', 'fcreg5_2_s0'] +:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5=0 { + RD = sext(fcsr); +} + +:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5=1 { + local mask:4 = 0x1f; + RD = sext(fcsr & mask); +} + +:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5=2 { + local mask:4 = 0x1f1f0000; + RD = sext(fcsr & mask); +} + +:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5=3 { + local mask:4 = 0x300; + RD = sext(fcsr & mask); +} + +# per the manual: if the fcsr does not exist, the result is uncertain +:movfcsr2gr RD, fcsr is op10_31=0x4532 & RD & fcsr & imm5_5 { + uncertain_fcsr(imm5_5:1); + RD = sext(fcsr); +} + + +#la-fp.txt movfr2fcc mask=0x0114d000 [@orig_name=movfr2cf] +#0x0114d000 0xfffffc18 c0:3,f5:5 ['fcc0_3_s0', 'freg5_5_s0'] +:movfr2cf fccD, FRJ is op11_31=0x229a & fccD & FRJ { + fccD = FRJ[0,1]; +} + +#la-fp.txt movfcc2fr mask=0x0114d400 [@orig_name=movcf2fr] +#0x0114d400 0xffffff00 f0:5,c5:3 ['freg0_5_s0', 'fcc5_3_s0'] +:movcf2fr FRD, fccJ is op10_31=0x4535 & FRD & fccJ { + FRD[0,1] = fccJ[0,1]; +} + +#la-fp.txt movgr2fcc mask=0x0114d800 [@orig_name=movgr2cf] +#0x0114d800 0xfffffc18 c0:3,r5:5 ['fcc0_3_s0', 'reg5_5_s0'] +:movgr2cf fccD, RJsrc is op10_31=0x4536 & fccD & RJsrc { + fccD = RJsrc[0,1]; +} + +#la-fp.txt movfcc2gr mask=0x0114dc00 [@orig_name=movcf2gr] +#0x0114dc00 0xffffff00 r0:5,c5:3 ['reg0_5_s0', 'fcc5_3_s0'] +:movcf2gr RD, fccJ is op10_31=0x4537 & RD & fccJ { + RD[0,1] = fccJ[0,1]; +} + + +#la-fp.txt fsel mask=0x0d000000 +#0x0d000000 0xfffc0000 f0:5,f5:5,f10:5,c15:3 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'fcc15_3_s0'] +:fsel FRD, FRJ, FRK, fccA is op20_31=0xd0 & FRD & FRJ & FRK & fccA { + local test:1 = (fccA == 0); + FRD = (zext(!test) * FRK) + (zext(test) * FRJ); +} + + +#la-fp.txt bceqz mask=0x48000000 [@orig_fmt=CjSd5k16ps2] +#0x48000000 0xfc000300 c5:3,sb0:5|10:16<<2 ['fcc5_3_s0', 'sbranch0_0_s2'] +:bceqz fccJ, Rel21 is op26_31=0x12 & fccJ & op8_9=0 & Rel21 { + if(fccJ == 0) goto Rel21; +} + + +#la-fp.txt bcnez mask=0x48000100 [@orig_fmt=CjSd5k16ps2] +#0x48000100 0xfc000300 c5:3,sb0:5|10:16<<2 ['fcc5_3_s0', 'sbranch0_0_s2'] +#TODO: FIX RELATIVE OFFSET +:bcnez fccJ, Rel21 is op26_31=0x12 & fccJ & op8_9=1 & Rel21 { + if(fccJ != 0) goto Rel21; +} + + +##################################### +# Floating-Point Single Instructions +##################################### + + +#la-fp-s.txt fadd.s mask=0x01008000 +#0x01008000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fadd.s frD, frJ, frK is op15_31=0x201 & frD & frJ & frK { + frD = frJ f+ frK; +} + +#la-fp-s.txt fsub.s mask=0x01028000 +#0x01028000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fsub.s frD, frJ, frK is op15_31=0x205 & frD & frJ & frK { + frD = frJ f- frK; +} + +#la-fp-s.txt fmul.s mask=0x01048000 +#0x01048000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmul.s frD, frJ, frK is op15_31=0x209 & frD & frJ & frK { + frD = frJ f* frK; +} + +#la-fp-s.txt fdiv.s mask=0x01068000 +#0x01068000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fdiv.s frD, frJ, frK is op15_31=0x20d & frD & frJ & frK { + frD = frJ f/ frK; +} + + +#la-fp-s.txt fmadd.s mask=0x08100000 +#0x08100000 0xfff00000 f0:5, f5:5, f10:5, f15:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0'] +:fmadd.s frD, frJ, frK, frA is op20_31=0x81 & frD & frJ & frK & frA { + frD = (frJ f* frK) f+ frA; +} + +#la-fp-s.txt fmsub.s mask=0x08500000 +#0x08500000 0xfff00000 f0:5, f5:5, f10:5, f15:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0'] +:fmsub.s frD, frJ, frK, frA is op20_31=0x85 & frD & frJ & frK & frA { + frD = (frJ f* frK) f- frA; +} + +#la-fp-s.txt fnmadd.s mask=0x08900000 +#0x08900000 0xfff00000 f0:5, f5:5, f10:5, f15:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0'] +:fnmadd.s frD, frJ, frK, frA is op20_31=0x89 & frD & frJ & frK & frA { + frD = f- ((frJ f* frK) f+ frA); +} + +#la-fp-s.txt fnmsub.s mask=0x08d00000 +#0x08d00000 0xfff00000 f0:5, f5:5, f10:5, f15:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0', 'freg15_5_s0'] +:fnmsub.s frD, frJ, frK, frA is op20_31=0x8d & frD & frJ & frK & frA { + frD = f- ((frJ f* frK) f- frA); +} + + +#la-fp-s.txt fmax.s mask=0x01088000 +#0x01088000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmax.s frD, frJ, frK is op15_31=0x211 & frD & frJ & frK { + local jval = frJ; + local kval = frK; + frD = (zext(jval f>= kval) * jval) + (zext(jval f< kval) * jval); +} + +#la-fp-s.txt fmin.s mask=0x010a8000 +#0x010a8000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmin.s frD, frJ, frK is op15_31=0x215 & frD & frJ & frK { + local jval = frJ; + local kval = frK; + frD = (zext(jval f<= kval) * jval) + (zext(jval f> kval) * jval); +} + + +#la-fp-s.txt fmaxa.s mask=0x010c8000 +#0x010c8000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmaxa.s frD, frJ, frK is op15_31=0x219 & frD & frJ & frK { + local jval = frJ; + local kval = frK; + frD = (zext(abs(jval) f>= abs(kval)) * jval) + (zext(abs(jval) f< abs(kval)) * jval); +} + +#la-fp-s.txt fmina.s mask=0x010e8000 +#0x010e8000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fmina.s frD, frJ, frK is op15_31=0x21d & frD & frJ & frK { + local jval = frJ; + local kval = frK; + frD = (zext(abs(jval) f<= abs(kval)) * jval) + (zext(abs(jval) f> abs(kval)) * jval); +} + + +#la-fp-s.txt fabs.s mask=0x01140400 +#0x01140400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fabs.s frD, frJ is op10_31=0x4501 & frD & frJ { + frD = abs(frJ); +} + +#la-fp-s.txt fneg.s mask=0x01141400 +#0x01141400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fneg.s frD, frJ is op10_31=0x4505 & frD & frJ { + frD = f- frJ; +} + + +#la-fp-s.txt fsqrt.s mask=0x01144400 +#0x01144400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fsqrt.s frD, frJ is op10_31=0x4511 & frD & frJ { + frD = sqrt(frJ); +} + +#la-fp-s.txt frecip.s mask=0x01145400 +#0x01145400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:frecip.s frD, frJ is op10_31=0x4515 & frD & frJ { + local one:4 = 1; + frD = int2float(one) f/ frJ; +} + +#la-fp-s.txt frsqrt.s mask=0x01146400 +#0x01146400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:frsqrt.s frD, frJ is op10_31=0x4519 & frD & frJ { + local one:4 = 1; + frD = int2float(one) f/ sqrt(frJ); +} + + +#la-fp-s.txt fscaleb.s mask=0x01108000 +#0x01108000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fscaleb.s frD, frJ, frK is op15_31=0x221 & frD & frJ & frK { + frD = f_scaleb(frJ, frK); +} + + +#la-fp-s.txt flogb.s mask=0x01142400 +#0x01142400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:flogb.s frD, frJ is op10_31=0x4509 & frD & frJ { + frD = f_logb(frJ); +} + +#la-fp-s.txt fcopysign.s mask=0x01128000 +#0x01128000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fcopysign.s frD, frJ, frK is op15_31=0x225 & frD & frJ & frK { + local kval = frK; + frD = frJ f* (kval/abs(kval)); +} + + +#la-fp-s.txt fclass.s mask=0x01143400 +#0x01143400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fclass.s frD, frJ is op10_31=0x450d & frD & frJ { + frD = f_class(frJ); +} + + +#la-fp-s.txt fmov.s mask=0x01149400 +#0x01149400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fmov.s frD, frJ is op10_31=0x4525 & frD & frJ { + frD = frJ; +} + + +#la-fp-s.txt movgr2fr.w mask=0x0114a400 +#0x0114a400 0xfffffc00 f0:5,r5:5 ['freg0_5_s0', 'reg5_5_s0'] +:movgr2fr.w frD, RJ32src is op10_31=0x4529 & frD & RJ32src { + frD = RJ32src; +} + +#la-fp-s.txt movgr2frh.w mask=0x0114ac00 +#0x0114ac00 0xfffffc00 f0:5,r5:5 ['freg0_5_s0', 'reg5_5_s0'] +:movgr2frh.w drD, RJ32src is op10_31=0x452b & drD & RJ32src { + drD = (zext(RJ32src) << 32) | (drD & 0xffffffff); +} + + +#la-fp-s.txt movfr2gr.s mask=0x0114b400 +#0x0114b400 0xfffffc00 r0:5, f5:5 ['reg0_5_s0', 'freg5_5_s0'] +:movfr2gr.s RD, frJ is op10_31=0x452d & RD & frJ { + RD = sext(frJ); +} + +#la-fp-s.txt movfrh2gr.s mask=0x0114bc00 +#0x0114bc00 0xfffffc00 r0:5, f5:5 ['reg0_5_s0', 'freg5_5_s0'] +:movfrh2gr.s RD, drJ is op10_31=0x452f & RD & drJ { + RD = sext(drJ[32,32]); +} + + +#la-fp-s.txt ftintrm.w.s mask=0x011a0400 +#0x011a0400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrm.w.s frD, frJ is op10_31=0x4681 & frD & frJ { + frD = trunc(frJ); +} + +#la-fp-s.txt ftintrm.l.s mask=0x011a2400 +#0x011a2400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrm.l.s frD, frJ is op10_31=0x4689 & frD & frJ { + local val:8 = trunc(frJ); + frD = val(0); +} + + +#la-fp-s.txt ftintrp.w.s mask=0x011a4400 +#0x011a4400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrp.w.s frD, frJ is op10_31=0x4691 & frD & frJ { + frD = trunc(frJ); +} + +#la-fp-s.txt ftintrp.l.s mask=0x011a6400 +#0x011a6400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrp.l.s frD, frJ is op10_31=0x4699 & frD & frJ { + local val:8 = trunc(frJ); + frD = val(0); +} + + +#la-fp-s.txt ftintrz.w.s mask=0x011a8400 +#0x011a8400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrz.w.s frD, frJ is op10_31=0x46a1 & frD & frJ { + frD = trunc(frJ); +} + +#la-fp-s.txt ftintrz.l.s mask=0x011aa400 +#0x011aa400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrz.l.s frD, frJ is op10_31=0x46a9 & frD & frJ { + local val:8 = trunc(frJ); + frD = val(0); +} + + +#la-fp-s.txt ftintrne.w.s mask=0x011ac400 +#0x011ac400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrne.w.s frD, frJ is op10_31=0x46b1 & frD & frJ { + frD = round_even(frJ); +} + +#la-fp-s.txt ftintrne.l.s mask=0x011ae400 +#0x011ae400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftintrne.l.s frD, frJ is op10_31=0x46b9 & frD & frJ { + local val:8 = round_even(frJ); + frD = val(0); +} + + +#la-fp-s.txt ftint.w.s mask=0x011b0400 +#0x011b0400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftint.w.s frD, frJ is op10_31=0x46c1 & frD & frJ { + frD = trunc(frJ); +} + +#la-fp-s.txt ftint.l.s mask=0x011b2400 +#0x011b2400 0xfffffc00 f0:5, f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ftint.l.s frD, frJ is op10_31=0x46c9 & frD & frJ { + local val:8 = trunc(frJ); + frD = val(0); +} + + +#la-fp-s.txt ffint.s.w mask=0x011d1000 +#0x011d1000 0xfffffc00 f0:5,f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ffint.s.w frD,frJ is op10_31=0x4744 & frD & frJ { + frD =int2float(frJ); +} + + +#la-fp-s.txt ffint.s.l mask=0x011d1800 +#0x011d1800 0xfffffc00 f0:5,f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:ffint.s.l frD,frJ is op10_31=0x4746 & frD & frJ { + local val:8 = int2float(frJ); + frD = frJ(0); +} + + +#la-fp-s.txt frint.s mask=0x011e4400 +#0x011e4400 0xfffffc00 f0:5,f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:frint.s frD,frJ is op10_31=0x4791 & frD & frJ { + local val:4 = trunc(frJ); + frD = int2float(val); +} + + +#la-fp-s.txt fld.s mask=0x2b000000 +#0x2b000000 0xffc00000 f0:5,r5:5,so10:12 ['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:fld.s frD, ldst_addr is op22_31=0xac & frD & ldst_addr { + frD = sext(*[ram]:4 ldst_addr); +} + + +#la-fp-s.txt fst.s mask=0x2b400000 +#0x2b400000 0xffc00000 f0:5,r5:5,so10:12 ['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +:fst.s frD, ldst_addr is op22_31=0xad & frD & ldst_addr { + *[ram]:4 ldst_addr = frD:4; +} + + +#la-fp-s.txt fldx.s mask=0x38300000 +#0x38300000 0xffff8000 f0:5,r5:5,r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fldx.s frD, ldstx_addr is op15_31=0x7060 & frD & ldstx_addr { + frD = *[ram]:4 ldstx_addr; +} + +#la-fp-s.txt fstx.s mask=0x38380000 +#0x38380000 0xffff8000 f0:5,r5:5,r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fstx.s frD, ldstx_addr is op15_31=0x7070 & frD & ldstx_addr { + *[ram]:4 ldstx_addr = frD; +} + +SNaN: "c" is cond_s = 0 { } +SNaN: "s" is cond_s = 1 { } + +fcond: SNaN^"af" is cond=0x0 & SNaN { FCMPR = 0; } +fcond: SNaN^"lt" is cond=0x1 & SNaN { FCMPR = FCMP1 f< FCMP2; } +fcond: SNaN^"eq" is cond=0x2 & SNaN { FCMPR = FCMP1 f== FCMP2; } +fcond: SNaN^"le" is cond=0x3 & SNaN { FCMPR = FCMP1 f<= FCMP2; } +fcond: SNaN^"un" is cond=0x4 & SNaN { FCMPR = nan(FCMP1) || nan(FCMP2); } +fcond: SNaN^"ult" is cond=0x5 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f< FCMP2); } +fcond: SNaN^"ueq" is cond=0x6 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f== FCMP2); } +fcond: SNaN^"ule" is cond=0x7 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f<= FCMP2); } +fcond: SNaN^"ne" is cond=0x8 & SNaN { FCMPR = FCMP1 f!= FCMP2; } +fcond: SNaN^"or" is cond=0xa & SNaN { FCMPR = !(nan(FCMP1) || nan(FCMP2)); } +fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f!= FCMP2); } + +#la-fp-s.txt fcmp.caf.s mask=0x0c100000 +#0x0c100000 0xffff8018 c0:3, f5:5, f10:5 ['fcc0_3_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fcmp.^fcond^".s" fccD, frJ, frK is op20_31=0xc1 & fcond & op3_4 = 0 & fccD & frJ & frK { + FCMP1 = frJ; + FCMP2 = frK; + build fcond; + fccD = FCMPR; +} + + +#la-bound-fp-s.txt fldgt.s mask=0x38740000 +#0x38740000 0xffff8000 f0:5, r5:5, r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fldgt.s frD, RJsrc, RKsrc is op15_31=0x70e8 & frD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + frD = sext(*[ram]:4 vaddr); + +} + + +#la-bound-fp-s.txt fldle.s mask=0x38750000 +#0x38750000 0xffff8000 f0:5, r5:5, r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fldle.s frD, RJsrc, RKsrc is op15_31=0x70ea & frD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + frD = sext(*[ram]:4 vaddr); + +} + + +#la-bound-fp-s.txt fstgt.s mask=0x38760000 +#0x38760000 0xffff8000 f0:5, r5:5, r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fstgt.s frD, RJsrc, RKsrc is op15_31=0x70ec & frD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr > RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:4 vaddr = frD; + +} + + +#la-bound-fp-s.txt fstle.s mask=0x38770000 +#0x38770000 0xffff8000 f0:5, r5:5, r10:5 ['freg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:fstle.s frD, RJsrc, RKsrc is op15_31=0x70ee & frD & RJsrc & RKsrc { + local vaddr = RJsrc; + if (vaddr <= RKsrc) goto ; + bound_check_exception(RJsrc, RKsrc); + goto ; + + *[ram]:4 vaddr = frD; + +} + diff --git a/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec b/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec new file mode 100644 index 0000000000..1689513d1d --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec new file mode 100644 index 0000000000..fba9d74aba --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec @@ -0,0 +1,145 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lasx.sinc b/Ghidra/Processors/Loongarch/data/languages/lasx.sinc new file mode 100644 index 0000000000..0ae4624457 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/lasx.sinc @@ -0,0 +1,5851 @@ +define pcodeop xvfmadd.s; + +#lasx.txt xvfmadd.s mask=0x0a100000 +#0x0a100000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvfmadd.s xrD, xrJ, xrK, xrA is op20_31=0xa1 & xrD & xrJ & xrK & xrA { + xrD = xvfmadd.s(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvfmadd.d; + +#lasx.txt xvfmadd.d mask=0x0a200000 +#0x0a200000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvfmadd.d xrD, xrJ, xrK, xrA is op20_31=0xa2 & xrD & xrJ & xrK & xrA { + xrD = xvfmadd.d(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvfmsub.s; + +#lasx.txt xvfmsub.s mask=0x0a500000 +#0x0a500000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvfmsub.s xrD, xrJ, xrK, xrA is op20_31=0xa5 & xrD & xrJ & xrK & xrA { + xrD = xvfmsub.s(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvfmsub.d; + +#lasx.txt xvfmsub.d mask=0x0a600000 +#0x0a600000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvfmsub.d xrD, xrJ, xrK, xrA is op20_31=0xa6 & xrD & xrJ & xrK & xrA { + xrD = xvfmsub.d(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvfnmadd.s; + +#lasx.txt xvfnmadd.s mask=0x0a900000 +#0x0a900000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvfnmadd.s xrD, xrJ, xrK, xrA is op20_31=0xa9 & xrD & xrJ & xrK & xrA { + xrD = xvfnmadd.s(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvfnmadd.d; + +#lasx.txt xvfnmadd.d mask=0x0aa00000 +#0x0aa00000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvfnmadd.d xrD, xrJ, xrK, xrA is op20_31=0xaa & xrD & xrJ & xrK & xrA { + xrD = xvfnmadd.d(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvfnmsub.s; + +#lasx.txt xvfnmsub.s mask=0x0ad00000 +#0x0ad00000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvfnmsub.s xrD, xrJ, xrK, xrA is op20_31=0xad & xrD & xrJ & xrK & xrA { + xrD = xvfnmsub.s(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvfnmsub.d; + +#lasx.txt xvfnmsub.d mask=0x0ae00000 +#0x0ae00000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvfnmsub.d xrD, xrJ, xrK, xrA is op20_31=0xae & xrD & xrJ & xrK & xrA { + xrD = xvfnmsub.d(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvfcmp.caf.s; + +#lasx.txt xvfcmp.caf.s mask=0x0c900000 +#0x0c900000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.caf.s xrD, xrJ, xrK is op15_31=0x1920 & xrD & xrJ & xrK { + xrD = xvfcmp.caf.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.saf.s; + +#lasx.txt xvfcmp.saf.s mask=0x0c908000 +#0x0c908000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.saf.s xrD, xrJ, xrK is op15_31=0x1921 & xrD & xrJ & xrK { + xrD = xvfcmp.saf.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.clt.s; + +#lasx.txt xvfcmp.clt.s mask=0x0c910000 +#0x0c910000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.clt.s xrD, xrJ, xrK is op15_31=0x1922 & xrD & xrJ & xrK { + xrD = xvfcmp.clt.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.slt.s; + +#lasx.txt xvfcmp.slt.s mask=0x0c918000 +#0x0c918000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.slt.s xrD, xrJ, xrK is op15_31=0x1923 & xrD & xrJ & xrK { + xrD = xvfcmp.slt.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.ceq.s; + +#lasx.txt xvfcmp.ceq.s mask=0x0c920000 +#0x0c920000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.ceq.s xrD, xrJ, xrK is op15_31=0x1924 & xrD & xrJ & xrK { + xrD = xvfcmp.ceq.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.seq.s; + +#lasx.txt xvfcmp.seq.s mask=0x0c928000 +#0x0c928000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.seq.s xrD, xrJ, xrK is op15_31=0x1925 & xrD & xrJ & xrK { + xrD = xvfcmp.seq.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cle.s; + +#lasx.txt xvfcmp.cle.s mask=0x0c930000 +#0x0c930000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cle.s xrD, xrJ, xrK is op15_31=0x1926 & xrD & xrJ & xrK { + xrD = xvfcmp.cle.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sle.s; + +#lasx.txt xvfcmp.sle.s mask=0x0c938000 +#0x0c938000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sle.s xrD, xrJ, xrK is op15_31=0x1927 & xrD & xrJ & xrK { + xrD = xvfcmp.sle.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cun.s; + +#lasx.txt xvfcmp.cun.s mask=0x0c940000 +#0x0c940000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cun.s xrD, xrJ, xrK is op15_31=0x1928 & xrD & xrJ & xrK { + xrD = xvfcmp.cun.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sun.s; + +#lasx.txt xvfcmp.sun.s mask=0x0c948000 +#0x0c948000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sun.s xrD, xrJ, xrK is op15_31=0x1929 & xrD & xrJ & xrK { + xrD = xvfcmp.sun.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cult.s; + +#lasx.txt xvfcmp.cult.s mask=0x0c950000 +#0x0c950000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cult.s xrD, xrJ, xrK is op15_31=0x192a & xrD & xrJ & xrK { + xrD = xvfcmp.cult.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sult.s; + +#lasx.txt xvfcmp.sult.s mask=0x0c958000 +#0x0c958000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sult.s xrD, xrJ, xrK is op15_31=0x192b & xrD & xrJ & xrK { + xrD = xvfcmp.sult.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cueq.s; + +#lasx.txt xvfcmp.cueq.s mask=0x0c960000 +#0x0c960000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cueq.s xrD, xrJ, xrK is op15_31=0x192c & xrD & xrJ & xrK { + xrD = xvfcmp.cueq.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sueq.s; + +#lasx.txt xvfcmp.sueq.s mask=0x0c968000 +#0x0c968000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sueq.s xrD, xrJ, xrK is op15_31=0x192d & xrD & xrJ & xrK { + xrD = xvfcmp.sueq.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cule.s; + +#lasx.txt xvfcmp.cule.s mask=0x0c970000 +#0x0c970000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cule.s xrD, xrJ, xrK is op15_31=0x192e & xrD & xrJ & xrK { + xrD = xvfcmp.cule.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sule.s; + +#lasx.txt xvfcmp.sule.s mask=0x0c978000 +#0x0c978000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sule.s xrD, xrJ, xrK is op15_31=0x192f & xrD & xrJ & xrK { + xrD = xvfcmp.sule.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cne.s; + +#lasx.txt xvfcmp.cne.s mask=0x0c980000 +#0x0c980000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cne.s xrD, xrJ, xrK is op15_31=0x1930 & xrD & xrJ & xrK { + xrD = xvfcmp.cne.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sne.s; + +#lasx.txt xvfcmp.sne.s mask=0x0c988000 +#0x0c988000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sne.s xrD, xrJ, xrK is op15_31=0x1931 & xrD & xrJ & xrK { + xrD = xvfcmp.sne.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cor.s; + +#lasx.txt xvfcmp.cor.s mask=0x0c9a0000 +#0x0c9a0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cor.s xrD, xrJ, xrK is op15_31=0x1934 & xrD & xrJ & xrK { + xrD = xvfcmp.cor.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sor.s; + +#lasx.txt xvfcmp.sor.s mask=0x0c9a8000 +#0x0c9a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sor.s xrD, xrJ, xrK is op15_31=0x1935 & xrD & xrJ & xrK { + xrD = xvfcmp.sor.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cune.s; + +#lasx.txt xvfcmp.cune.s mask=0x0c9c0000 +#0x0c9c0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cune.s xrD, xrJ, xrK is op15_31=0x1938 & xrD & xrJ & xrK { + xrD = xvfcmp.cune.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sune.s; + +#lasx.txt xvfcmp.sune.s mask=0x0c9c8000 +#0x0c9c8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sune.s xrD, xrJ, xrK is op15_31=0x1939 & xrD & xrJ & xrK { + xrD = xvfcmp.sune.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.caf.d; + +#lasx.txt xvfcmp.caf.d mask=0x0ca00000 +#0x0ca00000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.caf.d xrD, xrJ, xrK is op15_31=0x1940 & xrD & xrJ & xrK { + xrD = xvfcmp.caf.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.saf.d; + +#lasx.txt xvfcmp.saf.d mask=0x0ca08000 +#0x0ca08000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.saf.d xrD, xrJ, xrK is op15_31=0x1941 & xrD & xrJ & xrK { + xrD = xvfcmp.saf.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.clt.d; + +#lasx.txt xvfcmp.clt.d mask=0x0ca10000 +#0x0ca10000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.clt.d xrD, xrJ, xrK is op15_31=0x1942 & xrD & xrJ & xrK { + xrD = xvfcmp.clt.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.slt.d; + +#lasx.txt xvfcmp.slt.d mask=0x0ca18000 +#0x0ca18000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.slt.d xrD, xrJ, xrK is op15_31=0x1943 & xrD & xrJ & xrK { + xrD = xvfcmp.slt.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.ceq.d; + +#lasx.txt xvfcmp.ceq.d mask=0x0ca20000 +#0x0ca20000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.ceq.d xrD, xrJ, xrK is op15_31=0x1944 & xrD & xrJ & xrK { + xrD = xvfcmp.ceq.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.seq.d; + +#lasx.txt xvfcmp.seq.d mask=0x0ca28000 +#0x0ca28000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.seq.d xrD, xrJ, xrK is op15_31=0x1945 & xrD & xrJ & xrK { + xrD = xvfcmp.seq.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cle.d; + +#lasx.txt xvfcmp.cle.d mask=0x0ca30000 +#0x0ca30000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cle.d xrD, xrJ, xrK is op15_31=0x1946 & xrD & xrJ & xrK { + xrD = xvfcmp.cle.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sle.d; + +#lasx.txt xvfcmp.sle.d mask=0x0ca38000 +#0x0ca38000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sle.d xrD, xrJ, xrK is op15_31=0x1947 & xrD & xrJ & xrK { + xrD = xvfcmp.sle.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cun.d; + +#lasx.txt xvfcmp.cun.d mask=0x0ca40000 +#0x0ca40000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cun.d xrD, xrJ, xrK is op15_31=0x1948 & xrD & xrJ & xrK { + xrD = xvfcmp.cun.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sun.d; + +#lasx.txt xvfcmp.sun.d mask=0x0ca48000 +#0x0ca48000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sun.d xrD, xrJ, xrK is op15_31=0x1949 & xrD & xrJ & xrK { + xrD = xvfcmp.sun.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cult.d; + +#lasx.txt xvfcmp.cult.d mask=0x0ca50000 +#0x0ca50000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cult.d xrD, xrJ, xrK is op15_31=0x194a & xrD & xrJ & xrK { + xrD = xvfcmp.cult.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sult.d; + +#lasx.txt xvfcmp.sult.d mask=0x0ca58000 +#0x0ca58000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sult.d xrD, xrJ, xrK is op15_31=0x194b & xrD & xrJ & xrK { + xrD = xvfcmp.sult.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cueq.d; + +#lasx.txt xvfcmp.cueq.d mask=0x0ca60000 +#0x0ca60000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cueq.d xrD, xrJ, xrK is op15_31=0x194c & xrD & xrJ & xrK { + xrD = xvfcmp.cueq.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sueq.d; + +#lasx.txt xvfcmp.sueq.d mask=0x0ca68000 +#0x0ca68000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sueq.d xrD, xrJ, xrK is op15_31=0x194d & xrD & xrJ & xrK { + xrD = xvfcmp.sueq.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cule.d; + +#lasx.txt xvfcmp.cule.d mask=0x0ca70000 +#0x0ca70000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cule.d xrD, xrJ, xrK is op15_31=0x194e & xrD & xrJ & xrK { + xrD = xvfcmp.cule.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sule.d; + +#lasx.txt xvfcmp.sule.d mask=0x0ca78000 +#0x0ca78000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sule.d xrD, xrJ, xrK is op15_31=0x194f & xrD & xrJ & xrK { + xrD = xvfcmp.sule.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cne.d; + +#lasx.txt xvfcmp.cne.d mask=0x0ca80000 +#0x0ca80000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cne.d xrD, xrJ, xrK is op15_31=0x1950 & xrD & xrJ & xrK { + xrD = xvfcmp.cne.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sne.d; + +#lasx.txt xvfcmp.sne.d mask=0x0ca88000 +#0x0ca88000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sne.d xrD, xrJ, xrK is op15_31=0x1951 & xrD & xrJ & xrK { + xrD = xvfcmp.sne.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cor.d; + +#lasx.txt xvfcmp.cor.d mask=0x0caa0000 +#0x0caa0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cor.d xrD, xrJ, xrK is op15_31=0x1954 & xrD & xrJ & xrK { + xrD = xvfcmp.cor.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sor.d; + +#lasx.txt xvfcmp.sor.d mask=0x0caa8000 +#0x0caa8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sor.d xrD, xrJ, xrK is op15_31=0x1955 & xrD & xrJ & xrK { + xrD = xvfcmp.sor.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.cune.d; + +#lasx.txt xvfcmp.cune.d mask=0x0cac0000 +#0x0cac0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.cune.d xrD, xrJ, xrK is op15_31=0x1958 & xrD & xrJ & xrK { + xrD = xvfcmp.cune.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcmp.sune.d; + +#lasx.txt xvfcmp.sune.d mask=0x0cac8000 +#0x0cac8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcmp.sune.d xrD, xrJ, xrK is op15_31=0x1959 & xrD & xrJ & xrK { + xrD = xvfcmp.sune.d(xrD, xrJ, xrK); +} + +define pcodeop xvbitsel.v; + +#lasx.txt xvbitsel.v mask=0x0d200000 +#0x0d200000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvbitsel.v xrD, xrJ, xrK, xrA is op20_31=0xd2 & xrD & xrJ & xrK & xrA { + xrD = xvbitsel.v(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvshuf.b; + +#lasx.txt xvshuf.b mask=0x0d600000 +#0x0d600000 0xfff00000 x0:5,x5:5,x10:5,x15:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0', 'xreg15_5_s0'] +:xvshuf.b xrD, xrJ, xrK, xrA is op20_31=0xd6 & xrD & xrJ & xrK & xrA { + xrD = xvshuf.b(xrD, xrJ, xrK, xrA); +} + +define pcodeop xvld; + +#lasx.txt xvld mask=0x2c800000 +#0x2c800000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:xvld xrD, RJsrc,simm10_12 is op22_31=0xb2 & xrD & RJsrc & simm10_12 { + xrD = xvld(xrD, RJsrc, simm10_12:$(REGSIZE)); +} + +define pcodeop xvst; + +#lasx.txt xvst mask=0x2cc00000 +#0x2cc00000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:xvst xrD, RJsrc,simm10_12 is op22_31=0xb3 & xrD & RJsrc & simm10_12 { + xrD = xvst(xrD, RJsrc, simm10_12:$(REGSIZE)); +} + +define pcodeop xvldrepl.d; + +#lasx.txt xvldrepl.d mask=0x32100000 [@orig_fmt=XdJSk9ps3] +#0x32100000 0xfff80000 x0:5, r5:5,so10:9<<3 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_9_s0'] +#TODO: FIX RELATIVE OFFSET +:xvldrepl.d xrD, RJsrc,simm10_9 is op19_31=0x642 & xrD & RJsrc & simm10_9 { + xrD = xvldrepl.d(xrD, RJsrc, simm10_9:$(REGSIZE)); +} + +define pcodeop xvldrepl.w; + +#lasx.txt xvldrepl.w mask=0x32200000 [@orig_fmt=XdJSk10ps2] +#0x32200000 0xfff00000 x0:5, r5:5,so10:10<<2 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_10_s0'] +#TODO: FIX RELATIVE OFFSET +:xvldrepl.w xrD, RJsrc,simm10_10 is op20_31=0x322 & xrD & RJsrc & simm10_10 { + xrD = xvldrepl.w(xrD, RJsrc, simm10_10:$(REGSIZE)); +} + +define pcodeop xvldrepl.h; + +#lasx.txt xvldrepl.h mask=0x32400000 [@orig_fmt=XdJSk11ps1] +#0x32400000 0xffe00000 x0:5, r5:5,so10:11<<1 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_11_s0'] +#TODO: FIX RELATIVE OFFSET +:xvldrepl.h xrD, RJsrc,simm10_11 is op21_31=0x192 & xrD & RJsrc & simm10_11 { + xrD = xvldrepl.h(xrD, RJsrc, simm10_11:$(REGSIZE)); +} + +define pcodeop xvldrepl.b; + +#lasx.txt xvldrepl.b mask=0x32800000 +#0x32800000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:xvldrepl.b xrD, RJsrc,simm10_12 is op22_31=0xca & xrD & RJsrc & simm10_12 { + xrD = xvldrepl.b(xrD, RJsrc, simm10_12:$(REGSIZE)); +} + +define pcodeop xvstelm.d; + +#lasx.txt xvstelm.d mask=0x33100000 [@orig_fmt=XdJSk8ps3Un2] +#0x33100000 0xfff00000 x0:5, r5:5,so10:8<<3,u18:2 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_2_s0'] +#TODO: FIX RELATIVE OFFSET +:xvstelm.d xrD, RJsrc,simm10_8, imm18_2 is op20_31=0x331 & xrD & RJsrc & simm10_8 & imm18_2 { + xrD = xvstelm.d(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_2:$(REGSIZE)); +} + +define pcodeop xvstelm.w; + +#lasx.txt xvstelm.w mask=0x33200000 [@orig_fmt=XdJSk8ps2Un3] +#0x33200000 0xffe00000 x0:5, r5:5,so10:8<<2,u18:3 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_3_s0'] +#TODO: FIX RELATIVE OFFSET +:xvstelm.w xrD, RJsrc,simm10_8, imm18_3 is op21_31=0x199 & xrD & RJsrc & simm10_8 & imm18_3 { + xrD = xvstelm.w(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_3:$(REGSIZE)); +} + +define pcodeop xvstelm.h; + +#lasx.txt xvstelm.h mask=0x33400000 [@orig_fmt=XdJSk8ps1Un4] +#0x33400000 0xffc00000 x0:5, r5:5,so10:8<<1,u18:4 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_4_s0'] +#TODO: FIX RELATIVE OFFSET +:xvstelm.h xrD, RJsrc,simm10_8, imm18_4 is op22_31=0xcd & xrD & RJsrc & simm10_8 & imm18_4 { + xrD = xvstelm.h(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_4:$(REGSIZE)); +} + +define pcodeop xvstelm.b; + +#lasx.txt xvstelm.b mask=0x33800000 +#0x33800000 0xff800000 x0:5, r5:5,so10:8,u18:5 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_5_s0'] +#TODO: FIX RELATIVE OFFSET +:xvstelm.b xrD, RJsrc,simm10_8, imm18_5 is op23_31=0x67 & xrD & RJsrc & simm10_8 & imm18_5 { + xrD = xvstelm.b(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_5:$(REGSIZE)); +} + +define pcodeop xvldx; + +#lasx.txt xvldx mask=0x38480000 +#0x38480000 0xffff8000 x0:5, r5:5, r10:5 ['xreg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:xvldx xrD, RJsrc, RKsrc is op15_31=0x7090 & xrD & RJsrc & RKsrc { + xrD = xvldx(xrD, RJsrc, RKsrc); +} + +define pcodeop xvstx; + +#lasx.txt xvstx mask=0x384c0000 +#0x384c0000 0xffff8000 x0:5, r5:5, r10:5 ['xreg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:xvstx xrD, RJsrc, RKsrc is op15_31=0x7098 & xrD & RJsrc & RKsrc { + xrD = xvstx(xrD, RJsrc, RKsrc); +} + +define pcodeop xvseq.b; + +#lasx.txt xvseq.b mask=0x74000000 +#0x74000000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvseq.b xrD, xrJ, xrK is op15_31=0xe800 & xrD & xrJ & xrK { + xrD = xvseq.b(xrD, xrJ, xrK); +} + +define pcodeop xvseq.h; + +#lasx.txt xvseq.h mask=0x74008000 +#0x74008000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvseq.h xrD, xrJ, xrK is op15_31=0xe801 & xrD & xrJ & xrK { + xrD = xvseq.h(xrD, xrJ, xrK); +} + +define pcodeop xvseq.w; + +#lasx.txt xvseq.w mask=0x74010000 +#0x74010000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvseq.w xrD, xrJ, xrK is op15_31=0xe802 & xrD & xrJ & xrK { + xrD = xvseq.w(xrD, xrJ, xrK); +} + +define pcodeop xvseq.d; + +#lasx.txt xvseq.d mask=0x74018000 +#0x74018000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvseq.d xrD, xrJ, xrK is op15_31=0xe803 & xrD & xrJ & xrK { + xrD = xvseq.d(xrD, xrJ, xrK); +} + +define pcodeop xvsle.b; + +#lasx.txt xvsle.b mask=0x74020000 +#0x74020000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsle.b xrD, xrJ, xrK is op15_31=0xe804 & xrD & xrJ & xrK { + xrD = xvsle.b(xrD, xrJ, xrK); +} + +define pcodeop xvsle.h; + +#lasx.txt xvsle.h mask=0x74028000 +#0x74028000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsle.h xrD, xrJ, xrK is op15_31=0xe805 & xrD & xrJ & xrK { + xrD = xvsle.h(xrD, xrJ, xrK); +} + +define pcodeop xvsle.w; + +#lasx.txt xvsle.w mask=0x74030000 +#0x74030000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsle.w xrD, xrJ, xrK is op15_31=0xe806 & xrD & xrJ & xrK { + xrD = xvsle.w(xrD, xrJ, xrK); +} + +define pcodeop xvsle.d; + +#lasx.txt xvsle.d mask=0x74038000 +#0x74038000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsle.d xrD, xrJ, xrK is op15_31=0xe807 & xrD & xrJ & xrK { + xrD = xvsle.d(xrD, xrJ, xrK); +} + +define pcodeop xvsle.bu; + +#lasx.txt xvsle.bu mask=0x74040000 +#0x74040000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsle.bu xrD, xrJ, xrK is op15_31=0xe808 & xrD & xrJ & xrK { + xrD = xvsle.bu(xrD, xrJ, xrK); +} + +define pcodeop xvsle.hu; + +#lasx.txt xvsle.hu mask=0x74048000 +#0x74048000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsle.hu xrD, xrJ, xrK is op15_31=0xe809 & xrD & xrJ & xrK { + xrD = xvsle.hu(xrD, xrJ, xrK); +} + +define pcodeop xvsle.wu; + +#lasx.txt xvsle.wu mask=0x74050000 +#0x74050000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsle.wu xrD, xrJ, xrK is op15_31=0xe80a & xrD & xrJ & xrK { + xrD = xvsle.wu(xrD, xrJ, xrK); +} + +define pcodeop xvsle.du; + +#lasx.txt xvsle.du mask=0x74058000 +#0x74058000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsle.du xrD, xrJ, xrK is op15_31=0xe80b & xrD & xrJ & xrK { + xrD = xvsle.du(xrD, xrJ, xrK); +} + +define pcodeop xvslt.b; + +#lasx.txt xvslt.b mask=0x74060000 +#0x74060000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvslt.b xrD, xrJ, xrK is op15_31=0xe80c & xrD & xrJ & xrK { + xrD = xvslt.b(xrD, xrJ, xrK); +} + +define pcodeop xvslt.h; + +#lasx.txt xvslt.h mask=0x74068000 +#0x74068000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvslt.h xrD, xrJ, xrK is op15_31=0xe80d & xrD & xrJ & xrK { + xrD = xvslt.h(xrD, xrJ, xrK); +} + +define pcodeop xvslt.w; + +#lasx.txt xvslt.w mask=0x74070000 +#0x74070000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvslt.w xrD, xrJ, xrK is op15_31=0xe80e & xrD & xrJ & xrK { + xrD = xvslt.w(xrD, xrJ, xrK); +} + +define pcodeop xvslt.d; + +#lasx.txt xvslt.d mask=0x74078000 +#0x74078000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvslt.d xrD, xrJ, xrK is op15_31=0xe80f & xrD & xrJ & xrK { + xrD = xvslt.d(xrD, xrJ, xrK); +} + +define pcodeop xvslt.bu; + +#lasx.txt xvslt.bu mask=0x74080000 +#0x74080000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvslt.bu xrD, xrJ, xrK is op15_31=0xe810 & xrD & xrJ & xrK { + xrD = xvslt.bu(xrD, xrJ, xrK); +} + +define pcodeop xvslt.hu; + +#lasx.txt xvslt.hu mask=0x74088000 +#0x74088000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvslt.hu xrD, xrJ, xrK is op15_31=0xe811 & xrD & xrJ & xrK { + xrD = xvslt.hu(xrD, xrJ, xrK); +} + +define pcodeop xvslt.wu; + +#lasx.txt xvslt.wu mask=0x74090000 +#0x74090000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvslt.wu xrD, xrJ, xrK is op15_31=0xe812 & xrD & xrJ & xrK { + xrD = xvslt.wu(xrD, xrJ, xrK); +} + +define pcodeop xvslt.du; + +#lasx.txt xvslt.du mask=0x74098000 +#0x74098000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvslt.du xrD, xrJ, xrK is op15_31=0xe813 & xrD & xrJ & xrK { + xrD = xvslt.du(xrD, xrJ, xrK); +} + +define pcodeop xvadd.b; + +#lasx.txt xvadd.b mask=0x740a0000 +#0x740a0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadd.b xrD, xrJ, xrK is op15_31=0xe814 & xrD & xrJ & xrK { + xrD = xvadd.b(xrD, xrJ, xrK); +} + +define pcodeop xvadd.h; + +#lasx.txt xvadd.h mask=0x740a8000 +#0x740a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadd.h xrD, xrJ, xrK is op15_31=0xe815 & xrD & xrJ & xrK { + xrD = xvadd.h(xrD, xrJ, xrK); +} + +define pcodeop xvadd.w; + +#lasx.txt xvadd.w mask=0x740b0000 +#0x740b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadd.w xrD, xrJ, xrK is op15_31=0xe816 & xrD & xrJ & xrK { + xrD = xvadd.w(xrD, xrJ, xrK); +} + +define pcodeop xvadd.d; + +#lasx.txt xvadd.d mask=0x740b8000 +#0x740b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadd.d xrD, xrJ, xrK is op15_31=0xe817 & xrD & xrJ & xrK { + xrD = xvadd.d(xrD, xrJ, xrK); +} + +define pcodeop xvsub.b; + +#lasx.txt xvsub.b mask=0x740c0000 +#0x740c0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsub.b xrD, xrJ, xrK is op15_31=0xe818 & xrD & xrJ & xrK { + xrD = xvsub.b(xrD, xrJ, xrK); +} + +define pcodeop xvsub.h; + +#lasx.txt xvsub.h mask=0x740c8000 +#0x740c8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsub.h xrD, xrJ, xrK is op15_31=0xe819 & xrD & xrJ & xrK { + xrD = xvsub.h(xrD, xrJ, xrK); +} + +define pcodeop xvsub.w; + +#lasx.txt xvsub.w mask=0x740d0000 +#0x740d0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsub.w xrD, xrJ, xrK is op15_31=0xe81a & xrD & xrJ & xrK { + xrD = xvsub.w(xrD, xrJ, xrK); +} + +define pcodeop xvsub.d; + +#lasx.txt xvsub.d mask=0x740d8000 +#0x740d8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsub.d xrD, xrJ, xrK is op15_31=0xe81b & xrD & xrJ & xrK { + xrD = xvsub.d(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.h.b; + +#lasx.txt xvaddwev.h.b mask=0x741e0000 +#0x741e0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.h.b xrD, xrJ, xrK is op15_31=0xe83c & xrD & xrJ & xrK { + xrD = xvaddwev.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.w.h; + +#lasx.txt xvaddwev.w.h mask=0x741e8000 +#0x741e8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.w.h xrD, xrJ, xrK is op15_31=0xe83d & xrD & xrJ & xrK { + xrD = xvaddwev.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.d.w; + +#lasx.txt xvaddwev.d.w mask=0x741f0000 +#0x741f0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.d.w xrD, xrJ, xrK is op15_31=0xe83e & xrD & xrJ & xrK { + xrD = xvaddwev.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.q.d; + +#lasx.txt xvaddwev.q.d mask=0x741f8000 +#0x741f8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.q.d xrD, xrJ, xrK is op15_31=0xe83f & xrD & xrJ & xrK { + xrD = xvaddwev.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvsubwev.h.b; + +#lasx.txt xvsubwev.h.b mask=0x74200000 +#0x74200000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwev.h.b xrD, xrJ, xrK is op15_31=0xe840 & xrD & xrJ & xrK { + xrD = xvsubwev.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvsubwev.w.h; + +#lasx.txt xvsubwev.w.h mask=0x74208000 +#0x74208000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwev.w.h xrD, xrJ, xrK is op15_31=0xe841 & xrD & xrJ & xrK { + xrD = xvsubwev.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvsubwev.d.w; + +#lasx.txt xvsubwev.d.w mask=0x74210000 +#0x74210000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwev.d.w xrD, xrJ, xrK is op15_31=0xe842 & xrD & xrJ & xrK { + xrD = xvsubwev.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvsubwev.q.d; + +#lasx.txt xvsubwev.q.d mask=0x74218000 +#0x74218000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwev.q.d xrD, xrJ, xrK is op15_31=0xe843 & xrD & xrJ & xrK { + xrD = xvsubwev.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.h.b; + +#lasx.txt xvaddwod.h.b mask=0x74220000 +#0x74220000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.h.b xrD, xrJ, xrK is op15_31=0xe844 & xrD & xrJ & xrK { + xrD = xvaddwod.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.w.h; + +#lasx.txt xvaddwod.w.h mask=0x74228000 +#0x74228000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.w.h xrD, xrJ, xrK is op15_31=0xe845 & xrD & xrJ & xrK { + xrD = xvaddwod.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.d.w; + +#lasx.txt xvaddwod.d.w mask=0x74230000 +#0x74230000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.d.w xrD, xrJ, xrK is op15_31=0xe846 & xrD & xrJ & xrK { + xrD = xvaddwod.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.q.d; + +#lasx.txt xvaddwod.q.d mask=0x74238000 +#0x74238000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.q.d xrD, xrJ, xrK is op15_31=0xe847 & xrD & xrJ & xrK { + xrD = xvaddwod.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvsubwod.h.b; + +#lasx.txt xvsubwod.h.b mask=0x74240000 +#0x74240000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwod.h.b xrD, xrJ, xrK is op15_31=0xe848 & xrD & xrJ & xrK { + xrD = xvsubwod.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvsubwod.w.h; + +#lasx.txt xvsubwod.w.h mask=0x74248000 +#0x74248000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwod.w.h xrD, xrJ, xrK is op15_31=0xe849 & xrD & xrJ & xrK { + xrD = xvsubwod.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvsubwod.d.w; + +#lasx.txt xvsubwod.d.w mask=0x74250000 +#0x74250000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwod.d.w xrD, xrJ, xrK is op15_31=0xe84a & xrD & xrJ & xrK { + xrD = xvsubwod.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvsubwod.q.d; + +#lasx.txt xvsubwod.q.d mask=0x74258000 +#0x74258000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwod.q.d xrD, xrJ, xrK is op15_31=0xe84b & xrD & xrJ & xrK { + xrD = xvsubwod.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.h.bu; + +#lasx.txt xvaddwev.h.bu mask=0x742e0000 +#0x742e0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.h.bu xrD, xrJ, xrK is op15_31=0xe85c & xrD & xrJ & xrK { + xrD = xvaddwev.h.bu(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.w.hu; + +#lasx.txt xvaddwev.w.hu mask=0x742e8000 +#0x742e8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.w.hu xrD, xrJ, xrK is op15_31=0xe85d & xrD & xrJ & xrK { + xrD = xvaddwev.w.hu(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.d.wu; + +#lasx.txt xvaddwev.d.wu mask=0x742f0000 +#0x742f0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.d.wu xrD, xrJ, xrK is op15_31=0xe85e & xrD & xrJ & xrK { + xrD = xvaddwev.d.wu(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.q.du; + +#lasx.txt xvaddwev.q.du mask=0x742f8000 +#0x742f8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.q.du xrD, xrJ, xrK is op15_31=0xe85f & xrD & xrJ & xrK { + xrD = xvaddwev.q.du(xrD, xrJ, xrK); +} + +define pcodeop xvsubwev.h.bu; + +#lasx.txt xvsubwev.h.bu mask=0x74300000 +#0x74300000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwev.h.bu xrD, xrJ, xrK is op15_31=0xe860 & xrD & xrJ & xrK { + xrD = xvsubwev.h.bu(xrD, xrJ, xrK); +} + +define pcodeop xvsubwev.w.hu; + +#lasx.txt xvsubwev.w.hu mask=0x74308000 +#0x74308000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwev.w.hu xrD, xrJ, xrK is op15_31=0xe861 & xrD & xrJ & xrK { + xrD = xvsubwev.w.hu(xrD, xrJ, xrK); +} + +define pcodeop xvsubwev.d.wu; + +#lasx.txt xvsubwev.d.wu mask=0x74310000 +#0x74310000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwev.d.wu xrD, xrJ, xrK is op15_31=0xe862 & xrD & xrJ & xrK { + xrD = xvsubwev.d.wu(xrD, xrJ, xrK); +} + +define pcodeop xvsubwev.q.du; + +#lasx.txt xvsubwev.q.du mask=0x74318000 +#0x74318000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwev.q.du xrD, xrJ, xrK is op15_31=0xe863 & xrD & xrJ & xrK { + xrD = xvsubwev.q.du(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.h.bu; + +#lasx.txt xvaddwod.h.bu mask=0x74320000 +#0x74320000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.h.bu xrD, xrJ, xrK is op15_31=0xe864 & xrD & xrJ & xrK { + xrD = xvaddwod.h.bu(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.w.hu; + +#lasx.txt xvaddwod.w.hu mask=0x74328000 +#0x74328000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.w.hu xrD, xrJ, xrK is op15_31=0xe865 & xrD & xrJ & xrK { + xrD = xvaddwod.w.hu(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.d.wu; + +#lasx.txt xvaddwod.d.wu mask=0x74330000 +#0x74330000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.d.wu xrD, xrJ, xrK is op15_31=0xe866 & xrD & xrJ & xrK { + xrD = xvaddwod.d.wu(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.q.du; + +#lasx.txt xvaddwod.q.du mask=0x74338000 +#0x74338000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.q.du xrD, xrJ, xrK is op15_31=0xe867 & xrD & xrJ & xrK { + xrD = xvaddwod.q.du(xrD, xrJ, xrK); +} + +define pcodeop xvsubwod.h.bu; + +#lasx.txt xvsubwod.h.bu mask=0x74340000 +#0x74340000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwod.h.bu xrD, xrJ, xrK is op15_31=0xe868 & xrD & xrJ & xrK { + xrD = xvsubwod.h.bu(xrD, xrJ, xrK); +} + +define pcodeop xvsubwod.w.hu; + +#lasx.txt xvsubwod.w.hu mask=0x74348000 +#0x74348000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwod.w.hu xrD, xrJ, xrK is op15_31=0xe869 & xrD & xrJ & xrK { + xrD = xvsubwod.w.hu(xrD, xrJ, xrK); +} + +define pcodeop xvsubwod.d.wu; + +#lasx.txt xvsubwod.d.wu mask=0x74350000 +#0x74350000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwod.d.wu xrD, xrJ, xrK is op15_31=0xe86a & xrD & xrJ & xrK { + xrD = xvsubwod.d.wu(xrD, xrJ, xrK); +} + +define pcodeop xvsubwod.q.du; + +#lasx.txt xvsubwod.q.du mask=0x74358000 +#0x74358000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsubwod.q.du xrD, xrJ, xrK is op15_31=0xe86b & xrD & xrJ & xrK { + xrD = xvsubwod.q.du(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.h.bu.b; + +#lasx.txt xvaddwev.h.bu.b mask=0x743e0000 +#0x743e0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.h.bu.b xrD, xrJ, xrK is op15_31=0xe87c & xrD & xrJ & xrK { + xrD = xvaddwev.h.bu.b(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.w.hu.h; + +#lasx.txt xvaddwev.w.hu.h mask=0x743e8000 +#0x743e8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.w.hu.h xrD, xrJ, xrK is op15_31=0xe87d & xrD & xrJ & xrK { + xrD = xvaddwev.w.hu.h(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.d.wu.w; + +#lasx.txt xvaddwev.d.wu.w mask=0x743f0000 +#0x743f0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.d.wu.w xrD, xrJ, xrK is op15_31=0xe87e & xrD & xrJ & xrK { + xrD = xvaddwev.d.wu.w(xrD, xrJ, xrK); +} + +define pcodeop xvaddwev.q.du.d; + +#lasx.txt xvaddwev.q.du.d mask=0x743f8000 +#0x743f8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwev.q.du.d xrD, xrJ, xrK is op15_31=0xe87f & xrD & xrJ & xrK { + xrD = xvaddwev.q.du.d(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.h.bu.b; + +#lasx.txt xvaddwod.h.bu.b mask=0x74400000 +#0x74400000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.h.bu.b xrD, xrJ, xrK is op15_31=0xe880 & xrD & xrJ & xrK { + xrD = xvaddwod.h.bu.b(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.w.hu.h; + +#lasx.txt xvaddwod.w.hu.h mask=0x74408000 +#0x74408000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.w.hu.h xrD, xrJ, xrK is op15_31=0xe881 & xrD & xrJ & xrK { + xrD = xvaddwod.w.hu.h(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.d.wu.w; + +#lasx.txt xvaddwod.d.wu.w mask=0x74410000 +#0x74410000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.d.wu.w xrD, xrJ, xrK is op15_31=0xe882 & xrD & xrJ & xrK { + xrD = xvaddwod.d.wu.w(xrD, xrJ, xrK); +} + +define pcodeop xvaddwod.q.du.d; + +#lasx.txt xvaddwod.q.du.d mask=0x74418000 +#0x74418000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvaddwod.q.du.d xrD, xrJ, xrK is op15_31=0xe883 & xrD & xrJ & xrK { + xrD = xvaddwod.q.du.d(xrD, xrJ, xrK); +} + +define pcodeop xvsadd.b; + +#lasx.txt xvsadd.b mask=0x74460000 +#0x74460000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsadd.b xrD, xrJ, xrK is op15_31=0xe88c & xrD & xrJ & xrK { + xrD = xvsadd.b(xrD, xrJ, xrK); +} + +define pcodeop xvsadd.h; + +#lasx.txt xvsadd.h mask=0x74468000 +#0x74468000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsadd.h xrD, xrJ, xrK is op15_31=0xe88d & xrD & xrJ & xrK { + xrD = xvsadd.h(xrD, xrJ, xrK); +} + +define pcodeop xvsadd.w; + +#lasx.txt xvsadd.w mask=0x74470000 +#0x74470000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsadd.w xrD, xrJ, xrK is op15_31=0xe88e & xrD & xrJ & xrK { + xrD = xvsadd.w(xrD, xrJ, xrK); +} + +define pcodeop xvsadd.d; + +#lasx.txt xvsadd.d mask=0x74478000 +#0x74478000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsadd.d xrD, xrJ, xrK is op15_31=0xe88f & xrD & xrJ & xrK { + xrD = xvsadd.d(xrD, xrJ, xrK); +} + +define pcodeop xvssub.b; + +#lasx.txt xvssub.b mask=0x74480000 +#0x74480000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssub.b xrD, xrJ, xrK is op15_31=0xe890 & xrD & xrJ & xrK { + xrD = xvssub.b(xrD, xrJ, xrK); +} + +define pcodeop xvssub.h; + +#lasx.txt xvssub.h mask=0x74488000 +#0x74488000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssub.h xrD, xrJ, xrK is op15_31=0xe891 & xrD & xrJ & xrK { + xrD = xvssub.h(xrD, xrJ, xrK); +} + +define pcodeop xvssub.w; + +#lasx.txt xvssub.w mask=0x74490000 +#0x74490000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssub.w xrD, xrJ, xrK is op15_31=0xe892 & xrD & xrJ & xrK { + xrD = xvssub.w(xrD, xrJ, xrK); +} + +define pcodeop xvssub.d; + +#lasx.txt xvssub.d mask=0x74498000 +#0x74498000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssub.d xrD, xrJ, xrK is op15_31=0xe893 & xrD & xrJ & xrK { + xrD = xvssub.d(xrD, xrJ, xrK); +} + +define pcodeop xvsadd.bu; + +#lasx.txt xvsadd.bu mask=0x744a0000 +#0x744a0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsadd.bu xrD, xrJ, xrK is op15_31=0xe894 & xrD & xrJ & xrK { + xrD = xvsadd.bu(xrD, xrJ, xrK); +} + +define pcodeop xvsadd.hu; + +#lasx.txt xvsadd.hu mask=0x744a8000 +#0x744a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsadd.hu xrD, xrJ, xrK is op15_31=0xe895 & xrD & xrJ & xrK { + xrD = xvsadd.hu(xrD, xrJ, xrK); +} + +define pcodeop xvsadd.wu; + +#lasx.txt xvsadd.wu mask=0x744b0000 +#0x744b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsadd.wu xrD, xrJ, xrK is op15_31=0xe896 & xrD & xrJ & xrK { + xrD = xvsadd.wu(xrD, xrJ, xrK); +} + +define pcodeop xvsadd.du; + +#lasx.txt xvsadd.du mask=0x744b8000 +#0x744b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsadd.du xrD, xrJ, xrK is op15_31=0xe897 & xrD & xrJ & xrK { + xrD = xvsadd.du(xrD, xrJ, xrK); +} + +define pcodeop xvssub.bu; + +#lasx.txt xvssub.bu mask=0x744c0000 +#0x744c0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssub.bu xrD, xrJ, xrK is op15_31=0xe898 & xrD & xrJ & xrK { + xrD = xvssub.bu(xrD, xrJ, xrK); +} + +define pcodeop xvssub.hu; + +#lasx.txt xvssub.hu mask=0x744c8000 +#0x744c8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssub.hu xrD, xrJ, xrK is op15_31=0xe899 & xrD & xrJ & xrK { + xrD = xvssub.hu(xrD, xrJ, xrK); +} + +define pcodeop xvssub.wu; + +#lasx.txt xvssub.wu mask=0x744d0000 +#0x744d0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssub.wu xrD, xrJ, xrK is op15_31=0xe89a & xrD & xrJ & xrK { + xrD = xvssub.wu(xrD, xrJ, xrK); +} + +define pcodeop xvssub.du; + +#lasx.txt xvssub.du mask=0x744d8000 +#0x744d8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssub.du xrD, xrJ, xrK is op15_31=0xe89b & xrD & xrJ & xrK { + xrD = xvssub.du(xrD, xrJ, xrK); +} + +define pcodeop xvhaddw.h.b; + +#lasx.txt xvhaddw.h.b mask=0x74540000 +#0x74540000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhaddw.h.b xrD, xrJ, xrK is op15_31=0xe8a8 & xrD & xrJ & xrK { + xrD = xvhaddw.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvhaddw.w.h; + +#lasx.txt xvhaddw.w.h mask=0x74548000 +#0x74548000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhaddw.w.h xrD, xrJ, xrK is op15_31=0xe8a9 & xrD & xrJ & xrK { + xrD = xvhaddw.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvhaddw.d.w; + +#lasx.txt xvhaddw.d.w mask=0x74550000 +#0x74550000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhaddw.d.w xrD, xrJ, xrK is op15_31=0xe8aa & xrD & xrJ & xrK { + xrD = xvhaddw.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvhaddw.q.d; + +#lasx.txt xvhaddw.q.d mask=0x74558000 +#0x74558000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhaddw.q.d xrD, xrJ, xrK is op15_31=0xe8ab & xrD & xrJ & xrK { + xrD = xvhaddw.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvhsubw.h.b; + +#lasx.txt xvhsubw.h.b mask=0x74560000 +#0x74560000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhsubw.h.b xrD, xrJ, xrK is op15_31=0xe8ac & xrD & xrJ & xrK { + xrD = xvhsubw.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvhsubw.w.h; + +#lasx.txt xvhsubw.w.h mask=0x74568000 +#0x74568000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhsubw.w.h xrD, xrJ, xrK is op15_31=0xe8ad & xrD & xrJ & xrK { + xrD = xvhsubw.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvhsubw.d.w; + +#lasx.txt xvhsubw.d.w mask=0x74570000 +#0x74570000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhsubw.d.w xrD, xrJ, xrK is op15_31=0xe8ae & xrD & xrJ & xrK { + xrD = xvhsubw.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvhsubw.q.d; + +#lasx.txt xvhsubw.q.d mask=0x74578000 +#0x74578000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhsubw.q.d xrD, xrJ, xrK is op15_31=0xe8af & xrD & xrJ & xrK { + xrD = xvhsubw.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvhaddw.hu.bu; + +#lasx.txt xvhaddw.hu.bu mask=0x74580000 +#0x74580000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhaddw.hu.bu xrD, xrJ, xrK is op15_31=0xe8b0 & xrD & xrJ & xrK { + xrD = xvhaddw.hu.bu(xrD, xrJ, xrK); +} + +define pcodeop xvhaddw.wu.hu; + +#lasx.txt xvhaddw.wu.hu mask=0x74588000 +#0x74588000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhaddw.wu.hu xrD, xrJ, xrK is op15_31=0xe8b1 & xrD & xrJ & xrK { + xrD = xvhaddw.wu.hu(xrD, xrJ, xrK); +} + +define pcodeop xvhaddw.du.wu; + +#lasx.txt xvhaddw.du.wu mask=0x74590000 +#0x74590000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhaddw.du.wu xrD, xrJ, xrK is op15_31=0xe8b2 & xrD & xrJ & xrK { + xrD = xvhaddw.du.wu(xrD, xrJ, xrK); +} + +define pcodeop xvhaddw.qu.du; + +#lasx.txt xvhaddw.qu.du mask=0x74598000 +#0x74598000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhaddw.qu.du xrD, xrJ, xrK is op15_31=0xe8b3 & xrD & xrJ & xrK { + xrD = xvhaddw.qu.du(xrD, xrJ, xrK); +} + +define pcodeop xvhsubw.hu.bu; + +#lasx.txt xvhsubw.hu.bu mask=0x745a0000 +#0x745a0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhsubw.hu.bu xrD, xrJ, xrK is op15_31=0xe8b4 & xrD & xrJ & xrK { + xrD = xvhsubw.hu.bu(xrD, xrJ, xrK); +} + +define pcodeop xvhsubw.wu.hu; + +#lasx.txt xvhsubw.wu.hu mask=0x745a8000 +#0x745a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhsubw.wu.hu xrD, xrJ, xrK is op15_31=0xe8b5 & xrD & xrJ & xrK { + xrD = xvhsubw.wu.hu(xrD, xrJ, xrK); +} + +define pcodeop xvhsubw.du.wu; + +#lasx.txt xvhsubw.du.wu mask=0x745b0000 +#0x745b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhsubw.du.wu xrD, xrJ, xrK is op15_31=0xe8b6 & xrD & xrJ & xrK { + xrD = xvhsubw.du.wu(xrD, xrJ, xrK); +} + +define pcodeop xvhsubw.qu.du; + +#lasx.txt xvhsubw.qu.du mask=0x745b8000 +#0x745b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvhsubw.qu.du xrD, xrJ, xrK is op15_31=0xe8b7 & xrD & xrJ & xrK { + xrD = xvhsubw.qu.du(xrD, xrJ, xrK); +} + +define pcodeop xvadda.b; + +#lasx.txt xvadda.b mask=0x745c0000 +#0x745c0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadda.b xrD, xrJ, xrK is op15_31=0xe8b8 & xrD & xrJ & xrK { + xrD = xvadda.b(xrD, xrJ, xrK); +} + +define pcodeop xvadda.h; + +#lasx.txt xvadda.h mask=0x745c8000 +#0x745c8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadda.h xrD, xrJ, xrK is op15_31=0xe8b9 & xrD & xrJ & xrK { + xrD = xvadda.h(xrD, xrJ, xrK); +} + +define pcodeop xvadda.w; + +#lasx.txt xvadda.w mask=0x745d0000 +#0x745d0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadda.w xrD, xrJ, xrK is op15_31=0xe8ba & xrD & xrJ & xrK { + xrD = xvadda.w(xrD, xrJ, xrK); +} + +define pcodeop xvadda.d; + +#lasx.txt xvadda.d mask=0x745d8000 +#0x745d8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadda.d xrD, xrJ, xrK is op15_31=0xe8bb & xrD & xrJ & xrK { + xrD = xvadda.d(xrD, xrJ, xrK); +} + +define pcodeop xvabsd.b; + +#lasx.txt xvabsd.b mask=0x74600000 +#0x74600000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvabsd.b xrD, xrJ, xrK is op15_31=0xe8c0 & xrD & xrJ & xrK { + xrD = xvabsd.b(xrD, xrJ, xrK); +} + +define pcodeop xvabsd.h; + +#lasx.txt xvabsd.h mask=0x74608000 +#0x74608000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvabsd.h xrD, xrJ, xrK is op15_31=0xe8c1 & xrD & xrJ & xrK { + xrD = xvabsd.h(xrD, xrJ, xrK); +} + +define pcodeop xvabsd.w; + +#lasx.txt xvabsd.w mask=0x74610000 +#0x74610000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvabsd.w xrD, xrJ, xrK is op15_31=0xe8c2 & xrD & xrJ & xrK { + xrD = xvabsd.w(xrD, xrJ, xrK); +} + +define pcodeop xvabsd.d; + +#lasx.txt xvabsd.d mask=0x74618000 +#0x74618000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvabsd.d xrD, xrJ, xrK is op15_31=0xe8c3 & xrD & xrJ & xrK { + xrD = xvabsd.d(xrD, xrJ, xrK); +} + +define pcodeop xvabsd.bu; + +#lasx.txt xvabsd.bu mask=0x74620000 +#0x74620000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvabsd.bu xrD, xrJ, xrK is op15_31=0xe8c4 & xrD & xrJ & xrK { + xrD = xvabsd.bu(xrD, xrJ, xrK); +} + +define pcodeop xvabsd.hu; + +#lasx.txt xvabsd.hu mask=0x74628000 +#0x74628000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvabsd.hu xrD, xrJ, xrK is op15_31=0xe8c5 & xrD & xrJ & xrK { + xrD = xvabsd.hu(xrD, xrJ, xrK); +} + +define pcodeop xvabsd.wu; + +#lasx.txt xvabsd.wu mask=0x74630000 +#0x74630000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvabsd.wu xrD, xrJ, xrK is op15_31=0xe8c6 & xrD & xrJ & xrK { + xrD = xvabsd.wu(xrD, xrJ, xrK); +} + +define pcodeop xvabsd.du; + +#lasx.txt xvabsd.du mask=0x74638000 +#0x74638000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvabsd.du xrD, xrJ, xrK is op15_31=0xe8c7 & xrD & xrJ & xrK { + xrD = xvabsd.du(xrD, xrJ, xrK); +} + +define pcodeop xvavg.b; + +#lasx.txt xvavg.b mask=0x74640000 +#0x74640000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavg.b xrD, xrJ, xrK is op15_31=0xe8c8 & xrD & xrJ & xrK { + xrD = xvavg.b(xrD, xrJ, xrK); +} + +define pcodeop xvavg.h; + +#lasx.txt xvavg.h mask=0x74648000 +#0x74648000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavg.h xrD, xrJ, xrK is op15_31=0xe8c9 & xrD & xrJ & xrK { + xrD = xvavg.h(xrD, xrJ, xrK); +} + +define pcodeop xvavg.w; + +#lasx.txt xvavg.w mask=0x74650000 +#0x74650000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavg.w xrD, xrJ, xrK is op15_31=0xe8ca & xrD & xrJ & xrK { + xrD = xvavg.w(xrD, xrJ, xrK); +} + +define pcodeop xvavg.d; + +#lasx.txt xvavg.d mask=0x74658000 +#0x74658000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavg.d xrD, xrJ, xrK is op15_31=0xe8cb & xrD & xrJ & xrK { + xrD = xvavg.d(xrD, xrJ, xrK); +} + +define pcodeop xvavg.bu; + +#lasx.txt xvavg.bu mask=0x74660000 +#0x74660000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavg.bu xrD, xrJ, xrK is op15_31=0xe8cc & xrD & xrJ & xrK { + xrD = xvavg.bu(xrD, xrJ, xrK); +} + +define pcodeop xvavg.hu; + +#lasx.txt xvavg.hu mask=0x74668000 +#0x74668000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavg.hu xrD, xrJ, xrK is op15_31=0xe8cd & xrD & xrJ & xrK { + xrD = xvavg.hu(xrD, xrJ, xrK); +} + +define pcodeop xvavg.wu; + +#lasx.txt xvavg.wu mask=0x74670000 +#0x74670000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavg.wu xrD, xrJ, xrK is op15_31=0xe8ce & xrD & xrJ & xrK { + xrD = xvavg.wu(xrD, xrJ, xrK); +} + +define pcodeop xvavg.du; + +#lasx.txt xvavg.du mask=0x74678000 +#0x74678000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavg.du xrD, xrJ, xrK is op15_31=0xe8cf & xrD & xrJ & xrK { + xrD = xvavg.du(xrD, xrJ, xrK); +} + +define pcodeop xvavgr.b; + +#lasx.txt xvavgr.b mask=0x74680000 +#0x74680000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavgr.b xrD, xrJ, xrK is op15_31=0xe8d0 & xrD & xrJ & xrK { + xrD = xvavgr.b(xrD, xrJ, xrK); +} + +define pcodeop xvavgr.h; + +#lasx.txt xvavgr.h mask=0x74688000 +#0x74688000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavgr.h xrD, xrJ, xrK is op15_31=0xe8d1 & xrD & xrJ & xrK { + xrD = xvavgr.h(xrD, xrJ, xrK); +} + +define pcodeop xvavgr.w; + +#lasx.txt xvavgr.w mask=0x74690000 +#0x74690000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavgr.w xrD, xrJ, xrK is op15_31=0xe8d2 & xrD & xrJ & xrK { + xrD = xvavgr.w(xrD, xrJ, xrK); +} + +define pcodeop xvavgr.d; + +#lasx.txt xvavgr.d mask=0x74698000 +#0x74698000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavgr.d xrD, xrJ, xrK is op15_31=0xe8d3 & xrD & xrJ & xrK { + xrD = xvavgr.d(xrD, xrJ, xrK); +} + +define pcodeop xvavgr.bu; + +#lasx.txt xvavgr.bu mask=0x746a0000 +#0x746a0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavgr.bu xrD, xrJ, xrK is op15_31=0xe8d4 & xrD & xrJ & xrK { + xrD = xvavgr.bu(xrD, xrJ, xrK); +} + +define pcodeop xvavgr.hu; + +#lasx.txt xvavgr.hu mask=0x746a8000 +#0x746a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavgr.hu xrD, xrJ, xrK is op15_31=0xe8d5 & xrD & xrJ & xrK { + xrD = xvavgr.hu(xrD, xrJ, xrK); +} + +define pcodeop xvavgr.wu; + +#lasx.txt xvavgr.wu mask=0x746b0000 +#0x746b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavgr.wu xrD, xrJ, xrK is op15_31=0xe8d6 & xrD & xrJ & xrK { + xrD = xvavgr.wu(xrD, xrJ, xrK); +} + +define pcodeop xvavgr.du; + +#lasx.txt xvavgr.du mask=0x746b8000 +#0x746b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvavgr.du xrD, xrJ, xrK is op15_31=0xe8d7 & xrD & xrJ & xrK { + xrD = xvavgr.du(xrD, xrJ, xrK); +} + +define pcodeop xvmax.b; + +#lasx.txt xvmax.b mask=0x74700000 +#0x74700000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmax.b xrD, xrJ, xrK is op15_31=0xe8e0 & xrD & xrJ & xrK { + xrD = xvmax.b(xrD, xrJ, xrK); +} + +define pcodeop xvmax.h; + +#lasx.txt xvmax.h mask=0x74708000 +#0x74708000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmax.h xrD, xrJ, xrK is op15_31=0xe8e1 & xrD & xrJ & xrK { + xrD = xvmax.h(xrD, xrJ, xrK); +} + +define pcodeop xvmax.w; + +#lasx.txt xvmax.w mask=0x74710000 +#0x74710000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmax.w xrD, xrJ, xrK is op15_31=0xe8e2 & xrD & xrJ & xrK { + xrD = xvmax.w(xrD, xrJ, xrK); +} + +define pcodeop xvmax.d; + +#lasx.txt xvmax.d mask=0x74718000 +#0x74718000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmax.d xrD, xrJ, xrK is op15_31=0xe8e3 & xrD & xrJ & xrK { + xrD = xvmax.d(xrD, xrJ, xrK); +} + +define pcodeop xvmin.b; + +#lasx.txt xvmin.b mask=0x74720000 +#0x74720000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmin.b xrD, xrJ, xrK is op15_31=0xe8e4 & xrD & xrJ & xrK { + xrD = xvmin.b(xrD, xrJ, xrK); +} + +define pcodeop xvmin.h; + +#lasx.txt xvmin.h mask=0x74728000 +#0x74728000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmin.h xrD, xrJ, xrK is op15_31=0xe8e5 & xrD & xrJ & xrK { + xrD = xvmin.h(xrD, xrJ, xrK); +} + +define pcodeop xvmin.w; + +#lasx.txt xvmin.w mask=0x74730000 +#0x74730000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmin.w xrD, xrJ, xrK is op15_31=0xe8e6 & xrD & xrJ & xrK { + xrD = xvmin.w(xrD, xrJ, xrK); +} + +define pcodeop xvmin.d; + +#lasx.txt xvmin.d mask=0x74738000 +#0x74738000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmin.d xrD, xrJ, xrK is op15_31=0xe8e7 & xrD & xrJ & xrK { + xrD = xvmin.d(xrD, xrJ, xrK); +} + +define pcodeop xvmax.bu; + +#lasx.txt xvmax.bu mask=0x74740000 +#0x74740000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmax.bu xrD, xrJ, xrK is op15_31=0xe8e8 & xrD & xrJ & xrK { + xrD = xvmax.bu(xrD, xrJ, xrK); +} + +define pcodeop xvmax.hu; + +#lasx.txt xvmax.hu mask=0x74748000 +#0x74748000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmax.hu xrD, xrJ, xrK is op15_31=0xe8e9 & xrD & xrJ & xrK { + xrD = xvmax.hu(xrD, xrJ, xrK); +} + +define pcodeop xvmax.wu; + +#lasx.txt xvmax.wu mask=0x74750000 +#0x74750000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmax.wu xrD, xrJ, xrK is op15_31=0xe8ea & xrD & xrJ & xrK { + xrD = xvmax.wu(xrD, xrJ, xrK); +} + +define pcodeop xvmax.du; + +#lasx.txt xvmax.du mask=0x74758000 +#0x74758000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmax.du xrD, xrJ, xrK is op15_31=0xe8eb & xrD & xrJ & xrK { + xrD = xvmax.du(xrD, xrJ, xrK); +} + +define pcodeop xvmin.bu; + +#lasx.txt xvmin.bu mask=0x74760000 +#0x74760000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmin.bu xrD, xrJ, xrK is op15_31=0xe8ec & xrD & xrJ & xrK { + xrD = xvmin.bu(xrD, xrJ, xrK); +} + +define pcodeop xvmin.hu; + +#lasx.txt xvmin.hu mask=0x74768000 +#0x74768000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmin.hu xrD, xrJ, xrK is op15_31=0xe8ed & xrD & xrJ & xrK { + xrD = xvmin.hu(xrD, xrJ, xrK); +} + +define pcodeop xvmin.wu; + +#lasx.txt xvmin.wu mask=0x74770000 +#0x74770000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmin.wu xrD, xrJ, xrK is op15_31=0xe8ee & xrD & xrJ & xrK { + xrD = xvmin.wu(xrD, xrJ, xrK); +} + +define pcodeop xvmin.du; + +#lasx.txt xvmin.du mask=0x74778000 +#0x74778000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmin.du xrD, xrJ, xrK is op15_31=0xe8ef & xrD & xrJ & xrK { + xrD = xvmin.du(xrD, xrJ, xrK); +} + +define pcodeop xvmul.b; + +#lasx.txt xvmul.b mask=0x74840000 +#0x74840000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmul.b xrD, xrJ, xrK is op15_31=0xe908 & xrD & xrJ & xrK { + xrD = xvmul.b(xrD, xrJ, xrK); +} + +define pcodeop xvmul.h; + +#lasx.txt xvmul.h mask=0x74848000 +#0x74848000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmul.h xrD, xrJ, xrK is op15_31=0xe909 & xrD & xrJ & xrK { + xrD = xvmul.h(xrD, xrJ, xrK); +} + +define pcodeop xvmul.w; + +#lasx.txt xvmul.w mask=0x74850000 +#0x74850000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmul.w xrD, xrJ, xrK is op15_31=0xe90a & xrD & xrJ & xrK { + xrD = xvmul.w(xrD, xrJ, xrK); +} + +define pcodeop xvmul.d; + +#lasx.txt xvmul.d mask=0x74858000 +#0x74858000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmul.d xrD, xrJ, xrK is op15_31=0xe90b & xrD & xrJ & xrK { + xrD = xvmul.d(xrD, xrJ, xrK); +} + +define pcodeop xvmuh.b; + +#lasx.txt xvmuh.b mask=0x74860000 +#0x74860000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmuh.b xrD, xrJ, xrK is op15_31=0xe90c & xrD & xrJ & xrK { + xrD = xvmuh.b(xrD, xrJ, xrK); +} + +define pcodeop xvmuh.h; + +#lasx.txt xvmuh.h mask=0x74868000 +#0x74868000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmuh.h xrD, xrJ, xrK is op15_31=0xe90d & xrD & xrJ & xrK { + xrD = xvmuh.h(xrD, xrJ, xrK); +} + +define pcodeop xvmuh.w; + +#lasx.txt xvmuh.w mask=0x74870000 +#0x74870000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmuh.w xrD, xrJ, xrK is op15_31=0xe90e & xrD & xrJ & xrK { + xrD = xvmuh.w(xrD, xrJ, xrK); +} + +define pcodeop xvmuh.d; + +#lasx.txt xvmuh.d mask=0x74878000 +#0x74878000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmuh.d xrD, xrJ, xrK is op15_31=0xe90f & xrD & xrJ & xrK { + xrD = xvmuh.d(xrD, xrJ, xrK); +} + +define pcodeop xvmuh.bu; + +#lasx.txt xvmuh.bu mask=0x74880000 +#0x74880000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmuh.bu xrD, xrJ, xrK is op15_31=0xe910 & xrD & xrJ & xrK { + xrD = xvmuh.bu(xrD, xrJ, xrK); +} + +define pcodeop xvmuh.hu; + +#lasx.txt xvmuh.hu mask=0x74888000 +#0x74888000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmuh.hu xrD, xrJ, xrK is op15_31=0xe911 & xrD & xrJ & xrK { + xrD = xvmuh.hu(xrD, xrJ, xrK); +} + +define pcodeop xvmuh.wu; + +#lasx.txt xvmuh.wu mask=0x74890000 +#0x74890000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmuh.wu xrD, xrJ, xrK is op15_31=0xe912 & xrD & xrJ & xrK { + xrD = xvmuh.wu(xrD, xrJ, xrK); +} + +define pcodeop xvmuh.du; + +#lasx.txt xvmuh.du mask=0x74898000 +#0x74898000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmuh.du xrD, xrJ, xrK is op15_31=0xe913 & xrD & xrJ & xrK { + xrD = xvmuh.du(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.h.b; + +#lasx.txt xvmulwev.h.b mask=0x74900000 +#0x74900000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.h.b xrD, xrJ, xrK is op15_31=0xe920 & xrD & xrJ & xrK { + xrD = xvmulwev.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.w.h; + +#lasx.txt xvmulwev.w.h mask=0x74908000 +#0x74908000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.w.h xrD, xrJ, xrK is op15_31=0xe921 & xrD & xrJ & xrK { + xrD = xvmulwev.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.d.w; + +#lasx.txt xvmulwev.d.w mask=0x74910000 +#0x74910000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.d.w xrD, xrJ, xrK is op15_31=0xe922 & xrD & xrJ & xrK { + xrD = xvmulwev.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.q.d; + +#lasx.txt xvmulwev.q.d mask=0x74918000 +#0x74918000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.q.d xrD, xrJ, xrK is op15_31=0xe923 & xrD & xrJ & xrK { + xrD = xvmulwev.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.h.b; + +#lasx.txt xvmulwod.h.b mask=0x74920000 +#0x74920000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.h.b xrD, xrJ, xrK is op15_31=0xe924 & xrD & xrJ & xrK { + xrD = xvmulwod.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.w.h; + +#lasx.txt xvmulwod.w.h mask=0x74928000 +#0x74928000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.w.h xrD, xrJ, xrK is op15_31=0xe925 & xrD & xrJ & xrK { + xrD = xvmulwod.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.d.w; + +#lasx.txt xvmulwod.d.w mask=0x74930000 +#0x74930000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.d.w xrD, xrJ, xrK is op15_31=0xe926 & xrD & xrJ & xrK { + xrD = xvmulwod.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.q.d; + +#lasx.txt xvmulwod.q.d mask=0x74938000 +#0x74938000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.q.d xrD, xrJ, xrK is op15_31=0xe927 & xrD & xrJ & xrK { + xrD = xvmulwod.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.h.bu; + +#lasx.txt xvmulwev.h.bu mask=0x74980000 +#0x74980000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.h.bu xrD, xrJ, xrK is op15_31=0xe930 & xrD & xrJ & xrK { + xrD = xvmulwev.h.bu(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.w.hu; + +#lasx.txt xvmulwev.w.hu mask=0x74988000 +#0x74988000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.w.hu xrD, xrJ, xrK is op15_31=0xe931 & xrD & xrJ & xrK { + xrD = xvmulwev.w.hu(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.d.wu; + +#lasx.txt xvmulwev.d.wu mask=0x74990000 +#0x74990000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.d.wu xrD, xrJ, xrK is op15_31=0xe932 & xrD & xrJ & xrK { + xrD = xvmulwev.d.wu(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.q.du; + +#lasx.txt xvmulwev.q.du mask=0x74998000 +#0x74998000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.q.du xrD, xrJ, xrK is op15_31=0xe933 & xrD & xrJ & xrK { + xrD = xvmulwev.q.du(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.h.bu; + +#lasx.txt xvmulwod.h.bu mask=0x749a0000 +#0x749a0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.h.bu xrD, xrJ, xrK is op15_31=0xe934 & xrD & xrJ & xrK { + xrD = xvmulwod.h.bu(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.w.hu; + +#lasx.txt xvmulwod.w.hu mask=0x749a8000 +#0x749a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.w.hu xrD, xrJ, xrK is op15_31=0xe935 & xrD & xrJ & xrK { + xrD = xvmulwod.w.hu(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.d.wu; + +#lasx.txt xvmulwod.d.wu mask=0x749b0000 +#0x749b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.d.wu xrD, xrJ, xrK is op15_31=0xe936 & xrD & xrJ & xrK { + xrD = xvmulwod.d.wu(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.q.du; + +#lasx.txt xvmulwod.q.du mask=0x749b8000 +#0x749b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.q.du xrD, xrJ, xrK is op15_31=0xe937 & xrD & xrJ & xrK { + xrD = xvmulwod.q.du(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.h.bu.b; + +#lasx.txt xvmulwev.h.bu.b mask=0x74a00000 +#0x74a00000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.h.bu.b xrD, xrJ, xrK is op15_31=0xe940 & xrD & xrJ & xrK { + xrD = xvmulwev.h.bu.b(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.w.hu.h; + +#lasx.txt xvmulwev.w.hu.h mask=0x74a08000 +#0x74a08000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.w.hu.h xrD, xrJ, xrK is op15_31=0xe941 & xrD & xrJ & xrK { + xrD = xvmulwev.w.hu.h(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.d.wu.w; + +#lasx.txt xvmulwev.d.wu.w mask=0x74a10000 +#0x74a10000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.d.wu.w xrD, xrJ, xrK is op15_31=0xe942 & xrD & xrJ & xrK { + xrD = xvmulwev.d.wu.w(xrD, xrJ, xrK); +} + +define pcodeop xvmulwev.q.du.d; + +#lasx.txt xvmulwev.q.du.d mask=0x74a18000 +#0x74a18000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwev.q.du.d xrD, xrJ, xrK is op15_31=0xe943 & xrD & xrJ & xrK { + xrD = xvmulwev.q.du.d(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.h.bu.b; + +#lasx.txt xvmulwod.h.bu.b mask=0x74a20000 +#0x74a20000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.h.bu.b xrD, xrJ, xrK is op15_31=0xe944 & xrD & xrJ & xrK { + xrD = xvmulwod.h.bu.b(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.w.hu.h; + +#lasx.txt xvmulwod.w.hu.h mask=0x74a28000 +#0x74a28000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.w.hu.h xrD, xrJ, xrK is op15_31=0xe945 & xrD & xrJ & xrK { + xrD = xvmulwod.w.hu.h(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.d.wu.w; + +#lasx.txt xvmulwod.d.wu.w mask=0x74a30000 +#0x74a30000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.d.wu.w xrD, xrJ, xrK is op15_31=0xe946 & xrD & xrJ & xrK { + xrD = xvmulwod.d.wu.w(xrD, xrJ, xrK); +} + +define pcodeop xvmulwod.q.du.d; + +#lasx.txt xvmulwod.q.du.d mask=0x74a38000 +#0x74a38000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmulwod.q.du.d xrD, xrJ, xrK is op15_31=0xe947 & xrD & xrJ & xrK { + xrD = xvmulwod.q.du.d(xrD, xrJ, xrK); +} + +define pcodeop xvmadd.b; + +#lasx.txt xvmadd.b mask=0x74a80000 +#0x74a80000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmadd.b xrD, xrJ, xrK is op15_31=0xe950 & xrD & xrJ & xrK { + xrD = xvmadd.b(xrD, xrJ, xrK); +} + +define pcodeop xvmadd.h; + +#lasx.txt xvmadd.h mask=0x74a88000 +#0x74a88000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmadd.h xrD, xrJ, xrK is op15_31=0xe951 & xrD & xrJ & xrK { + xrD = xvmadd.h(xrD, xrJ, xrK); +} + +define pcodeop xvmadd.w; + +#lasx.txt xvmadd.w mask=0x74a90000 +#0x74a90000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmadd.w xrD, xrJ, xrK is op15_31=0xe952 & xrD & xrJ & xrK { + xrD = xvmadd.w(xrD, xrJ, xrK); +} + +define pcodeop xvmadd.d; + +#lasx.txt xvmadd.d mask=0x74a98000 +#0x74a98000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmadd.d xrD, xrJ, xrK is op15_31=0xe953 & xrD & xrJ & xrK { + xrD = xvmadd.d(xrD, xrJ, xrK); +} + +define pcodeop xvmsub.b; + +#lasx.txt xvmsub.b mask=0x74aa0000 +#0x74aa0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmsub.b xrD, xrJ, xrK is op15_31=0xe954 & xrD & xrJ & xrK { + xrD = xvmsub.b(xrD, xrJ, xrK); +} + +define pcodeop xvmsub.h; + +#lasx.txt xvmsub.h mask=0x74aa8000 +#0x74aa8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmsub.h xrD, xrJ, xrK is op15_31=0xe955 & xrD & xrJ & xrK { + xrD = xvmsub.h(xrD, xrJ, xrK); +} + +define pcodeop xvmsub.w; + +#lasx.txt xvmsub.w mask=0x74ab0000 +#0x74ab0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmsub.w xrD, xrJ, xrK is op15_31=0xe956 & xrD & xrJ & xrK { + xrD = xvmsub.w(xrD, xrJ, xrK); +} + +define pcodeop xvmsub.d; + +#lasx.txt xvmsub.d mask=0x74ab8000 +#0x74ab8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmsub.d xrD, xrJ, xrK is op15_31=0xe957 & xrD & xrJ & xrK { + xrD = xvmsub.d(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.h.b; + +#lasx.txt xvmaddwev.h.b mask=0x74ac0000 +#0x74ac0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.h.b xrD, xrJ, xrK is op15_31=0xe958 & xrD & xrJ & xrK { + xrD = xvmaddwev.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.w.h; + +#lasx.txt xvmaddwev.w.h mask=0x74ac8000 +#0x74ac8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.w.h xrD, xrJ, xrK is op15_31=0xe959 & xrD & xrJ & xrK { + xrD = xvmaddwev.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.d.w; + +#lasx.txt xvmaddwev.d.w mask=0x74ad0000 +#0x74ad0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.d.w xrD, xrJ, xrK is op15_31=0xe95a & xrD & xrJ & xrK { + xrD = xvmaddwev.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.q.d; + +#lasx.txt xvmaddwev.q.d mask=0x74ad8000 +#0x74ad8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.q.d xrD, xrJ, xrK is op15_31=0xe95b & xrD & xrJ & xrK { + xrD = xvmaddwev.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.h.b; + +#lasx.txt xvmaddwod.h.b mask=0x74ae0000 +#0x74ae0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.h.b xrD, xrJ, xrK is op15_31=0xe95c & xrD & xrJ & xrK { + xrD = xvmaddwod.h.b(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.w.h; + +#lasx.txt xvmaddwod.w.h mask=0x74ae8000 +#0x74ae8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.w.h xrD, xrJ, xrK is op15_31=0xe95d & xrD & xrJ & xrK { + xrD = xvmaddwod.w.h(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.d.w; + +#lasx.txt xvmaddwod.d.w mask=0x74af0000 +#0x74af0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.d.w xrD, xrJ, xrK is op15_31=0xe95e & xrD & xrJ & xrK { + xrD = xvmaddwod.d.w(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.q.d; + +#lasx.txt xvmaddwod.q.d mask=0x74af8000 +#0x74af8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.q.d xrD, xrJ, xrK is op15_31=0xe95f & xrD & xrJ & xrK { + xrD = xvmaddwod.q.d(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.h.bu; + +#lasx.txt xvmaddwev.h.bu mask=0x74b40000 +#0x74b40000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.h.bu xrD, xrJ, xrK is op15_31=0xe968 & xrD & xrJ & xrK { + xrD = xvmaddwev.h.bu(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.w.hu; + +#lasx.txt xvmaddwev.w.hu mask=0x74b48000 +#0x74b48000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.w.hu xrD, xrJ, xrK is op15_31=0xe969 & xrD & xrJ & xrK { + xrD = xvmaddwev.w.hu(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.d.wu; + +#lasx.txt xvmaddwev.d.wu mask=0x74b50000 +#0x74b50000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.d.wu xrD, xrJ, xrK is op15_31=0xe96a & xrD & xrJ & xrK { + xrD = xvmaddwev.d.wu(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.q.du; + +#lasx.txt xvmaddwev.q.du mask=0x74b58000 +#0x74b58000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.q.du xrD, xrJ, xrK is op15_31=0xe96b & xrD & xrJ & xrK { + xrD = xvmaddwev.q.du(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.h.bu; + +#lasx.txt xvmaddwod.h.bu mask=0x74b60000 +#0x74b60000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.h.bu xrD, xrJ, xrK is op15_31=0xe96c & xrD & xrJ & xrK { + xrD = xvmaddwod.h.bu(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.w.hu; + +#lasx.txt xvmaddwod.w.hu mask=0x74b68000 +#0x74b68000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.w.hu xrD, xrJ, xrK is op15_31=0xe96d & xrD & xrJ & xrK { + xrD = xvmaddwod.w.hu(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.d.wu; + +#lasx.txt xvmaddwod.d.wu mask=0x74b70000 +#0x74b70000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.d.wu xrD, xrJ, xrK is op15_31=0xe96e & xrD & xrJ & xrK { + xrD = xvmaddwod.d.wu(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.q.du; + +#lasx.txt xvmaddwod.q.du mask=0x74b78000 +#0x74b78000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.q.du xrD, xrJ, xrK is op15_31=0xe96f & xrD & xrJ & xrK { + xrD = xvmaddwod.q.du(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.h.bu.b; + +#lasx.txt xvmaddwev.h.bu.b mask=0x74bc0000 +#0x74bc0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.h.bu.b xrD, xrJ, xrK is op15_31=0xe978 & xrD & xrJ & xrK { + xrD = xvmaddwev.h.bu.b(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.w.hu.h; + +#lasx.txt xvmaddwev.w.hu.h mask=0x74bc8000 +#0x74bc8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.w.hu.h xrD, xrJ, xrK is op15_31=0xe979 & xrD & xrJ & xrK { + xrD = xvmaddwev.w.hu.h(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.d.wu.w; + +#lasx.txt xvmaddwev.d.wu.w mask=0x74bd0000 +#0x74bd0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.d.wu.w xrD, xrJ, xrK is op15_31=0xe97a & xrD & xrJ & xrK { + xrD = xvmaddwev.d.wu.w(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwev.q.du.d; + +#lasx.txt xvmaddwev.q.du.d mask=0x74bd8000 +#0x74bd8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwev.q.du.d xrD, xrJ, xrK is op15_31=0xe97b & xrD & xrJ & xrK { + xrD = xvmaddwev.q.du.d(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.h.bu.b; + +#lasx.txt xvmaddwod.h.bu.b mask=0x74be0000 +#0x74be0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.h.bu.b xrD, xrJ, xrK is op15_31=0xe97c & xrD & xrJ & xrK { + xrD = xvmaddwod.h.bu.b(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.w.hu.h; + +#lasx.txt xvmaddwod.w.hu.h mask=0x74be8000 +#0x74be8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.w.hu.h xrD, xrJ, xrK is op15_31=0xe97d & xrD & xrJ & xrK { + xrD = xvmaddwod.w.hu.h(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.d.wu.w; + +#lasx.txt xvmaddwod.d.wu.w mask=0x74bf0000 +#0x74bf0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.d.wu.w xrD, xrJ, xrK is op15_31=0xe97e & xrD & xrJ & xrK { + xrD = xvmaddwod.d.wu.w(xrD, xrJ, xrK); +} + +define pcodeop xvmaddwod.q.du.d; + +#lasx.txt xvmaddwod.q.du.d mask=0x74bf8000 +#0x74bf8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmaddwod.q.du.d xrD, xrJ, xrK is op15_31=0xe97f & xrD & xrJ & xrK { + xrD = xvmaddwod.q.du.d(xrD, xrJ, xrK); +} + +define pcodeop xvdiv.b; + +#lasx.txt xvdiv.b mask=0x74e00000 +#0x74e00000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvdiv.b xrD, xrJ, xrK is op15_31=0xe9c0 & xrD & xrJ & xrK { + xrD = xvdiv.b(xrD, xrJ, xrK); +} + +define pcodeop xvdiv.h; + +#lasx.txt xvdiv.h mask=0x74e08000 +#0x74e08000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvdiv.h xrD, xrJ, xrK is op15_31=0xe9c1 & xrD & xrJ & xrK { + xrD = xvdiv.h(xrD, xrJ, xrK); +} + +define pcodeop xvdiv.w; + +#lasx.txt xvdiv.w mask=0x74e10000 +#0x74e10000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvdiv.w xrD, xrJ, xrK is op15_31=0xe9c2 & xrD & xrJ & xrK { + xrD = xvdiv.w(xrD, xrJ, xrK); +} + +define pcodeop xvdiv.d; + +#lasx.txt xvdiv.d mask=0x74e18000 +#0x74e18000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvdiv.d xrD, xrJ, xrK is op15_31=0xe9c3 & xrD & xrJ & xrK { + xrD = xvdiv.d(xrD, xrJ, xrK); +} + +define pcodeop xvmod.b; + +#lasx.txt xvmod.b mask=0x74e20000 +#0x74e20000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmod.b xrD, xrJ, xrK is op15_31=0xe9c4 & xrD & xrJ & xrK { + xrD = xvmod.b(xrD, xrJ, xrK); +} + +define pcodeop xvmod.h; + +#lasx.txt xvmod.h mask=0x74e28000 +#0x74e28000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmod.h xrD, xrJ, xrK is op15_31=0xe9c5 & xrD & xrJ & xrK { + xrD = xvmod.h(xrD, xrJ, xrK); +} + +define pcodeop xvmod.w; + +#lasx.txt xvmod.w mask=0x74e30000 +#0x74e30000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmod.w xrD, xrJ, xrK is op15_31=0xe9c6 & xrD & xrJ & xrK { + xrD = xvmod.w(xrD, xrJ, xrK); +} + +define pcodeop xvmod.d; + +#lasx.txt xvmod.d mask=0x74e38000 +#0x74e38000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmod.d xrD, xrJ, xrK is op15_31=0xe9c7 & xrD & xrJ & xrK { + xrD = xvmod.d(xrD, xrJ, xrK); +} + +define pcodeop xvdiv.bu; + +#lasx.txt xvdiv.bu mask=0x74e40000 +#0x74e40000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvdiv.bu xrD, xrJ, xrK is op15_31=0xe9c8 & xrD & xrJ & xrK { + xrD = xvdiv.bu(xrD, xrJ, xrK); +} + +define pcodeop xvdiv.hu; + +#lasx.txt xvdiv.hu mask=0x74e48000 +#0x74e48000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvdiv.hu xrD, xrJ, xrK is op15_31=0xe9c9 & xrD & xrJ & xrK { + xrD = xvdiv.hu(xrD, xrJ, xrK); +} + +define pcodeop xvdiv.wu; + +#lasx.txt xvdiv.wu mask=0x74e50000 +#0x74e50000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvdiv.wu xrD, xrJ, xrK is op15_31=0xe9ca & xrD & xrJ & xrK { + xrD = xvdiv.wu(xrD, xrJ, xrK); +} + +define pcodeop xvdiv.du; + +#lasx.txt xvdiv.du mask=0x74e58000 +#0x74e58000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvdiv.du xrD, xrJ, xrK is op15_31=0xe9cb & xrD & xrJ & xrK { + xrD = xvdiv.du(xrD, xrJ, xrK); +} + +define pcodeop xvmod.bu; + +#lasx.txt xvmod.bu mask=0x74e60000 +#0x74e60000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmod.bu xrD, xrJ, xrK is op15_31=0xe9cc & xrD & xrJ & xrK { + xrD = xvmod.bu(xrD, xrJ, xrK); +} + +define pcodeop xvmod.hu; + +#lasx.txt xvmod.hu mask=0x74e68000 +#0x74e68000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmod.hu xrD, xrJ, xrK is op15_31=0xe9cd & xrD & xrJ & xrK { + xrD = xvmod.hu(xrD, xrJ, xrK); +} + +define pcodeop xvmod.wu; + +#lasx.txt xvmod.wu mask=0x74e70000 +#0x74e70000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmod.wu xrD, xrJ, xrK is op15_31=0xe9ce & xrD & xrJ & xrK { + xrD = xvmod.wu(xrD, xrJ, xrK); +} + +define pcodeop xvmod.du; + +#lasx.txt xvmod.du mask=0x74e78000 +#0x74e78000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvmod.du xrD, xrJ, xrK is op15_31=0xe9cf & xrD & xrJ & xrK { + xrD = xvmod.du(xrD, xrJ, xrK); +} + +define pcodeop xvsll.b; + +#lasx.txt xvsll.b mask=0x74e80000 +#0x74e80000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsll.b xrD, xrJ, xrK is op15_31=0xe9d0 & xrD & xrJ & xrK { + xrD = xvsll.b(xrD, xrJ, xrK); +} + +define pcodeop xvsll.h; + +#lasx.txt xvsll.h mask=0x74e88000 +#0x74e88000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsll.h xrD, xrJ, xrK is op15_31=0xe9d1 & xrD & xrJ & xrK { + xrD = xvsll.h(xrD, xrJ, xrK); +} + +define pcodeop xvsll.w; + +#lasx.txt xvsll.w mask=0x74e90000 +#0x74e90000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsll.w xrD, xrJ, xrK is op15_31=0xe9d2 & xrD & xrJ & xrK { + xrD = xvsll.w(xrD, xrJ, xrK); +} + +define pcodeop xvsll.d; + +#lasx.txt xvsll.d mask=0x74e98000 +#0x74e98000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsll.d xrD, xrJ, xrK is op15_31=0xe9d3 & xrD & xrJ & xrK { + xrD = xvsll.d(xrD, xrJ, xrK); +} + +define pcodeop xvsrl.b; + +#lasx.txt xvsrl.b mask=0x74ea0000 +#0x74ea0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrl.b xrD, xrJ, xrK is op15_31=0xe9d4 & xrD & xrJ & xrK { + xrD = xvsrl.b(xrD, xrJ, xrK); +} + +define pcodeop xvsrl.h; + +#lasx.txt xvsrl.h mask=0x74ea8000 +#0x74ea8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrl.h xrD, xrJ, xrK is op15_31=0xe9d5 & xrD & xrJ & xrK { + xrD = xvsrl.h(xrD, xrJ, xrK); +} + +define pcodeop xvsrl.w; + +#lasx.txt xvsrl.w mask=0x74eb0000 +#0x74eb0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrl.w xrD, xrJ, xrK is op15_31=0xe9d6 & xrD & xrJ & xrK { + xrD = xvsrl.w(xrD, xrJ, xrK); +} + +define pcodeop xvsrl.d; + +#lasx.txt xvsrl.d mask=0x74eb8000 +#0x74eb8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrl.d xrD, xrJ, xrK is op15_31=0xe9d7 & xrD & xrJ & xrK { + xrD = xvsrl.d(xrD, xrJ, xrK); +} + +define pcodeop xvsra.b; + +#lasx.txt xvsra.b mask=0x74ec0000 +#0x74ec0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsra.b xrD, xrJ, xrK is op15_31=0xe9d8 & xrD & xrJ & xrK { + xrD = xvsra.b(xrD, xrJ, xrK); +} + +define pcodeop xvsra.h; + +#lasx.txt xvsra.h mask=0x74ec8000 +#0x74ec8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsra.h xrD, xrJ, xrK is op15_31=0xe9d9 & xrD & xrJ & xrK { + xrD = xvsra.h(xrD, xrJ, xrK); +} + +define pcodeop xvsra.w; + +#lasx.txt xvsra.w mask=0x74ed0000 +#0x74ed0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsra.w xrD, xrJ, xrK is op15_31=0xe9da & xrD & xrJ & xrK { + xrD = xvsra.w(xrD, xrJ, xrK); +} + +define pcodeop xvsra.d; + +#lasx.txt xvsra.d mask=0x74ed8000 +#0x74ed8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsra.d xrD, xrJ, xrK is op15_31=0xe9db & xrD & xrJ & xrK { + xrD = xvsra.d(xrD, xrJ, xrK); +} + +define pcodeop xvrotr.b; + +#lasx.txt xvrotr.b mask=0x74ee0000 +#0x74ee0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvrotr.b xrD, xrJ, xrK is op15_31=0xe9dc & xrD & xrJ & xrK { + xrD = xvrotr.b(xrD, xrJ, xrK); +} + +define pcodeop xvrotr.h; + +#lasx.txt xvrotr.h mask=0x74ee8000 +#0x74ee8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvrotr.h xrD, xrJ, xrK is op15_31=0xe9dd & xrD & xrJ & xrK { + xrD = xvrotr.h(xrD, xrJ, xrK); +} + +define pcodeop xvrotr.w; + +#lasx.txt xvrotr.w mask=0x74ef0000 +#0x74ef0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvrotr.w xrD, xrJ, xrK is op15_31=0xe9de & xrD & xrJ & xrK { + xrD = xvrotr.w(xrD, xrJ, xrK); +} + +define pcodeop xvrotr.d; + +#lasx.txt xvrotr.d mask=0x74ef8000 +#0x74ef8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvrotr.d xrD, xrJ, xrK is op15_31=0xe9df & xrD & xrJ & xrK { + xrD = xvrotr.d(xrD, xrJ, xrK); +} + +define pcodeop xvsrlr.b; + +#lasx.txt xvsrlr.b mask=0x74f00000 +#0x74f00000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrlr.b xrD, xrJ, xrK is op15_31=0xe9e0 & xrD & xrJ & xrK { + xrD = xvsrlr.b(xrD, xrJ, xrK); +} + +define pcodeop xvsrlr.h; + +#lasx.txt xvsrlr.h mask=0x74f08000 +#0x74f08000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrlr.h xrD, xrJ, xrK is op15_31=0xe9e1 & xrD & xrJ & xrK { + xrD = xvsrlr.h(xrD, xrJ, xrK); +} + +define pcodeop xvsrlr.w; + +#lasx.txt xvsrlr.w mask=0x74f10000 +#0x74f10000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrlr.w xrD, xrJ, xrK is op15_31=0xe9e2 & xrD & xrJ & xrK { + xrD = xvsrlr.w(xrD, xrJ, xrK); +} + +define pcodeop xvsrlr.d; + +#lasx.txt xvsrlr.d mask=0x74f18000 +#0x74f18000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrlr.d xrD, xrJ, xrK is op15_31=0xe9e3 & xrD & xrJ & xrK { + xrD = xvsrlr.d(xrD, xrJ, xrK); +} + +define pcodeop xvsrar.b; + +#lasx.txt xvsrar.b mask=0x74f20000 +#0x74f20000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrar.b xrD, xrJ, xrK is op15_31=0xe9e4 & xrD & xrJ & xrK { + xrD = xvsrar.b(xrD, xrJ, xrK); +} + +define pcodeop xvsrar.h; + +#lasx.txt xvsrar.h mask=0x74f28000 +#0x74f28000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrar.h xrD, xrJ, xrK is op15_31=0xe9e5 & xrD & xrJ & xrK { + xrD = xvsrar.h(xrD, xrJ, xrK); +} + +define pcodeop xvsrar.w; + +#lasx.txt xvsrar.w mask=0x74f30000 +#0x74f30000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrar.w xrD, xrJ, xrK is op15_31=0xe9e6 & xrD & xrJ & xrK { + xrD = xvsrar.w(xrD, xrJ, xrK); +} + +define pcodeop xvsrar.d; + +#lasx.txt xvsrar.d mask=0x74f38000 +#0x74f38000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrar.d xrD, xrJ, xrK is op15_31=0xe9e7 & xrD & xrJ & xrK { + xrD = xvsrar.d(xrD, xrJ, xrK); +} + +define pcodeop xvsrln.b.h; + +#lasx.txt xvsrln.b.h mask=0x74f48000 +#0x74f48000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrln.b.h xrD, xrJ, xrK is op15_31=0xe9e9 & xrD & xrJ & xrK { + xrD = xvsrln.b.h(xrD, xrJ, xrK); +} + +define pcodeop xvsrln.h.w; + +#lasx.txt xvsrln.h.w mask=0x74f50000 +#0x74f50000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrln.h.w xrD, xrJ, xrK is op15_31=0xe9ea & xrD & xrJ & xrK { + xrD = xvsrln.h.w(xrD, xrJ, xrK); +} + +define pcodeop xvsrln.w.d; + +#lasx.txt xvsrln.w.d mask=0x74f58000 +#0x74f58000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrln.w.d xrD, xrJ, xrK is op15_31=0xe9eb & xrD & xrJ & xrK { + xrD = xvsrln.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvsran.b.h; + +#lasx.txt xvsran.b.h mask=0x74f68000 +#0x74f68000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsran.b.h xrD, xrJ, xrK is op15_31=0xe9ed & xrD & xrJ & xrK { + xrD = xvsran.b.h(xrD, xrJ, xrK); +} + +define pcodeop xvsran.h.w; + +#lasx.txt xvsran.h.w mask=0x74f70000 +#0x74f70000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsran.h.w xrD, xrJ, xrK is op15_31=0xe9ee & xrD & xrJ & xrK { + xrD = xvsran.h.w(xrD, xrJ, xrK); +} + +define pcodeop xvsran.w.d; + +#lasx.txt xvsran.w.d mask=0x74f78000 +#0x74f78000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsran.w.d xrD, xrJ, xrK is op15_31=0xe9ef & xrD & xrJ & xrK { + xrD = xvsran.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvsrlrn.b.h; + +#lasx.txt xvsrlrn.b.h mask=0x74f88000 +#0x74f88000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrlrn.b.h xrD, xrJ, xrK is op15_31=0xe9f1 & xrD & xrJ & xrK { + xrD = xvsrlrn.b.h(xrD, xrJ, xrK); +} + +define pcodeop xvsrlrn.h.w; + +#lasx.txt xvsrlrn.h.w mask=0x74f90000 +#0x74f90000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrlrn.h.w xrD, xrJ, xrK is op15_31=0xe9f2 & xrD & xrJ & xrK { + xrD = xvsrlrn.h.w(xrD, xrJ, xrK); +} + +define pcodeop xvsrlrn.w.d; + +#lasx.txt xvsrlrn.w.d mask=0x74f98000 +#0x74f98000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrlrn.w.d xrD, xrJ, xrK is op15_31=0xe9f3 & xrD & xrJ & xrK { + xrD = xvsrlrn.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvsrarn.b.h; + +#lasx.txt xvsrarn.b.h mask=0x74fa8000 +#0x74fa8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrarn.b.h xrD, xrJ, xrK is op15_31=0xe9f5 & xrD & xrJ & xrK { + xrD = xvsrarn.b.h(xrD, xrJ, xrK); +} + +define pcodeop xvsrarn.h.w; + +#lasx.txt xvsrarn.h.w mask=0x74fb0000 +#0x74fb0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrarn.h.w xrD, xrJ, xrK is op15_31=0xe9f6 & xrD & xrJ & xrK { + xrD = xvsrarn.h.w(xrD, xrJ, xrK); +} + +define pcodeop xvsrarn.w.d; + +#lasx.txt xvsrarn.w.d mask=0x74fb8000 +#0x74fb8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsrarn.w.d xrD, xrJ, xrK is op15_31=0xe9f7 & xrD & xrJ & xrK { + xrD = xvsrarn.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvssrln.b.h; + +#lasx.txt xvssrln.b.h mask=0x74fc8000 +#0x74fc8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrln.b.h xrD, xrJ, xrK is op15_31=0xe9f9 & xrD & xrJ & xrK { + xrD = xvssrln.b.h(xrD, xrJ, xrK); +} + +define pcodeop xvssrln.h.w; + +#lasx.txt xvssrln.h.w mask=0x74fd0000 +#0x74fd0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrln.h.w xrD, xrJ, xrK is op15_31=0xe9fa & xrD & xrJ & xrK { + xrD = xvssrln.h.w(xrD, xrJ, xrK); +} + +define pcodeop xvssrln.w.d; + +#lasx.txt xvssrln.w.d mask=0x74fd8000 +#0x74fd8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrln.w.d xrD, xrJ, xrK is op15_31=0xe9fb & xrD & xrJ & xrK { + xrD = xvssrln.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvssran.b.h; + +#lasx.txt xvssran.b.h mask=0x74fe8000 +#0x74fe8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssran.b.h xrD, xrJ, xrK is op15_31=0xe9fd & xrD & xrJ & xrK { + xrD = xvssran.b.h(xrD, xrJ, xrK); +} + +define pcodeop xvssran.h.w; + +#lasx.txt xvssran.h.w mask=0x74ff0000 +#0x74ff0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssran.h.w xrD, xrJ, xrK is op15_31=0xe9fe & xrD & xrJ & xrK { + xrD = xvssran.h.w(xrD, xrJ, xrK); +} + +define pcodeop xvssran.w.d; + +#lasx.txt xvssran.w.d mask=0x74ff8000 +#0x74ff8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssran.w.d xrD, xrJ, xrK is op15_31=0xe9ff & xrD & xrJ & xrK { + xrD = xvssran.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvssrlrn.b.h; + +#lasx.txt xvssrlrn.b.h mask=0x75008000 +#0x75008000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrlrn.b.h xrD, xrJ, xrK is op15_31=0xea01 & xrD & xrJ & xrK { + xrD = xvssrlrn.b.h(xrD, xrJ, xrK); +} + +define pcodeop xvssrlrn.h.w; + +#lasx.txt xvssrlrn.h.w mask=0x75010000 +#0x75010000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrlrn.h.w xrD, xrJ, xrK is op15_31=0xea02 & xrD & xrJ & xrK { + xrD = xvssrlrn.h.w(xrD, xrJ, xrK); +} + +define pcodeop xvssrlrn.w.d; + +#lasx.txt xvssrlrn.w.d mask=0x75018000 +#0x75018000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrlrn.w.d xrD, xrJ, xrK is op15_31=0xea03 & xrD & xrJ & xrK { + xrD = xvssrlrn.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvssrarn.b.h; + +#lasx.txt xvssrarn.b.h mask=0x75028000 +#0x75028000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrarn.b.h xrD, xrJ, xrK is op15_31=0xea05 & xrD & xrJ & xrK { + xrD = xvssrarn.b.h(xrD, xrJ, xrK); +} + +define pcodeop xvssrarn.h.w; + +#lasx.txt xvssrarn.h.w mask=0x75030000 +#0x75030000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrarn.h.w xrD, xrJ, xrK is op15_31=0xea06 & xrD & xrJ & xrK { + xrD = xvssrarn.h.w(xrD, xrJ, xrK); +} + +define pcodeop xvssrarn.w.d; + +#lasx.txt xvssrarn.w.d mask=0x75038000 +#0x75038000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrarn.w.d xrD, xrJ, xrK is op15_31=0xea07 & xrD & xrJ & xrK { + xrD = xvssrarn.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvssrln.bu.h; + +#lasx.txt xvssrln.bu.h mask=0x75048000 +#0x75048000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrln.bu.h xrD, xrJ, xrK is op15_31=0xea09 & xrD & xrJ & xrK { + xrD = xvssrln.bu.h(xrD, xrJ, xrK); +} + +define pcodeop xvssrln.hu.w; + +#lasx.txt xvssrln.hu.w mask=0x75050000 +#0x75050000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrln.hu.w xrD, xrJ, xrK is op15_31=0xea0a & xrD & xrJ & xrK { + xrD = xvssrln.hu.w(xrD, xrJ, xrK); +} + +define pcodeop xvssrln.wu.d; + +#lasx.txt xvssrln.wu.d mask=0x75058000 +#0x75058000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrln.wu.d xrD, xrJ, xrK is op15_31=0xea0b & xrD & xrJ & xrK { + xrD = xvssrln.wu.d(xrD, xrJ, xrK); +} + +define pcodeop xvssran.bu.h; + +#lasx.txt xvssran.bu.h mask=0x75068000 +#0x75068000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssran.bu.h xrD, xrJ, xrK is op15_31=0xea0d & xrD & xrJ & xrK { + xrD = xvssran.bu.h(xrD, xrJ, xrK); +} + +define pcodeop xvssran.hu.w; + +#lasx.txt xvssran.hu.w mask=0x75070000 +#0x75070000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssran.hu.w xrD, xrJ, xrK is op15_31=0xea0e & xrD & xrJ & xrK { + xrD = xvssran.hu.w(xrD, xrJ, xrK); +} + +define pcodeop xvssran.wu.d; + +#lasx.txt xvssran.wu.d mask=0x75078000 +#0x75078000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssran.wu.d xrD, xrJ, xrK is op15_31=0xea0f & xrD & xrJ & xrK { + xrD = xvssran.wu.d(xrD, xrJ, xrK); +} + +define pcodeop xvssrlrn.bu.h; + +#lasx.txt xvssrlrn.bu.h mask=0x75088000 +#0x75088000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrlrn.bu.h xrD, xrJ, xrK is op15_31=0xea11 & xrD & xrJ & xrK { + xrD = xvssrlrn.bu.h(xrD, xrJ, xrK); +} + +define pcodeop xvssrlrn.hu.w; + +#lasx.txt xvssrlrn.hu.w mask=0x75090000 +#0x75090000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrlrn.hu.w xrD, xrJ, xrK is op15_31=0xea12 & xrD & xrJ & xrK { + xrD = xvssrlrn.hu.w(xrD, xrJ, xrK); +} + +define pcodeop xvssrlrn.wu.d; + +#lasx.txt xvssrlrn.wu.d mask=0x75098000 +#0x75098000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrlrn.wu.d xrD, xrJ, xrK is op15_31=0xea13 & xrD & xrJ & xrK { + xrD = xvssrlrn.wu.d(xrD, xrJ, xrK); +} + +define pcodeop xvssrarn.bu.h; + +#lasx.txt xvssrarn.bu.h mask=0x750a8000 +#0x750a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrarn.bu.h xrD, xrJ, xrK is op15_31=0xea15 & xrD & xrJ & xrK { + xrD = xvssrarn.bu.h(xrD, xrJ, xrK); +} + +define pcodeop xvssrarn.hu.w; + +#lasx.txt xvssrarn.hu.w mask=0x750b0000 +#0x750b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrarn.hu.w xrD, xrJ, xrK is op15_31=0xea16 & xrD & xrJ & xrK { + xrD = xvssrarn.hu.w(xrD, xrJ, xrK); +} + +define pcodeop xvssrarn.wu.d; + +#lasx.txt xvssrarn.wu.d mask=0x750b8000 +#0x750b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvssrarn.wu.d xrD, xrJ, xrK is op15_31=0xea17 & xrD & xrJ & xrK { + xrD = xvssrarn.wu.d(xrD, xrJ, xrK); +} + +define pcodeop xvbitclr.b; + +#lasx.txt xvbitclr.b mask=0x750c0000 +#0x750c0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitclr.b xrD, xrJ, xrK is op15_31=0xea18 & xrD & xrJ & xrK { + xrD = xvbitclr.b(xrD, xrJ, xrK); +} + +define pcodeop xvbitclr.h; + +#lasx.txt xvbitclr.h mask=0x750c8000 +#0x750c8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitclr.h xrD, xrJ, xrK is op15_31=0xea19 & xrD & xrJ & xrK { + xrD = xvbitclr.h(xrD, xrJ, xrK); +} + +define pcodeop xvbitclr.w; + +#lasx.txt xvbitclr.w mask=0x750d0000 +#0x750d0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitclr.w xrD, xrJ, xrK is op15_31=0xea1a & xrD & xrJ & xrK { + xrD = xvbitclr.w(xrD, xrJ, xrK); +} + +define pcodeop xvbitclr.d; + +#lasx.txt xvbitclr.d mask=0x750d8000 +#0x750d8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitclr.d xrD, xrJ, xrK is op15_31=0xea1b & xrD & xrJ & xrK { + xrD = xvbitclr.d(xrD, xrJ, xrK); +} + +define pcodeop xvbitset.b; + +#lasx.txt xvbitset.b mask=0x750e0000 +#0x750e0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitset.b xrD, xrJ, xrK is op15_31=0xea1c & xrD & xrJ & xrK { + xrD = xvbitset.b(xrD, xrJ, xrK); +} + +define pcodeop xvbitset.h; + +#lasx.txt xvbitset.h mask=0x750e8000 +#0x750e8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitset.h xrD, xrJ, xrK is op15_31=0xea1d & xrD & xrJ & xrK { + xrD = xvbitset.h(xrD, xrJ, xrK); +} + +define pcodeop xvbitset.w; + +#lasx.txt xvbitset.w mask=0x750f0000 +#0x750f0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitset.w xrD, xrJ, xrK is op15_31=0xea1e & xrD & xrJ & xrK { + xrD = xvbitset.w(xrD, xrJ, xrK); +} + +define pcodeop xvbitset.d; + +#lasx.txt xvbitset.d mask=0x750f8000 +#0x750f8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitset.d xrD, xrJ, xrK is op15_31=0xea1f & xrD & xrJ & xrK { + xrD = xvbitset.d(xrD, xrJ, xrK); +} + +define pcodeop xvbitrev.b; + +#lasx.txt xvbitrev.b mask=0x75100000 +#0x75100000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitrev.b xrD, xrJ, xrK is op15_31=0xea20 & xrD & xrJ & xrK { + xrD = xvbitrev.b(xrD, xrJ, xrK); +} + +define pcodeop xvbitrev.h; + +#lasx.txt xvbitrev.h mask=0x75108000 +#0x75108000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitrev.h xrD, xrJ, xrK is op15_31=0xea21 & xrD & xrJ & xrK { + xrD = xvbitrev.h(xrD, xrJ, xrK); +} + +define pcodeop xvbitrev.w; + +#lasx.txt xvbitrev.w mask=0x75110000 +#0x75110000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitrev.w xrD, xrJ, xrK is op15_31=0xea22 & xrD & xrJ & xrK { + xrD = xvbitrev.w(xrD, xrJ, xrK); +} + +define pcodeop xvbitrev.d; + +#lasx.txt xvbitrev.d mask=0x75118000 +#0x75118000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvbitrev.d xrD, xrJ, xrK is op15_31=0xea23 & xrD & xrJ & xrK { + xrD = xvbitrev.d(xrD, xrJ, xrK); +} + +define pcodeop xvpackev.b; + +#lasx.txt xvpackev.b mask=0x75160000 +#0x75160000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpackev.b xrD, xrJ, xrK is op15_31=0xea2c & xrD & xrJ & xrK { + xrD = xvpackev.b(xrD, xrJ, xrK); +} + +define pcodeop xvpackev.h; + +#lasx.txt xvpackev.h mask=0x75168000 +#0x75168000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpackev.h xrD, xrJ, xrK is op15_31=0xea2d & xrD & xrJ & xrK { + xrD = xvpackev.h(xrD, xrJ, xrK); +} + +define pcodeop xvpackev.w; + +#lasx.txt xvpackev.w mask=0x75170000 +#0x75170000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpackev.w xrD, xrJ, xrK is op15_31=0xea2e & xrD & xrJ & xrK { + xrD = xvpackev.w(xrD, xrJ, xrK); +} + +define pcodeop xvpackev.d; + +#lasx.txt xvpackev.d mask=0x75178000 +#0x75178000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpackev.d xrD, xrJ, xrK is op15_31=0xea2f & xrD & xrJ & xrK { + xrD = xvpackev.d(xrD, xrJ, xrK); +} + +define pcodeop xvpackod.b; + +#lasx.txt xvpackod.b mask=0x75180000 +#0x75180000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpackod.b xrD, xrJ, xrK is op15_31=0xea30 & xrD & xrJ & xrK { + xrD = xvpackod.b(xrD, xrJ, xrK); +} + +define pcodeop xvpackod.h; + +#lasx.txt xvpackod.h mask=0x75188000 +#0x75188000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpackod.h xrD, xrJ, xrK is op15_31=0xea31 & xrD & xrJ & xrK { + xrD = xvpackod.h(xrD, xrJ, xrK); +} + +define pcodeop xvpackod.w; + +#lasx.txt xvpackod.w mask=0x75190000 +#0x75190000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpackod.w xrD, xrJ, xrK is op15_31=0xea32 & xrD & xrJ & xrK { + xrD = xvpackod.w(xrD, xrJ, xrK); +} + +define pcodeop xvpackod.d; + +#lasx.txt xvpackod.d mask=0x75198000 +#0x75198000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpackod.d xrD, xrJ, xrK is op15_31=0xea33 & xrD & xrJ & xrK { + xrD = xvpackod.d(xrD, xrJ, xrK); +} + +define pcodeop xvilvl.b; + +#lasx.txt xvilvl.b mask=0x751a0000 +#0x751a0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvilvl.b xrD, xrJ, xrK is op15_31=0xea34 & xrD & xrJ & xrK { + xrD = xvilvl.b(xrD, xrJ, xrK); +} + +define pcodeop xvilvl.h; + +#lasx.txt xvilvl.h mask=0x751a8000 +#0x751a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvilvl.h xrD, xrJ, xrK is op15_31=0xea35 & xrD & xrJ & xrK { + xrD = xvilvl.h(xrD, xrJ, xrK); +} + +define pcodeop xvilvl.w; + +#lasx.txt xvilvl.w mask=0x751b0000 +#0x751b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvilvl.w xrD, xrJ, xrK is op15_31=0xea36 & xrD & xrJ & xrK { + xrD = xvilvl.w(xrD, xrJ, xrK); +} + +define pcodeop xvilvl.d; + +#lasx.txt xvilvl.d mask=0x751b8000 +#0x751b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvilvl.d xrD, xrJ, xrK is op15_31=0xea37 & xrD & xrJ & xrK { + xrD = xvilvl.d(xrD, xrJ, xrK); +} + +define pcodeop xvilvh.b; + +#lasx.txt xvilvh.b mask=0x751c0000 +#0x751c0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvilvh.b xrD, xrJ, xrK is op15_31=0xea38 & xrD & xrJ & xrK { + xrD = xvilvh.b(xrD, xrJ, xrK); +} + +define pcodeop xvilvh.h; + +#lasx.txt xvilvh.h mask=0x751c8000 +#0x751c8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvilvh.h xrD, xrJ, xrK is op15_31=0xea39 & xrD & xrJ & xrK { + xrD = xvilvh.h(xrD, xrJ, xrK); +} + +define pcodeop xvilvh.w; + +#lasx.txt xvilvh.w mask=0x751d0000 +#0x751d0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvilvh.w xrD, xrJ, xrK is op15_31=0xea3a & xrD & xrJ & xrK { + xrD = xvilvh.w(xrD, xrJ, xrK); +} + +define pcodeop xvilvh.d; + +#lasx.txt xvilvh.d mask=0x751d8000 +#0x751d8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvilvh.d xrD, xrJ, xrK is op15_31=0xea3b & xrD & xrJ & xrK { + xrD = xvilvh.d(xrD, xrJ, xrK); +} + +define pcodeop xvpickev.b; + +#lasx.txt xvpickev.b mask=0x751e0000 +#0x751e0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpickev.b xrD, xrJ, xrK is op15_31=0xea3c & xrD & xrJ & xrK { + xrD = xvpickev.b(xrD, xrJ, xrK); +} + +define pcodeop xvpickev.h; + +#lasx.txt xvpickev.h mask=0x751e8000 +#0x751e8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpickev.h xrD, xrJ, xrK is op15_31=0xea3d & xrD & xrJ & xrK { + xrD = xvpickev.h(xrD, xrJ, xrK); +} + +define pcodeop xvpickev.w; + +#lasx.txt xvpickev.w mask=0x751f0000 +#0x751f0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpickev.w xrD, xrJ, xrK is op15_31=0xea3e & xrD & xrJ & xrK { + xrD = xvpickev.w(xrD, xrJ, xrK); +} + +define pcodeop xvpickev.d; + +#lasx.txt xvpickev.d mask=0x751f8000 +#0x751f8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpickev.d xrD, xrJ, xrK is op15_31=0xea3f & xrD & xrJ & xrK { + xrD = xvpickev.d(xrD, xrJ, xrK); +} + +define pcodeop xvpickod.b; + +#lasx.txt xvpickod.b mask=0x75200000 +#0x75200000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpickod.b xrD, xrJ, xrK is op15_31=0xea40 & xrD & xrJ & xrK { + xrD = xvpickod.b(xrD, xrJ, xrK); +} + +define pcodeop xvpickod.h; + +#lasx.txt xvpickod.h mask=0x75208000 +#0x75208000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpickod.h xrD, xrJ, xrK is op15_31=0xea41 & xrD & xrJ & xrK { + xrD = xvpickod.h(xrD, xrJ, xrK); +} + +define pcodeop xvpickod.w; + +#lasx.txt xvpickod.w mask=0x75210000 +#0x75210000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpickod.w xrD, xrJ, xrK is op15_31=0xea42 & xrD & xrJ & xrK { + xrD = xvpickod.w(xrD, xrJ, xrK); +} + +define pcodeop xvpickod.d; + +#lasx.txt xvpickod.d mask=0x75218000 +#0x75218000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvpickod.d xrD, xrJ, xrK is op15_31=0xea43 & xrD & xrJ & xrK { + xrD = xvpickod.d(xrD, xrJ, xrK); +} + +define pcodeop xvreplve.b; + +#lasx.txt xvreplve.b mask=0x75220000 +#0x75220000 0xffff8000 x0:5,x5:5, r10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'reg10_5_s0'] +:xvreplve.b xrD, xrJ, RKsrc is op15_31=0xea44 & xrD & xrJ & RKsrc { + xrD = xvreplve.b(xrD, xrJ, RKsrc); +} + +define pcodeop xvreplve.h; + +#lasx.txt xvreplve.h mask=0x75228000 +#0x75228000 0xffff8000 x0:5,x5:5, r10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'reg10_5_s0'] +:xvreplve.h xrD, xrJ, RKsrc is op15_31=0xea45 & xrD & xrJ & RKsrc { + xrD = xvreplve.h(xrD, xrJ, RKsrc); +} + +define pcodeop xvreplve.w; + +#lasx.txt xvreplve.w mask=0x75230000 +#0x75230000 0xffff8000 x0:5,x5:5, r10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'reg10_5_s0'] +:xvreplve.w xrD, xrJ, RKsrc is op15_31=0xea46 & xrD & xrJ & RKsrc { + xrD = xvreplve.w(xrD, xrJ, RKsrc); +} + +define pcodeop xvreplve.d; + +#lasx.txt xvreplve.d mask=0x75238000 +#0x75238000 0xffff8000 x0:5,x5:5, r10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'reg10_5_s0'] +:xvreplve.d xrD, xrJ, RKsrc is op15_31=0xea47 & xrD & xrJ & RKsrc { + xrD = xvreplve.d(xrD, xrJ, RKsrc); +} + +define pcodeop xvand.v; + +#lasx.txt xvand.v mask=0x75260000 +#0x75260000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvand.v xrD, xrJ, xrK is op15_31=0xea4c & xrD & xrJ & xrK { + xrD = xvand.v(xrD, xrJ, xrK); +} + +define pcodeop xvor.v; + +#lasx.txt xvor.v mask=0x75268000 +#0x75268000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvor.v xrD, xrJ, xrK is op15_31=0xea4d & xrD & xrJ & xrK { + xrD = xvor.v(xrD, xrJ, xrK); +} + +define pcodeop xvxor.v; + +#lasx.txt xvxor.v mask=0x75270000 +#0x75270000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvxor.v xrD, xrJ, xrK is op15_31=0xea4e & xrD & xrJ & xrK { + xrD = xvxor.v(xrD, xrJ, xrK); +} + +define pcodeop xvnor.v; + +#lasx.txt xvnor.v mask=0x75278000 +#0x75278000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvnor.v xrD, xrJ, xrK is op15_31=0xea4f & xrD & xrJ & xrK { + xrD = xvnor.v(xrD, xrJ, xrK); +} + +define pcodeop xvandn.v; + +#lasx.txt xvandn.v mask=0x75280000 +#0x75280000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvandn.v xrD, xrJ, xrK is op15_31=0xea50 & xrD & xrJ & xrK { + xrD = xvandn.v(xrD, xrJ, xrK); +} + +define pcodeop xvorn.v; + +#lasx.txt xvorn.v mask=0x75288000 +#0x75288000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvorn.v xrD, xrJ, xrK is op15_31=0xea51 & xrD & xrJ & xrK { + xrD = xvorn.v(xrD, xrJ, xrK); +} + +define pcodeop xvfrstp.b; + +#lasx.txt xvfrstp.b mask=0x752b0000 +#0x752b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfrstp.b xrD, xrJ, xrK is op15_31=0xea56 & xrD & xrJ & xrK { + xrD = xvfrstp.b(xrD, xrJ, xrK); +} + +define pcodeop xvfrstp.h; + +#lasx.txt xvfrstp.h mask=0x752b8000 +#0x752b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfrstp.h xrD, xrJ, xrK is op15_31=0xea57 & xrD & xrJ & xrK { + xrD = xvfrstp.h(xrD, xrJ, xrK); +} + +define pcodeop xvadd.q; + +#lasx.txt xvadd.q mask=0x752d0000 +#0x752d0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvadd.q xrD, xrJ, xrK is op15_31=0xea5a & xrD & xrJ & xrK { + xrD = xvadd.q(xrD, xrJ, xrK); +} + +define pcodeop xvsub.q; + +#lasx.txt xvsub.q mask=0x752d8000 +#0x752d8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsub.q xrD, xrJ, xrK is op15_31=0xea5b & xrD & xrJ & xrK { + xrD = xvsub.q(xrD, xrJ, xrK); +} + +define pcodeop xvsigncov.b; + +#lasx.txt xvsigncov.b mask=0x752e0000 +#0x752e0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsigncov.b xrD, xrJ, xrK is op15_31=0xea5c & xrD & xrJ & xrK { + xrD = xvsigncov.b(xrD, xrJ, xrK); +} + +define pcodeop xvsigncov.h; + +#lasx.txt xvsigncov.h mask=0x752e8000 +#0x752e8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsigncov.h xrD, xrJ, xrK is op15_31=0xea5d & xrD & xrJ & xrK { + xrD = xvsigncov.h(xrD, xrJ, xrK); +} + +define pcodeop xvsigncov.w; + +#lasx.txt xvsigncov.w mask=0x752f0000 +#0x752f0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsigncov.w xrD, xrJ, xrK is op15_31=0xea5e & xrD & xrJ & xrK { + xrD = xvsigncov.w(xrD, xrJ, xrK); +} + +define pcodeop xvsigncov.d; + +#lasx.txt xvsigncov.d mask=0x752f8000 +#0x752f8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvsigncov.d xrD, xrJ, xrK is op15_31=0xea5f & xrD & xrJ & xrK { + xrD = xvsigncov.d(xrD, xrJ, xrK); +} + +define pcodeop xvfadd.s; + +#lasx.txt xvfadd.s mask=0x75308000 +#0x75308000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfadd.s xrD, xrJ, xrK is op15_31=0xea61 & xrD & xrJ & xrK { + xrD = xvfadd.s(xrD, xrJ, xrK); +} + +define pcodeop xvfadd.d; + +#lasx.txt xvfadd.d mask=0x75310000 +#0x75310000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfadd.d xrD, xrJ, xrK is op15_31=0xea62 & xrD & xrJ & xrK { + xrD = xvfadd.d(xrD, xrJ, xrK); +} + +define pcodeop xvfsub.s; + +#lasx.txt xvfsub.s mask=0x75328000 +#0x75328000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfsub.s xrD, xrJ, xrK is op15_31=0xea65 & xrD & xrJ & xrK { + xrD = xvfsub.s(xrD, xrJ, xrK); +} + +define pcodeop xvfsub.d; + +#lasx.txt xvfsub.d mask=0x75330000 +#0x75330000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfsub.d xrD, xrJ, xrK is op15_31=0xea66 & xrD & xrJ & xrK { + xrD = xvfsub.d(xrD, xrJ, xrK); +} + +define pcodeop xvfmul.s; + +#lasx.txt xvfmul.s mask=0x75388000 +#0x75388000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmul.s xrD, xrJ, xrK is op15_31=0xea71 & xrD & xrJ & xrK { + xrD = xvfmul.s(xrD, xrJ, xrK); +} + +define pcodeop xvfmul.d; + +#lasx.txt xvfmul.d mask=0x75390000 +#0x75390000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmul.d xrD, xrJ, xrK is op15_31=0xea72 & xrD & xrJ & xrK { + xrD = xvfmul.d(xrD, xrJ, xrK); +} + +define pcodeop xvfdiv.s; + +#lasx.txt xvfdiv.s mask=0x753a8000 +#0x753a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfdiv.s xrD, xrJ, xrK is op15_31=0xea75 & xrD & xrJ & xrK { + xrD = xvfdiv.s(xrD, xrJ, xrK); +} + +define pcodeop xvfdiv.d; + +#lasx.txt xvfdiv.d mask=0x753b0000 +#0x753b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfdiv.d xrD, xrJ, xrK is op15_31=0xea76 & xrD & xrJ & xrK { + xrD = xvfdiv.d(xrD, xrJ, xrK); +} + +define pcodeop xvfmax.s; + +#lasx.txt xvfmax.s mask=0x753c8000 +#0x753c8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmax.s xrD, xrJ, xrK is op15_31=0xea79 & xrD & xrJ & xrK { + xrD = xvfmax.s(xrD, xrJ, xrK); +} + +define pcodeop xvfmax.d; + +#lasx.txt xvfmax.d mask=0x753d0000 +#0x753d0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmax.d xrD, xrJ, xrK is op15_31=0xea7a & xrD & xrJ & xrK { + xrD = xvfmax.d(xrD, xrJ, xrK); +} + +define pcodeop xvfmin.s; + +#lasx.txt xvfmin.s mask=0x753e8000 +#0x753e8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmin.s xrD, xrJ, xrK is op15_31=0xea7d & xrD & xrJ & xrK { + xrD = xvfmin.s(xrD, xrJ, xrK); +} + +define pcodeop xvfmin.d; + +#lasx.txt xvfmin.d mask=0x753f0000 +#0x753f0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmin.d xrD, xrJ, xrK is op15_31=0xea7e & xrD & xrJ & xrK { + xrD = xvfmin.d(xrD, xrJ, xrK); +} + +define pcodeop xvfmaxa.s; + +#lasx.txt xvfmaxa.s mask=0x75408000 +#0x75408000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmaxa.s xrD, xrJ, xrK is op15_31=0xea81 & xrD & xrJ & xrK { + xrD = xvfmaxa.s(xrD, xrJ, xrK); +} + +define pcodeop xvfmaxa.d; + +#lasx.txt xvfmaxa.d mask=0x75410000 +#0x75410000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmaxa.d xrD, xrJ, xrK is op15_31=0xea82 & xrD & xrJ & xrK { + xrD = xvfmaxa.d(xrD, xrJ, xrK); +} + +define pcodeop xvfmina.s; + +#lasx.txt xvfmina.s mask=0x75428000 +#0x75428000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmina.s xrD, xrJ, xrK is op15_31=0xea85 & xrD & xrJ & xrK { + xrD = xvfmina.s(xrD, xrJ, xrK); +} + +define pcodeop xvfmina.d; + +#lasx.txt xvfmina.d mask=0x75430000 +#0x75430000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfmina.d xrD, xrJ, xrK is op15_31=0xea86 & xrD & xrJ & xrK { + xrD = xvfmina.d(xrD, xrJ, xrK); +} + +define pcodeop xvfcvt.h.s; + +#lasx.txt xvfcvt.h.s mask=0x75460000 +#0x75460000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcvt.h.s xrD, xrJ, xrK is op15_31=0xea8c & xrD & xrJ & xrK { + xrD = xvfcvt.h.s(xrD, xrJ, xrK); +} + +define pcodeop xvfcvt.s.d; + +#lasx.txt xvfcvt.s.d mask=0x75468000 +#0x75468000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvfcvt.s.d xrD, xrJ, xrK is op15_31=0xea8d & xrD & xrJ & xrK { + xrD = xvfcvt.s.d(xrD, xrJ, xrK); +} + +define pcodeop xvffint.s.l; + +#lasx.txt xvffint.s.l mask=0x75480000 +#0x75480000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvffint.s.l xrD, xrJ, xrK is op15_31=0xea90 & xrD & xrJ & xrK { + xrD = xvffint.s.l(xrD, xrJ, xrK); +} + +define pcodeop xvftint.w.d; + +#lasx.txt xvftint.w.d mask=0x75498000 +#0x75498000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvftint.w.d xrD, xrJ, xrK is op15_31=0xea93 & xrD & xrJ & xrK { + xrD = xvftint.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvftintrm.w.d; + +#lasx.txt xvftintrm.w.d mask=0x754a0000 +#0x754a0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvftintrm.w.d xrD, xrJ, xrK is op15_31=0xea94 & xrD & xrJ & xrK { + xrD = xvftintrm.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvftintrp.w.d; + +#lasx.txt xvftintrp.w.d mask=0x754a8000 +#0x754a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvftintrp.w.d xrD, xrJ, xrK is op15_31=0xea95 & xrD & xrJ & xrK { + xrD = xvftintrp.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvftintrz.w.d; + +#lasx.txt xvftintrz.w.d mask=0x754b0000 +#0x754b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvftintrz.w.d xrD, xrJ, xrK is op15_31=0xea96 & xrD & xrJ & xrK { + xrD = xvftintrz.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvftintrne.w.d; + +#lasx.txt xvftintrne.w.d mask=0x754b8000 +#0x754b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvftintrne.w.d xrD, xrJ, xrK is op15_31=0xea97 & xrD & xrJ & xrK { + xrD = xvftintrne.w.d(xrD, xrJ, xrK); +} + +define pcodeop xvshuf.h; + +#lasx.txt xvshuf.h mask=0x757a8000 +#0x757a8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvshuf.h xrD, xrJ, xrK is op15_31=0xeaf5 & xrD & xrJ & xrK { + xrD = xvshuf.h(xrD, xrJ, xrK); +} + +define pcodeop xvshuf.w; + +#lasx.txt xvshuf.w mask=0x757b0000 +#0x757b0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvshuf.w xrD, xrJ, xrK is op15_31=0xeaf6 & xrD & xrJ & xrK { + xrD = xvshuf.w(xrD, xrJ, xrK); +} + +define pcodeop xvshuf.d; + +#lasx.txt xvshuf.d mask=0x757b8000 +#0x757b8000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvshuf.d xrD, xrJ, xrK is op15_31=0xeaf7 & xrD & xrJ & xrK { + xrD = xvshuf.d(xrD, xrJ, xrK); +} + +define pcodeop xvperm.w; + +#lasx.txt xvperm.w mask=0x757d0000 +#0x757d0000 0xffff8000 x0:5,x5:5,x10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'xreg10_5_s0'] +:xvperm.w xrD, xrJ, xrK is op15_31=0xeafa & xrD & xrJ & xrK { + xrD = xvperm.w(xrD, xrJ, xrK); +} + +define pcodeop xvseqi.b; + +#lasx.txt xvseqi.b mask=0x76800000 +#0x76800000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvseqi.b xrD, xrJ,simm10_5 is op15_31=0xed00 & xrD & xrJ & simm10_5 { + xrD = xvseqi.b(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvseqi.h; + +#lasx.txt xvseqi.h mask=0x76808000 +#0x76808000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvseqi.h xrD, xrJ,simm10_5 is op15_31=0xed01 & xrD & xrJ & simm10_5 { + xrD = xvseqi.h(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvseqi.w; + +#lasx.txt xvseqi.w mask=0x76810000 +#0x76810000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvseqi.w xrD, xrJ,simm10_5 is op15_31=0xed02 & xrD & xrJ & simm10_5 { + xrD = xvseqi.w(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvseqi.d; + +#lasx.txt xvseqi.d mask=0x76818000 +#0x76818000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvseqi.d xrD, xrJ,simm10_5 is op15_31=0xed03 & xrD & xrJ & simm10_5 { + xrD = xvseqi.d(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslei.b; + +#lasx.txt xvslei.b mask=0x76820000 +#0x76820000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvslei.b xrD, xrJ,simm10_5 is op15_31=0xed04 & xrD & xrJ & simm10_5 { + xrD = xvslei.b(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslei.h; + +#lasx.txt xvslei.h mask=0x76828000 +#0x76828000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvslei.h xrD, xrJ,simm10_5 is op15_31=0xed05 & xrD & xrJ & simm10_5 { + xrD = xvslei.h(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslei.w; + +#lasx.txt xvslei.w mask=0x76830000 +#0x76830000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvslei.w xrD, xrJ,simm10_5 is op15_31=0xed06 & xrD & xrJ & simm10_5 { + xrD = xvslei.w(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslei.d; + +#lasx.txt xvslei.d mask=0x76838000 +#0x76838000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvslei.d xrD, xrJ,simm10_5 is op15_31=0xed07 & xrD & xrJ & simm10_5 { + xrD = xvslei.d(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslei.bu; + +#lasx.txt xvslei.bu mask=0x76840000 +#0x76840000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslei.bu xrD, xrJ, imm10_5 is op15_31=0xed08 & xrD & xrJ & imm10_5 { + xrD = xvslei.bu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvslei.hu; + +#lasx.txt xvslei.hu mask=0x76848000 +#0x76848000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslei.hu xrD, xrJ, imm10_5 is op15_31=0xed09 & xrD & xrJ & imm10_5 { + xrD = xvslei.hu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvslei.wu; + +#lasx.txt xvslei.wu mask=0x76850000 +#0x76850000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslei.wu xrD, xrJ, imm10_5 is op15_31=0xed0a & xrD & xrJ & imm10_5 { + xrD = xvslei.wu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvslei.du; + +#lasx.txt xvslei.du mask=0x76858000 +#0x76858000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslei.du xrD, xrJ, imm10_5 is op15_31=0xed0b & xrD & xrJ & imm10_5 { + xrD = xvslei.du(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvslti.b; + +#lasx.txt xvslti.b mask=0x76860000 +#0x76860000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvslti.b xrD, xrJ,simm10_5 is op15_31=0xed0c & xrD & xrJ & simm10_5 { + xrD = xvslti.b(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslti.h; + +#lasx.txt xvslti.h mask=0x76868000 +#0x76868000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvslti.h xrD, xrJ,simm10_5 is op15_31=0xed0d & xrD & xrJ & simm10_5 { + xrD = xvslti.h(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslti.w; + +#lasx.txt xvslti.w mask=0x76870000 +#0x76870000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvslti.w xrD, xrJ,simm10_5 is op15_31=0xed0e & xrD & xrJ & simm10_5 { + xrD = xvslti.w(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslti.d; + +#lasx.txt xvslti.d mask=0x76878000 +#0x76878000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvslti.d xrD, xrJ,simm10_5 is op15_31=0xed0f & xrD & xrJ & simm10_5 { + xrD = xvslti.d(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvslti.bu; + +#lasx.txt xvslti.bu mask=0x76880000 +#0x76880000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslti.bu xrD, xrJ, imm10_5 is op15_31=0xed10 & xrD & xrJ & imm10_5 { + xrD = xvslti.bu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvslti.hu; + +#lasx.txt xvslti.hu mask=0x76888000 +#0x76888000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslti.hu xrD, xrJ, imm10_5 is op15_31=0xed11 & xrD & xrJ & imm10_5 { + xrD = xvslti.hu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvslti.wu; + +#lasx.txt xvslti.wu mask=0x76890000 +#0x76890000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslti.wu xrD, xrJ, imm10_5 is op15_31=0xed12 & xrD & xrJ & imm10_5 { + xrD = xvslti.wu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvslti.du; + +#lasx.txt xvslti.du mask=0x76898000 +#0x76898000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslti.du xrD, xrJ, imm10_5 is op15_31=0xed13 & xrD & xrJ & imm10_5 { + xrD = xvslti.du(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvaddi.bu; + +#lasx.txt xvaddi.bu mask=0x768a0000 +#0x768a0000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvaddi.bu xrD, xrJ, imm10_5 is op15_31=0xed14 & xrD & xrJ & imm10_5 { + xrD = xvaddi.bu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvaddi.hu; + +#lasx.txt xvaddi.hu mask=0x768a8000 +#0x768a8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvaddi.hu xrD, xrJ, imm10_5 is op15_31=0xed15 & xrD & xrJ & imm10_5 { + xrD = xvaddi.hu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvaddi.wu; + +#lasx.txt xvaddi.wu mask=0x768b0000 +#0x768b0000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvaddi.wu xrD, xrJ, imm10_5 is op15_31=0xed16 & xrD & xrJ & imm10_5 { + xrD = xvaddi.wu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvaddi.du; + +#lasx.txt xvaddi.du mask=0x768b8000 +#0x768b8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvaddi.du xrD, xrJ, imm10_5 is op15_31=0xed17 & xrD & xrJ & imm10_5 { + xrD = xvaddi.du(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsubi.bu; + +#lasx.txt xvsubi.bu mask=0x768c0000 +#0x768c0000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsubi.bu xrD, xrJ, imm10_5 is op15_31=0xed18 & xrD & xrJ & imm10_5 { + xrD = xvsubi.bu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsubi.hu; + +#lasx.txt xvsubi.hu mask=0x768c8000 +#0x768c8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsubi.hu xrD, xrJ, imm10_5 is op15_31=0xed19 & xrD & xrJ & imm10_5 { + xrD = xvsubi.hu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsubi.wu; + +#lasx.txt xvsubi.wu mask=0x768d0000 +#0x768d0000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsubi.wu xrD, xrJ, imm10_5 is op15_31=0xed1a & xrD & xrJ & imm10_5 { + xrD = xvsubi.wu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsubi.du; + +#lasx.txt xvsubi.du mask=0x768d8000 +#0x768d8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsubi.du xrD, xrJ, imm10_5 is op15_31=0xed1b & xrD & xrJ & imm10_5 { + xrD = xvsubi.du(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvbsll.v; + +#lasx.txt xvbsll.v mask=0x768e0000 +#0x768e0000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvbsll.v xrD, xrJ, imm10_5 is op15_31=0xed1c & xrD & xrJ & imm10_5 { + xrD = xvbsll.v(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvbsrl.v; + +#lasx.txt xvbsrl.v mask=0x768e8000 +#0x768e8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvbsrl.v xrD, xrJ, imm10_5 is op15_31=0xed1d & xrD & xrJ & imm10_5 { + xrD = xvbsrl.v(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvmaxi.b; + +#lasx.txt xvmaxi.b mask=0x76900000 +#0x76900000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvmaxi.b xrD, xrJ,simm10_5 is op15_31=0xed20 & xrD & xrJ & simm10_5 { + xrD = xvmaxi.b(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvmaxi.h; + +#lasx.txt xvmaxi.h mask=0x76908000 +#0x76908000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvmaxi.h xrD, xrJ,simm10_5 is op15_31=0xed21 & xrD & xrJ & simm10_5 { + xrD = xvmaxi.h(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvmaxi.w; + +#lasx.txt xvmaxi.w mask=0x76910000 +#0x76910000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvmaxi.w xrD, xrJ,simm10_5 is op15_31=0xed22 & xrD & xrJ & simm10_5 { + xrD = xvmaxi.w(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvmaxi.d; + +#lasx.txt xvmaxi.d mask=0x76918000 +#0x76918000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvmaxi.d xrD, xrJ,simm10_5 is op15_31=0xed23 & xrD & xrJ & simm10_5 { + xrD = xvmaxi.d(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvmini.b; + +#lasx.txt xvmini.b mask=0x76920000 +#0x76920000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvmini.b xrD, xrJ,simm10_5 is op15_31=0xed24 & xrD & xrJ & simm10_5 { + xrD = xvmini.b(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvmini.h; + +#lasx.txt xvmini.h mask=0x76928000 +#0x76928000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvmini.h xrD, xrJ,simm10_5 is op15_31=0xed25 & xrD & xrJ & simm10_5 { + xrD = xvmini.h(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvmini.w; + +#lasx.txt xvmini.w mask=0x76930000 +#0x76930000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvmini.w xrD, xrJ,simm10_5 is op15_31=0xed26 & xrD & xrJ & simm10_5 { + xrD = xvmini.w(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvmini.d; + +#lasx.txt xvmini.d mask=0x76938000 +#0x76938000 0xffff8000 x0:5,x5:5,s10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'simm10_5_s0'] +:xvmini.d xrD, xrJ,simm10_5 is op15_31=0xed27 & xrD & xrJ & simm10_5 { + xrD = xvmini.d(xrD, xrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop xvmaxi.bu; + +#lasx.txt xvmaxi.bu mask=0x76940000 +#0x76940000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvmaxi.bu xrD, xrJ, imm10_5 is op15_31=0xed28 & xrD & xrJ & imm10_5 { + xrD = xvmaxi.bu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvmaxi.hu; + +#lasx.txt xvmaxi.hu mask=0x76948000 +#0x76948000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvmaxi.hu xrD, xrJ, imm10_5 is op15_31=0xed29 & xrD & xrJ & imm10_5 { + xrD = xvmaxi.hu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvmaxi.wu; + +#lasx.txt xvmaxi.wu mask=0x76950000 +#0x76950000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvmaxi.wu xrD, xrJ, imm10_5 is op15_31=0xed2a & xrD & xrJ & imm10_5 { + xrD = xvmaxi.wu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvmaxi.du; + +#lasx.txt xvmaxi.du mask=0x76958000 +#0x76958000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvmaxi.du xrD, xrJ, imm10_5 is op15_31=0xed2b & xrD & xrJ & imm10_5 { + xrD = xvmaxi.du(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvmini.bu; + +#lasx.txt xvmini.bu mask=0x76960000 +#0x76960000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvmini.bu xrD, xrJ, imm10_5 is op15_31=0xed2c & xrD & xrJ & imm10_5 { + xrD = xvmini.bu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvmini.hu; + +#lasx.txt xvmini.hu mask=0x76968000 +#0x76968000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvmini.hu xrD, xrJ, imm10_5 is op15_31=0xed2d & xrD & xrJ & imm10_5 { + xrD = xvmini.hu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvmini.wu; + +#lasx.txt xvmini.wu mask=0x76970000 +#0x76970000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvmini.wu xrD, xrJ, imm10_5 is op15_31=0xed2e & xrD & xrJ & imm10_5 { + xrD = xvmini.wu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvmini.du; + +#lasx.txt xvmini.du mask=0x76978000 +#0x76978000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvmini.du xrD, xrJ, imm10_5 is op15_31=0xed2f & xrD & xrJ & imm10_5 { + xrD = xvmini.du(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvfrstpi.b; + +#lasx.txt xvfrstpi.b mask=0x769a0000 +#0x769a0000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvfrstpi.b xrD, xrJ, imm10_5 is op15_31=0xed34 & xrD & xrJ & imm10_5 { + xrD = xvfrstpi.b(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvfrstpi.h; + +#lasx.txt xvfrstpi.h mask=0x769a8000 +#0x769a8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvfrstpi.h xrD, xrJ, imm10_5 is op15_31=0xed35 & xrD & xrJ & imm10_5 { + xrD = xvfrstpi.h(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvclo.b; + +#lasx.txt xvclo.b mask=0x769c0000 +#0x769c0000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvclo.b xrD, xrJ is op10_31=0x1da700 & xrD & xrJ { + xrD = xvclo.b(xrD, xrJ); +} + +define pcodeop xvclo.h; + +#lasx.txt xvclo.h mask=0x769c0400 +#0x769c0400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvclo.h xrD, xrJ is op10_31=0x1da701 & xrD & xrJ { + xrD = xvclo.h(xrD, xrJ); +} + +define pcodeop xvclo.w; + +#lasx.txt xvclo.w mask=0x769c0800 +#0x769c0800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvclo.w xrD, xrJ is op10_31=0x1da702 & xrD & xrJ { + xrD = xvclo.w(xrD, xrJ); +} + +define pcodeop xvclo.d; + +#lasx.txt xvclo.d mask=0x769c0c00 +#0x769c0c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvclo.d xrD, xrJ is op10_31=0x1da703 & xrD & xrJ { + xrD = xvclo.d(xrD, xrJ); +} + +define pcodeop xvclz.b; + +#lasx.txt xvclz.b mask=0x769c1000 +#0x769c1000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvclz.b xrD, xrJ is op10_31=0x1da704 & xrD & xrJ { + xrD = xvclz.b(xrD, xrJ); +} + +define pcodeop xvclz.h; + +#lasx.txt xvclz.h mask=0x769c1400 +#0x769c1400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvclz.h xrD, xrJ is op10_31=0x1da705 & xrD & xrJ { + xrD = xvclz.h(xrD, xrJ); +} + +define pcodeop xvclz.w; + +#lasx.txt xvclz.w mask=0x769c1800 +#0x769c1800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvclz.w xrD, xrJ is op10_31=0x1da706 & xrD & xrJ { + xrD = xvclz.w(xrD, xrJ); +} + +define pcodeop xvclz.d; + +#lasx.txt xvclz.d mask=0x769c1c00 +#0x769c1c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvclz.d xrD, xrJ is op10_31=0x1da707 & xrD & xrJ { + xrD = xvclz.d(xrD, xrJ); +} + +define pcodeop xvpcnt.b; + +#lasx.txt xvpcnt.b mask=0x769c2000 +#0x769c2000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvpcnt.b xrD, xrJ is op10_31=0x1da708 & xrD & xrJ { + xrD = xvpcnt.b(xrD, xrJ); +} + +define pcodeop xvpcnt.h; + +#lasx.txt xvpcnt.h mask=0x769c2400 +#0x769c2400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvpcnt.h xrD, xrJ is op10_31=0x1da709 & xrD & xrJ { + xrD = xvpcnt.h(xrD, xrJ); +} + +define pcodeop xvpcnt.w; + +#lasx.txt xvpcnt.w mask=0x769c2800 +#0x769c2800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvpcnt.w xrD, xrJ is op10_31=0x1da70a & xrD & xrJ { + xrD = xvpcnt.w(xrD, xrJ); +} + +define pcodeop xvpcnt.d; + +#lasx.txt xvpcnt.d mask=0x769c2c00 +#0x769c2c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvpcnt.d xrD, xrJ is op10_31=0x1da70b & xrD & xrJ { + xrD = xvpcnt.d(xrD, xrJ); +} + +define pcodeop xvneg.b; + +#lasx.txt xvneg.b mask=0x769c3000 +#0x769c3000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvneg.b xrD, xrJ is op10_31=0x1da70c & xrD & xrJ { + xrD = xvneg.b(xrD, xrJ); +} + +define pcodeop xvneg.h; + +#lasx.txt xvneg.h mask=0x769c3400 +#0x769c3400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvneg.h xrD, xrJ is op10_31=0x1da70d & xrD & xrJ { + xrD = xvneg.h(xrD, xrJ); +} + +define pcodeop xvneg.w; + +#lasx.txt xvneg.w mask=0x769c3800 +#0x769c3800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvneg.w xrD, xrJ is op10_31=0x1da70e & xrD & xrJ { + xrD = xvneg.w(xrD, xrJ); +} + +define pcodeop xvneg.d; + +#lasx.txt xvneg.d mask=0x769c3c00 +#0x769c3c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvneg.d xrD, xrJ is op10_31=0x1da70f & xrD & xrJ { + xrD = xvneg.d(xrD, xrJ); +} + +define pcodeop xvmskltz.b; + +#lasx.txt xvmskltz.b mask=0x769c4000 +#0x769c4000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvmskltz.b xrD, xrJ is op10_31=0x1da710 & xrD & xrJ { + xrD = xvmskltz.b(xrD, xrJ); +} + +define pcodeop xvmskltz.h; + +#lasx.txt xvmskltz.h mask=0x769c4400 +#0x769c4400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvmskltz.h xrD, xrJ is op10_31=0x1da711 & xrD & xrJ { + xrD = xvmskltz.h(xrD, xrJ); +} + +define pcodeop xvmskltz.w; + +#lasx.txt xvmskltz.w mask=0x769c4800 +#0x769c4800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvmskltz.w xrD, xrJ is op10_31=0x1da712 & xrD & xrJ { + xrD = xvmskltz.w(xrD, xrJ); +} + +define pcodeop xvmskltz.d; + +#lasx.txt xvmskltz.d mask=0x769c4c00 +#0x769c4c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvmskltz.d xrD, xrJ is op10_31=0x1da713 & xrD & xrJ { + xrD = xvmskltz.d(xrD, xrJ); +} + +define pcodeop xvmskgez.b; + +#lasx.txt xvmskgez.b mask=0x769c5000 +#0x769c5000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvmskgez.b xrD, xrJ is op10_31=0x1da714 & xrD & xrJ { + xrD = xvmskgez.b(xrD, xrJ); +} + +define pcodeop xvmsknz.b; + +#lasx.txt xvmsknz.b mask=0x769c6000 +#0x769c6000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvmsknz.b xrD, xrJ is op10_31=0x1da718 & xrD & xrJ { + xrD = xvmsknz.b(xrD, xrJ); +} + +define pcodeop xvseteqz.v; + +#lasx.txt xvseteqz.v mask=0x769c9800 +#0x769c9800 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvseteqz.v fccD, xrJ is op10_31=0x1da726 & fccD & xrJ { + fccD = xvseteqz.v(fccD, xrJ); +} + +define pcodeop xvsetnez.v; + +#lasx.txt xvsetnez.v mask=0x769c9c00 +#0x769c9c00 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetnez.v fccD, xrJ is op10_31=0x1da727 & fccD & xrJ { + fccD = xvsetnez.v(fccD, xrJ); +} + +define pcodeop xvsetanyeqz.b; + +#lasx.txt xvsetanyeqz.b mask=0x769ca000 +#0x769ca000 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetanyeqz.b fccD, xrJ is op10_31=0x1da728 & fccD & xrJ { + fccD = xvsetanyeqz.b(fccD, xrJ); +} + +define pcodeop xvsetanyeqz.h; + +#lasx.txt xvsetanyeqz.h mask=0x769ca400 +#0x769ca400 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetanyeqz.h fccD, xrJ is op10_31=0x1da729 & fccD & xrJ { + fccD = xvsetanyeqz.h(fccD, xrJ); +} + +define pcodeop xvsetanyeqz.w; + +#lasx.txt xvsetanyeqz.w mask=0x769ca800 +#0x769ca800 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetanyeqz.w fccD, xrJ is op10_31=0x1da72a & fccD & xrJ { + fccD = xvsetanyeqz.w(fccD, xrJ); +} + +define pcodeop xvsetanyeqz.d; + +#lasx.txt xvsetanyeqz.d mask=0x769cac00 +#0x769cac00 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetanyeqz.d fccD, xrJ is op10_31=0x1da72b & fccD & xrJ { + fccD = xvsetanyeqz.d(fccD, xrJ); +} + +define pcodeop xvsetallnez.b; + +#lasx.txt xvsetallnez.b mask=0x769cb000 +#0x769cb000 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetallnez.b fccD, xrJ is op10_31=0x1da72c & fccD & xrJ { + fccD = xvsetallnez.b(fccD, xrJ); +} + +define pcodeop xvsetallnez.h; + +#lasx.txt xvsetallnez.h mask=0x769cb400 +#0x769cb400 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetallnez.h fccD, xrJ is op10_31=0x1da72d & fccD & xrJ { + fccD = xvsetallnez.h(fccD, xrJ); +} + +define pcodeop xvsetallnez.w; + +#lasx.txt xvsetallnez.w mask=0x769cb800 +#0x769cb800 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetallnez.w fccD, xrJ is op10_31=0x1da72e & fccD & xrJ { + fccD = xvsetallnez.w(fccD, xrJ); +} + +define pcodeop xvsetallnez.d; + +#lasx.txt xvsetallnez.d mask=0x769cbc00 +#0x769cbc00 0xfffffc18 c0:3,x5:5 ['fcc0_3_s0', 'xreg5_5_s0'] +:xvsetallnez.d fccD, xrJ is op10_31=0x1da72f & fccD & xrJ { + fccD = xvsetallnez.d(fccD, xrJ); +} + +define pcodeop xvflogb.s; + +#lasx.txt xvflogb.s mask=0x769cc400 +#0x769cc400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvflogb.s xrD, xrJ is op10_31=0x1da731 & xrD & xrJ { + xrD = xvflogb.s(xrD, xrJ); +} + +define pcodeop xvflogb.d; + +#lasx.txt xvflogb.d mask=0x769cc800 +#0x769cc800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvflogb.d xrD, xrJ is op10_31=0x1da732 & xrD & xrJ { + xrD = xvflogb.d(xrD, xrJ); +} + +define pcodeop xvfclass.s; + +#lasx.txt xvfclass.s mask=0x769cd400 +#0x769cd400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfclass.s xrD, xrJ is op10_31=0x1da735 & xrD & xrJ { + xrD = xvfclass.s(xrD, xrJ); +} + +define pcodeop xvfclass.d; + +#lasx.txt xvfclass.d mask=0x769cd800 +#0x769cd800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfclass.d xrD, xrJ is op10_31=0x1da736 & xrD & xrJ { + xrD = xvfclass.d(xrD, xrJ); +} + +define pcodeop xvfsqrt.s; + +#lasx.txt xvfsqrt.s mask=0x769ce400 +#0x769ce400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfsqrt.s xrD, xrJ is op10_31=0x1da739 & xrD & xrJ { + xrD = xvfsqrt.s(xrD, xrJ); +} + +define pcodeop xvfsqrt.d; + +#lasx.txt xvfsqrt.d mask=0x769ce800 +#0x769ce800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfsqrt.d xrD, xrJ is op10_31=0x1da73a & xrD & xrJ { + xrD = xvfsqrt.d(xrD, xrJ); +} + +define pcodeop xvfrecip.s; + +#lasx.txt xvfrecip.s mask=0x769cf400 +#0x769cf400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrecip.s xrD, xrJ is op10_31=0x1da73d & xrD & xrJ { + xrD = xvfrecip.s(xrD, xrJ); +} + +define pcodeop xvfrecip.d; + +#lasx.txt xvfrecip.d mask=0x769cf800 +#0x769cf800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrecip.d xrD, xrJ is op10_31=0x1da73e & xrD & xrJ { + xrD = xvfrecip.d(xrD, xrJ); +} + +define pcodeop xvfrsqrt.s; + +#lasx.txt xvfrsqrt.s mask=0x769d0400 +#0x769d0400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrsqrt.s xrD, xrJ is op10_31=0x1da741 & xrD & xrJ { + xrD = xvfrsqrt.s(xrD, xrJ); +} + +define pcodeop xvfrsqrt.d; + +#lasx.txt xvfrsqrt.d mask=0x769d0800 +#0x769d0800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrsqrt.d xrD, xrJ is op10_31=0x1da742 & xrD & xrJ { + xrD = xvfrsqrt.d(xrD, xrJ); +} + +define pcodeop xvfrint.s; + +#lasx.txt xvfrint.s mask=0x769d3400 +#0x769d3400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrint.s xrD, xrJ is op10_31=0x1da74d & xrD & xrJ { + xrD = xvfrint.s(xrD, xrJ); +} + +define pcodeop xvfrint.d; + +#lasx.txt xvfrint.d mask=0x769d3800 +#0x769d3800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrint.d xrD, xrJ is op10_31=0x1da74e & xrD & xrJ { + xrD = xvfrint.d(xrD, xrJ); +} + +define pcodeop xvfrintrm.s; + +#lasx.txt xvfrintrm.s mask=0x769d4400 +#0x769d4400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrintrm.s xrD, xrJ is op10_31=0x1da751 & xrD & xrJ { + xrD = xvfrintrm.s(xrD, xrJ); +} + +define pcodeop xvfrintrm.d; + +#lasx.txt xvfrintrm.d mask=0x769d4800 +#0x769d4800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrintrm.d xrD, xrJ is op10_31=0x1da752 & xrD & xrJ { + xrD = xvfrintrm.d(xrD, xrJ); +} + +define pcodeop xvfrintrp.s; + +#lasx.txt xvfrintrp.s mask=0x769d5400 +#0x769d5400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrintrp.s xrD, xrJ is op10_31=0x1da755 & xrD & xrJ { + xrD = xvfrintrp.s(xrD, xrJ); +} + +define pcodeop xvfrintrp.d; + +#lasx.txt xvfrintrp.d mask=0x769d5800 +#0x769d5800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrintrp.d xrD, xrJ is op10_31=0x1da756 & xrD & xrJ { + xrD = xvfrintrp.d(xrD, xrJ); +} + +define pcodeop xvfrintrz.s; + +#lasx.txt xvfrintrz.s mask=0x769d6400 +#0x769d6400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrintrz.s xrD, xrJ is op10_31=0x1da759 & xrD & xrJ { + xrD = xvfrintrz.s(xrD, xrJ); +} + +define pcodeop xvfrintrz.d; + +#lasx.txt xvfrintrz.d mask=0x769d6800 +#0x769d6800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrintrz.d xrD, xrJ is op10_31=0x1da75a & xrD & xrJ { + xrD = xvfrintrz.d(xrD, xrJ); +} + +define pcodeop xvfrintrne.s; + +#lasx.txt xvfrintrne.s mask=0x769d7400 +#0x769d7400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrintrne.s xrD, xrJ is op10_31=0x1da75d & xrD & xrJ { + xrD = xvfrintrne.s(xrD, xrJ); +} + +define pcodeop xvfrintrne.d; + +#lasx.txt xvfrintrne.d mask=0x769d7800 +#0x769d7800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfrintrne.d xrD, xrJ is op10_31=0x1da75e & xrD & xrJ { + xrD = xvfrintrne.d(xrD, xrJ); +} + +define pcodeop xvfcvtl.s.h; + +#lasx.txt xvfcvtl.s.h mask=0x769de800 +#0x769de800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfcvtl.s.h xrD, xrJ is op10_31=0x1da77a & xrD & xrJ { + xrD = xvfcvtl.s.h(xrD, xrJ); +} + +define pcodeop xvfcvth.s.h; + +#lasx.txt xvfcvth.s.h mask=0x769dec00 +#0x769dec00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfcvth.s.h xrD, xrJ is op10_31=0x1da77b & xrD & xrJ { + xrD = xvfcvth.s.h(xrD, xrJ); +} + +define pcodeop xvfcvtl.d.s; + +#lasx.txt xvfcvtl.d.s mask=0x769df000 +#0x769df000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfcvtl.d.s xrD, xrJ is op10_31=0x1da77c & xrD & xrJ { + xrD = xvfcvtl.d.s(xrD, xrJ); +} + +define pcodeop xvfcvth.d.s; + +#lasx.txt xvfcvth.d.s mask=0x769df400 +#0x769df400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvfcvth.d.s xrD, xrJ is op10_31=0x1da77d & xrD & xrJ { + xrD = xvfcvth.d.s(xrD, xrJ); +} + +define pcodeop xvffint.s.w; + +#lasx.txt xvffint.s.w mask=0x769e0000 +#0x769e0000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvffint.s.w xrD, xrJ is op10_31=0x1da780 & xrD & xrJ { + xrD = xvffint.s.w(xrD, xrJ); +} + +define pcodeop xvffint.s.wu; + +#lasx.txt xvffint.s.wu mask=0x769e0400 +#0x769e0400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvffint.s.wu xrD, xrJ is op10_31=0x1da781 & xrD & xrJ { + xrD = xvffint.s.wu(xrD, xrJ); +} + +define pcodeop xvffint.d.l; + +#lasx.txt xvffint.d.l mask=0x769e0800 +#0x769e0800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvffint.d.l xrD, xrJ is op10_31=0x1da782 & xrD & xrJ { + xrD = xvffint.d.l(xrD, xrJ); +} + +define pcodeop xvffint.d.lu; + +#lasx.txt xvffint.d.lu mask=0x769e0c00 +#0x769e0c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvffint.d.lu xrD, xrJ is op10_31=0x1da783 & xrD & xrJ { + xrD = xvffint.d.lu(xrD, xrJ); +} + +define pcodeop xvffintl.d.w; + +#lasx.txt xvffintl.d.w mask=0x769e1000 +#0x769e1000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvffintl.d.w xrD, xrJ is op10_31=0x1da784 & xrD & xrJ { + xrD = xvffintl.d.w(xrD, xrJ); +} + +define pcodeop xvffinth.d.w; + +#lasx.txt xvffinth.d.w mask=0x769e1400 +#0x769e1400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvffinth.d.w xrD, xrJ is op10_31=0x1da785 & xrD & xrJ { + xrD = xvffinth.d.w(xrD, xrJ); +} + +define pcodeop xvftint.w.s; + +#lasx.txt xvftint.w.s mask=0x769e3000 +#0x769e3000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftint.w.s xrD, xrJ is op10_31=0x1da78c & xrD & xrJ { + xrD = xvftint.w.s(xrD, xrJ); +} + +define pcodeop xvftint.l.d; + +#lasx.txt xvftint.l.d mask=0x769e3400 +#0x769e3400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftint.l.d xrD, xrJ is op10_31=0x1da78d & xrD & xrJ { + xrD = xvftint.l.d(xrD, xrJ); +} + +define pcodeop xvftintrm.w.s; + +#lasx.txt xvftintrm.w.s mask=0x769e3800 +#0x769e3800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrm.w.s xrD, xrJ is op10_31=0x1da78e & xrD & xrJ { + xrD = xvftintrm.w.s(xrD, xrJ); +} + +define pcodeop xvftintrm.l.d; + +#lasx.txt xvftintrm.l.d mask=0x769e3c00 +#0x769e3c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrm.l.d xrD, xrJ is op10_31=0x1da78f & xrD & xrJ { + xrD = xvftintrm.l.d(xrD, xrJ); +} + +define pcodeop xvftintrp.w.s; + +#lasx.txt xvftintrp.w.s mask=0x769e4000 +#0x769e4000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrp.w.s xrD, xrJ is op10_31=0x1da790 & xrD & xrJ { + xrD = xvftintrp.w.s(xrD, xrJ); +} + +define pcodeop xvftintrp.l.d; + +#lasx.txt xvftintrp.l.d mask=0x769e4400 +#0x769e4400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrp.l.d xrD, xrJ is op10_31=0x1da791 & xrD & xrJ { + xrD = xvftintrp.l.d(xrD, xrJ); +} + +define pcodeop xvftintrz.w.s; + +#lasx.txt xvftintrz.w.s mask=0x769e4800 +#0x769e4800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrz.w.s xrD, xrJ is op10_31=0x1da792 & xrD & xrJ { + xrD = xvftintrz.w.s(xrD, xrJ); +} + +define pcodeop xvftintrz.l.d; + +#lasx.txt xvftintrz.l.d mask=0x769e4c00 +#0x769e4c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrz.l.d xrD, xrJ is op10_31=0x1da793 & xrD & xrJ { + xrD = xvftintrz.l.d(xrD, xrJ); +} + +define pcodeop xvftintrne.w.s; + +#lasx.txt xvftintrne.w.s mask=0x769e5000 +#0x769e5000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrne.w.s xrD, xrJ is op10_31=0x1da794 & xrD & xrJ { + xrD = xvftintrne.w.s(xrD, xrJ); +} + +define pcodeop xvftintrne.l.d; + +#lasx.txt xvftintrne.l.d mask=0x769e5400 +#0x769e5400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrne.l.d xrD, xrJ is op10_31=0x1da795 & xrD & xrJ { + xrD = xvftintrne.l.d(xrD, xrJ); +} + +define pcodeop xvftint.wu.s; + +#lasx.txt xvftint.wu.s mask=0x769e5800 +#0x769e5800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftint.wu.s xrD, xrJ is op10_31=0x1da796 & xrD & xrJ { + xrD = xvftint.wu.s(xrD, xrJ); +} + +define pcodeop xvftint.lu.d; + +#lasx.txt xvftint.lu.d mask=0x769e5c00 +#0x769e5c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftint.lu.d xrD, xrJ is op10_31=0x1da797 & xrD & xrJ { + xrD = xvftint.lu.d(xrD, xrJ); +} + +define pcodeop xvftintrz.wu.s; + +#lasx.txt xvftintrz.wu.s mask=0x769e7000 +#0x769e7000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrz.wu.s xrD, xrJ is op10_31=0x1da79c & xrD & xrJ { + xrD = xvftintrz.wu.s(xrD, xrJ); +} + +define pcodeop xvftintrz.lu.d; + +#lasx.txt xvftintrz.lu.d mask=0x769e7400 +#0x769e7400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrz.lu.d xrD, xrJ is op10_31=0x1da79d & xrD & xrJ { + xrD = xvftintrz.lu.d(xrD, xrJ); +} + +define pcodeop xvftintl.l.s; + +#lasx.txt xvftintl.l.s mask=0x769e8000 +#0x769e8000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintl.l.s xrD, xrJ is op10_31=0x1da7a0 & xrD & xrJ { + xrD = xvftintl.l.s(xrD, xrJ); +} + +define pcodeop xvftinth.l.s; + +#lasx.txt xvftinth.l.s mask=0x769e8400 +#0x769e8400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftinth.l.s xrD, xrJ is op10_31=0x1da7a1 & xrD & xrJ { + xrD = xvftinth.l.s(xrD, xrJ); +} + +define pcodeop xvftintrml.l.s; + +#lasx.txt xvftintrml.l.s mask=0x769e8800 +#0x769e8800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrml.l.s xrD, xrJ is op10_31=0x1da7a2 & xrD & xrJ { + xrD = xvftintrml.l.s(xrD, xrJ); +} + +define pcodeop xvftintrmh.l.s; + +#lasx.txt xvftintrmh.l.s mask=0x769e8c00 +#0x769e8c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrmh.l.s xrD, xrJ is op10_31=0x1da7a3 & xrD & xrJ { + xrD = xvftintrmh.l.s(xrD, xrJ); +} + +define pcodeop xvftintrpl.l.s; + +#lasx.txt xvftintrpl.l.s mask=0x769e9000 +#0x769e9000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrpl.l.s xrD, xrJ is op10_31=0x1da7a4 & xrD & xrJ { + xrD = xvftintrpl.l.s(xrD, xrJ); +} + +define pcodeop xvftintrph.l.s; + +#lasx.txt xvftintrph.l.s mask=0x769e9400 +#0x769e9400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrph.l.s xrD, xrJ is op10_31=0x1da7a5 & xrD & xrJ { + xrD = xvftintrph.l.s(xrD, xrJ); +} + +define pcodeop xvftintrzl.l.s; + +#lasx.txt xvftintrzl.l.s mask=0x769e9800 +#0x769e9800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrzl.l.s xrD, xrJ is op10_31=0x1da7a6 & xrD & xrJ { + xrD = xvftintrzl.l.s(xrD, xrJ); +} + +define pcodeop xvftintrzh.l.s; + +#lasx.txt xvftintrzh.l.s mask=0x769e9c00 +#0x769e9c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrzh.l.s xrD, xrJ is op10_31=0x1da7a7 & xrD & xrJ { + xrD = xvftintrzh.l.s(xrD, xrJ); +} + +define pcodeop xvftintrnel.l.s; + +#lasx.txt xvftintrnel.l.s mask=0x769ea000 +#0x769ea000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrnel.l.s xrD, xrJ is op10_31=0x1da7a8 & xrD & xrJ { + xrD = xvftintrnel.l.s(xrD, xrJ); +} + +define pcodeop xvftintrneh.l.s; + +#lasx.txt xvftintrneh.l.s mask=0x769ea400 +#0x769ea400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvftintrneh.l.s xrD, xrJ is op10_31=0x1da7a9 & xrD & xrJ { + xrD = xvftintrneh.l.s(xrD, xrJ); +} + +define pcodeop xvexth.h.b; + +#lasx.txt xvexth.h.b mask=0x769ee000 +#0x769ee000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvexth.h.b xrD, xrJ is op10_31=0x1da7b8 & xrD & xrJ { + xrD = xvexth.h.b(xrD, xrJ); +} + +define pcodeop xvexth.w.h; + +#lasx.txt xvexth.w.h mask=0x769ee400 +#0x769ee400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvexth.w.h xrD, xrJ is op10_31=0x1da7b9 & xrD & xrJ { + xrD = xvexth.w.h(xrD, xrJ); +} + +define pcodeop xvexth.d.w; + +#lasx.txt xvexth.d.w mask=0x769ee800 +#0x769ee800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvexth.d.w xrD, xrJ is op10_31=0x1da7ba & xrD & xrJ { + xrD = xvexth.d.w(xrD, xrJ); +} + +define pcodeop xvexth.q.d; + +#lasx.txt xvexth.q.d mask=0x769eec00 +#0x769eec00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvexth.q.d xrD, xrJ is op10_31=0x1da7bb & xrD & xrJ { + xrD = xvexth.q.d(xrD, xrJ); +} + +define pcodeop xvexth.hu.bu; + +#lasx.txt xvexth.hu.bu mask=0x769ef000 +#0x769ef000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvexth.hu.bu xrD, xrJ is op10_31=0x1da7bc & xrD & xrJ { + xrD = xvexth.hu.bu(xrD, xrJ); +} + +define pcodeop xvexth.wu.hu; + +#lasx.txt xvexth.wu.hu mask=0x769ef400 +#0x769ef400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvexth.wu.hu xrD, xrJ is op10_31=0x1da7bd & xrD & xrJ { + xrD = xvexth.wu.hu(xrD, xrJ); +} + +define pcodeop xvexth.du.wu; + +#lasx.txt xvexth.du.wu mask=0x769ef800 +#0x769ef800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvexth.du.wu xrD, xrJ is op10_31=0x1da7be & xrD & xrJ { + xrD = xvexth.du.wu(xrD, xrJ); +} + +define pcodeop xvexth.qu.du; + +#lasx.txt xvexth.qu.du mask=0x769efc00 +#0x769efc00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvexth.qu.du xrD, xrJ is op10_31=0x1da7bf & xrD & xrJ { + xrD = xvexth.qu.du(xrD, xrJ); +} + +define pcodeop xvreplgr2vr.b; + +#lasx.txt xvreplgr2vr.b mask=0x769f0000 +#0x769f0000 0xfffffc00 x0:5, r5:5 ['xreg0_5_s0', 'reg5_5_s0'] +:xvreplgr2vr.b xrD, RJsrc is op10_31=0x1da7c0 & xrD & RJsrc { + xrD = xvreplgr2vr.b(xrD, RJsrc); +} + +define pcodeop xvreplgr2vr.h; + +#lasx.txt xvreplgr2vr.h mask=0x769f0400 +#0x769f0400 0xfffffc00 x0:5, r5:5 ['xreg0_5_s0', 'reg5_5_s0'] +:xvreplgr2vr.h xrD, RJsrc is op10_31=0x1da7c1 & xrD & RJsrc { + xrD = xvreplgr2vr.h(xrD, RJsrc); +} + +define pcodeop xvreplgr2vr.w; + +#lasx.txt xvreplgr2vr.w mask=0x769f0800 +#0x769f0800 0xfffffc00 x0:5, r5:5 ['xreg0_5_s0', 'reg5_5_s0'] +:xvreplgr2vr.w xrD, RJsrc is op10_31=0x1da7c2 & xrD & RJsrc { + xrD = xvreplgr2vr.w(xrD, RJsrc); +} + +define pcodeop xvreplgr2vr.d; + +#lasx.txt xvreplgr2vr.d mask=0x769f0c00 +#0x769f0c00 0xfffffc00 x0:5, r5:5 ['xreg0_5_s0', 'reg5_5_s0'] +:xvreplgr2vr.d xrD, RJsrc is op10_31=0x1da7c3 & xrD & RJsrc { + xrD = xvreplgr2vr.d(xrD, RJsrc); +} + +define pcodeop vext2xv.h.b; + +#lasx.txt vext2xv.h.b mask=0x769f1000 +#0x769f1000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.h.b xrD, xrJ is op10_31=0x1da7c4 & xrD & xrJ { + xrD = vext2xv.h.b(xrD, xrJ); +} + +define pcodeop vext2xv.w.b; + +#lasx.txt vext2xv.w.b mask=0x769f1400 +#0x769f1400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.w.b xrD, xrJ is op10_31=0x1da7c5 & xrD & xrJ { + xrD = vext2xv.w.b(xrD, xrJ); +} + +define pcodeop vext2xv.d.b; + +#lasx.txt vext2xv.d.b mask=0x769f1800 +#0x769f1800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.d.b xrD, xrJ is op10_31=0x1da7c6 & xrD & xrJ { + xrD = vext2xv.d.b(xrD, xrJ); +} + +define pcodeop vext2xv.w.h; + +#lasx.txt vext2xv.w.h mask=0x769f1c00 +#0x769f1c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.w.h xrD, xrJ is op10_31=0x1da7c7 & xrD & xrJ { + xrD = vext2xv.w.h(xrD, xrJ); +} + +define pcodeop vext2xv.d.h; + +#lasx.txt vext2xv.d.h mask=0x769f2000 +#0x769f2000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.d.h xrD, xrJ is op10_31=0x1da7c8 & xrD & xrJ { + xrD = vext2xv.d.h(xrD, xrJ); +} + +define pcodeop vext2xv.d.w; + +#lasx.txt vext2xv.d.w mask=0x769f2400 +#0x769f2400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.d.w xrD, xrJ is op10_31=0x1da7c9 & xrD & xrJ { + xrD = vext2xv.d.w(xrD, xrJ); +} + +define pcodeop vext2xv.hu.bu; + +#lasx.txt vext2xv.hu.bu mask=0x769f2800 +#0x769f2800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.hu.bu xrD, xrJ is op10_31=0x1da7ca & xrD & xrJ { + xrD = vext2xv.hu.bu(xrD, xrJ); +} + +define pcodeop vext2xv.wu.bu; + +#lasx.txt vext2xv.wu.bu mask=0x769f2c00 +#0x769f2c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.wu.bu xrD, xrJ is op10_31=0x1da7cb & xrD & xrJ { + xrD = vext2xv.wu.bu(xrD, xrJ); +} + +define pcodeop vext2xv.du.bu; + +#lasx.txt vext2xv.du.bu mask=0x769f3000 +#0x769f3000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.du.bu xrD, xrJ is op10_31=0x1da7cc & xrD & xrJ { + xrD = vext2xv.du.bu(xrD, xrJ); +} + +define pcodeop vext2xv.wu.hu; + +#lasx.txt vext2xv.wu.hu mask=0x769f3400 +#0x769f3400 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.wu.hu xrD, xrJ is op10_31=0x1da7cd & xrD & xrJ { + xrD = vext2xv.wu.hu(xrD, xrJ); +} + +define pcodeop vext2xv.du.hu; + +#lasx.txt vext2xv.du.hu mask=0x769f3800 +#0x769f3800 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.du.hu xrD, xrJ is op10_31=0x1da7ce & xrD & xrJ { + xrD = vext2xv.du.hu(xrD, xrJ); +} + +define pcodeop vext2xv.du.wu; + +#lasx.txt vext2xv.du.wu mask=0x769f3c00 +#0x769f3c00 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:vext2xv.du.wu xrD, xrJ is op10_31=0x1da7cf & xrD & xrJ { + xrD = vext2xv.du.wu(xrD, xrJ); +} + +define pcodeop xvrotri.b; + +#lasx.txt xvrotri.b mask=0x76a02000 +#0x76a02000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvrotri.b xrD, xrJ, imm10_3 is op13_31=0x3b501 & xrD & xrJ & imm10_3 { + xrD = xvrotri.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvrotri.h; + +#lasx.txt xvrotri.h mask=0x76a04000 +#0x76a04000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvrotri.h xrD, xrJ, imm10_4 is op14_31=0x1da81 & xrD & xrJ & imm10_4 { + xrD = xvrotri.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvrotri.w; + +#lasx.txt xvrotri.w mask=0x76a08000 +#0x76a08000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvrotri.w xrD, xrJ, imm10_5 is op15_31=0xed41 & xrD & xrJ & imm10_5 { + xrD = xvrotri.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvrotri.d; + +#lasx.txt xvrotri.d mask=0x76a10000 +#0x76a10000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvrotri.d xrD, xrJ, imm10_6 is op16_31=0x76a1 & xrD & xrJ & imm10_6 { + xrD = xvrotri.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrlri.b; + +#lasx.txt xvsrlri.b mask=0x76a42000 +#0x76a42000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvsrlri.b xrD, xrJ, imm10_3 is op13_31=0x3b521 & xrD & xrJ & imm10_3 { + xrD = xvsrlri.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvsrlri.h; + +#lasx.txt xvsrlri.h mask=0x76a44000 +#0x76a44000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsrlri.h xrD, xrJ, imm10_4 is op14_31=0x1da91 & xrD & xrJ & imm10_4 { + xrD = xvsrlri.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsrlri.w; + +#lasx.txt xvsrlri.w mask=0x76a48000 +#0x76a48000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsrlri.w xrD, xrJ, imm10_5 is op15_31=0xed49 & xrD & xrJ & imm10_5 { + xrD = xvsrlri.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsrlri.d; + +#lasx.txt xvsrlri.d mask=0x76a50000 +#0x76a50000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsrlri.d xrD, xrJ, imm10_6 is op16_31=0x76a5 & xrD & xrJ & imm10_6 { + xrD = xvsrlri.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrari.b; + +#lasx.txt xvsrari.b mask=0x76a82000 +#0x76a82000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvsrari.b xrD, xrJ, imm10_3 is op13_31=0x3b541 & xrD & xrJ & imm10_3 { + xrD = xvsrari.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvsrari.h; + +#lasx.txt xvsrari.h mask=0x76a84000 +#0x76a84000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsrari.h xrD, xrJ, imm10_4 is op14_31=0x1daa1 & xrD & xrJ & imm10_4 { + xrD = xvsrari.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsrari.w; + +#lasx.txt xvsrari.w mask=0x76a88000 +#0x76a88000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsrari.w xrD, xrJ, imm10_5 is op15_31=0xed51 & xrD & xrJ & imm10_5 { + xrD = xvsrari.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsrari.d; + +#lasx.txt xvsrari.d mask=0x76a90000 +#0x76a90000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsrari.d xrD, xrJ, imm10_6 is op16_31=0x76a9 & xrD & xrJ & imm10_6 { + xrD = xvsrari.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvinsgr2vr.w; + +#lasx.txt xvinsgr2vr.w mask=0x76ebc000 +#0x76ebc000 0xffffe000 x0:5, r5:5,u10:3 ['xreg0_5_s0', 'reg5_5_s0', 'imm10_3_s0'] +:xvinsgr2vr.w xrD, RJsrc, imm10_3 is op13_31=0x3b75e & xrD & RJsrc & imm10_3 { + xrD = xvinsgr2vr.w(xrD, RJsrc, imm10_3:$(REGSIZE)); +} + +define pcodeop xvinsgr2vr.d; + +#lasx.txt xvinsgr2vr.d mask=0x76ebe000 +#0x76ebe000 0xfffff000 x0:5, r5:5,u10:2 ['xreg0_5_s0', 'reg5_5_s0', 'imm10_2_s0'] +:xvinsgr2vr.d xrD, RJsrc, imm10_2 is op12_31=0x76ebe & xrD & RJsrc & imm10_2 { + xrD = xvinsgr2vr.d(xrD, RJsrc, imm10_2:$(REGSIZE)); +} + +define pcodeop xvpickve2gr.w; + +#lasx.txt xvpickve2gr.w mask=0x76efc000 +#0x76efc000 0xffffe000 r0:5,x5:5,u10:3 ['reg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvpickve2gr.w RD, xrJ, imm10_3 is op13_31=0x3b77e & RD & xrJ & imm10_3 { + RD = xvpickve2gr.w(RD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvpickve2gr.d; + +#lasx.txt xvpickve2gr.d mask=0x76efe000 +#0x76efe000 0xfffff000 r0:5,x5:5,u10:2 ['reg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0'] +:xvpickve2gr.d RD, xrJ, imm10_2 is op12_31=0x76efe & RD & xrJ & imm10_2 { + RD = xvpickve2gr.d(RD, xrJ, imm10_2:$(REGSIZE)); +} + +define pcodeop xvpickve2gr.wu; + +#lasx.txt xvpickve2gr.wu mask=0x76f3c000 +#0x76f3c000 0xffffe000 r0:5,x5:5,u10:3 ['reg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvpickve2gr.wu RD, xrJ, imm10_3 is op13_31=0x3b79e & RD & xrJ & imm10_3 { + RD = xvpickve2gr.wu(RD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvpickve2gr.du; + +#lasx.txt xvpickve2gr.du mask=0x76f3e000 +#0x76f3e000 0xfffff000 r0:5,x5:5,u10:2 ['reg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0'] +:xvpickve2gr.du RD, xrJ, imm10_2 is op12_31=0x76f3e & RD & xrJ & imm10_2 { + RD = xvpickve2gr.du(RD, xrJ, imm10_2:$(REGSIZE)); +} + +define pcodeop xvrepl128vei.b; + +#lasx.txt xvrepl128vei.b mask=0x76f78000 +#0x76f78000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvrepl128vei.b xrD, xrJ, imm10_4 is op14_31=0x1dbde & xrD & xrJ & imm10_4 { + xrD = xvrepl128vei.b(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvrepl128vei.h; + +#lasx.txt xvrepl128vei.h mask=0x76f7c000 +#0x76f7c000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvrepl128vei.h xrD, xrJ, imm10_3 is op13_31=0x3b7be & xrD & xrJ & imm10_3 { + xrD = xvrepl128vei.h(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvrepl128vei.w; + +#lasx.txt xvrepl128vei.w mask=0x76f7e000 +#0x76f7e000 0xfffff000 x0:5,x5:5,u10:2 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0'] +:xvrepl128vei.w xrD, xrJ, imm10_2 is op12_31=0x76f7e & xrD & xrJ & imm10_2 { + xrD = xvrepl128vei.w(xrD, xrJ, imm10_2:$(REGSIZE)); +} + +define pcodeop xvrepl128vei.d; + +#lasx.txt xvrepl128vei.d mask=0x76f7f000 +#0x76f7f000 0xfffff800 x0:5,x5:5,u10:1 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_1_s0'] +:xvrepl128vei.d xrD, xrJ, imm10_1 is op11_31=0xedefe & xrD & xrJ & imm10_1 { + xrD = xvrepl128vei.d(xrD, xrJ, imm10_1:$(REGSIZE)); +} + +define pcodeop xvinsve0.w; + +#lasx.txt xvinsve0.w mask=0x76ffc000 +#0x76ffc000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvinsve0.w xrD, xrJ, imm10_3 is op13_31=0x3b7fe & xrD & xrJ & imm10_3 { + xrD = xvinsve0.w(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvinsve0.d; + +#lasx.txt xvinsve0.d mask=0x76ffe000 +#0x76ffe000 0xfffff000 x0:5,x5:5,u10:2 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0'] +:xvinsve0.d xrD, xrJ, imm10_2 is op12_31=0x76ffe & xrD & xrJ & imm10_2 { + xrD = xvinsve0.d(xrD, xrJ, imm10_2:$(REGSIZE)); +} + +define pcodeop xvpickve.w; + +#lasx.txt xvpickve.w mask=0x7703c000 +#0x7703c000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvpickve.w xrD, xrJ, imm10_3 is op13_31=0x3b81e & xrD & xrJ & imm10_3 { + xrD = xvpickve.w(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvpickve.d; + +#lasx.txt xvpickve.d mask=0x7703e000 +#0x7703e000 0xfffff000 x0:5,x5:5,u10:2 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_2_s0'] +:xvpickve.d xrD, xrJ, imm10_2 is op12_31=0x7703e & xrD & xrJ & imm10_2 { + xrD = xvpickve.d(xrD, xrJ, imm10_2:$(REGSIZE)); +} + +define pcodeop xvreplve0.b; + +#lasx.txt xvreplve0.b mask=0x77070000 +#0x77070000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvreplve0.b xrD, xrJ is op10_31=0x1dc1c0 & xrD & xrJ { + xrD = xvreplve0.b(xrD, xrJ); +} + +define pcodeop xvreplve0.h; + +#lasx.txt xvreplve0.h mask=0x77078000 +#0x77078000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvreplve0.h xrD, xrJ is op10_31=0x1dc1e0 & xrD & xrJ { + xrD = xvreplve0.h(xrD, xrJ); +} + +define pcodeop xvreplve0.w; + +#lasx.txt xvreplve0.w mask=0x7707c000 +#0x7707c000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvreplve0.w xrD, xrJ is op10_31=0x1dc1f0 & xrD & xrJ { + xrD = xvreplve0.w(xrD, xrJ); +} + +define pcodeop xvreplve0.d; + +#lasx.txt xvreplve0.d mask=0x7707e000 +#0x7707e000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvreplve0.d xrD, xrJ is op10_31=0x1dc1f8 & xrD & xrJ { + xrD = xvreplve0.d(xrD, xrJ); +} + +define pcodeop xvreplve0.q; + +#lasx.txt xvreplve0.q mask=0x7707f000 +#0x7707f000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvreplve0.q xrD, xrJ is op10_31=0x1dc1fc & xrD & xrJ { + xrD = xvreplve0.q(xrD, xrJ); +} + +define pcodeop xvsllwil.h.b; + +#lasx.txt xvsllwil.h.b mask=0x77082000 +#0x77082000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvsllwil.h.b xrD, xrJ, imm10_3 is op13_31=0x3b841 & xrD & xrJ & imm10_3 { + xrD = xvsllwil.h.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvsllwil.w.h; + +#lasx.txt xvsllwil.w.h mask=0x77084000 +#0x77084000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsllwil.w.h xrD, xrJ, imm10_4 is op14_31=0x1dc21 & xrD & xrJ & imm10_4 { + xrD = xvsllwil.w.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsllwil.d.w; + +#lasx.txt xvsllwil.d.w mask=0x77088000 +#0x77088000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsllwil.d.w xrD, xrJ, imm10_5 is op15_31=0xee11 & xrD & xrJ & imm10_5 { + xrD = xvsllwil.d.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvextl.q.d; + +#lasx.txt xvextl.q.d mask=0x77090000 +#0x77090000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvextl.q.d xrD, xrJ is op10_31=0x1dc240 & xrD & xrJ { + xrD = xvextl.q.d(xrD, xrJ); +} + +define pcodeop xvsllwil.hu.bu; + +#lasx.txt xvsllwil.hu.bu mask=0x770c2000 +#0x770c2000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvsllwil.hu.bu xrD, xrJ, imm10_3 is op13_31=0x3b861 & xrD & xrJ & imm10_3 { + xrD = xvsllwil.hu.bu(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvsllwil.wu.hu; + +#lasx.txt xvsllwil.wu.hu mask=0x770c4000 +#0x770c4000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsllwil.wu.hu xrD, xrJ, imm10_4 is op14_31=0x1dc31 & xrD & xrJ & imm10_4 { + xrD = xvsllwil.wu.hu(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsllwil.du.wu; + +#lasx.txt xvsllwil.du.wu mask=0x770c8000 +#0x770c8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsllwil.du.wu xrD, xrJ, imm10_5 is op15_31=0xee19 & xrD & xrJ & imm10_5 { + xrD = xvsllwil.du.wu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvextl.qu.du; + +#lasx.txt xvextl.qu.du mask=0x770d0000 +#0x770d0000 0xfffffc00 x0:5,x5:5 ['xreg0_5_s0', 'xreg5_5_s0'] +:xvextl.qu.du xrD, xrJ is op10_31=0x1dc340 & xrD & xrJ { + xrD = xvextl.qu.du(xrD, xrJ); +} + +define pcodeop xvbitclri.b; + +#lasx.txt xvbitclri.b mask=0x77102000 +#0x77102000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvbitclri.b xrD, xrJ, imm10_3 is op13_31=0x3b881 & xrD & xrJ & imm10_3 { + xrD = xvbitclri.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvbitclri.h; + +#lasx.txt xvbitclri.h mask=0x77104000 +#0x77104000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvbitclri.h xrD, xrJ, imm10_4 is op14_31=0x1dc41 & xrD & xrJ & imm10_4 { + xrD = xvbitclri.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvbitclri.w; + +#lasx.txt xvbitclri.w mask=0x77108000 +#0x77108000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvbitclri.w xrD, xrJ, imm10_5 is op15_31=0xee21 & xrD & xrJ & imm10_5 { + xrD = xvbitclri.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvbitclri.d; + +#lasx.txt xvbitclri.d mask=0x77110000 +#0x77110000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvbitclri.d xrD, xrJ, imm10_6 is op16_31=0x7711 & xrD & xrJ & imm10_6 { + xrD = xvbitclri.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvbitseti.b; + +#lasx.txt xvbitseti.b mask=0x77142000 +#0x77142000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvbitseti.b xrD, xrJ, imm10_3 is op13_31=0x3b8a1 & xrD & xrJ & imm10_3 { + xrD = xvbitseti.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvbitseti.h; + +#lasx.txt xvbitseti.h mask=0x77144000 +#0x77144000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvbitseti.h xrD, xrJ, imm10_4 is op14_31=0x1dc51 & xrD & xrJ & imm10_4 { + xrD = xvbitseti.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvbitseti.w; + +#lasx.txt xvbitseti.w mask=0x77148000 +#0x77148000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvbitseti.w xrD, xrJ, imm10_5 is op15_31=0xee29 & xrD & xrJ & imm10_5 { + xrD = xvbitseti.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvbitseti.d; + +#lasx.txt xvbitseti.d mask=0x77150000 +#0x77150000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvbitseti.d xrD, xrJ, imm10_6 is op16_31=0x7715 & xrD & xrJ & imm10_6 { + xrD = xvbitseti.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvbitrevi.b; + +#lasx.txt xvbitrevi.b mask=0x77182000 +#0x77182000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvbitrevi.b xrD, xrJ, imm10_3 is op13_31=0x3b8c1 & xrD & xrJ & imm10_3 { + xrD = xvbitrevi.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvbitrevi.h; + +#lasx.txt xvbitrevi.h mask=0x77184000 +#0x77184000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvbitrevi.h xrD, xrJ, imm10_4 is op14_31=0x1dc61 & xrD & xrJ & imm10_4 { + xrD = xvbitrevi.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvbitrevi.w; + +#lasx.txt xvbitrevi.w mask=0x77188000 +#0x77188000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvbitrevi.w xrD, xrJ, imm10_5 is op15_31=0xee31 & xrD & xrJ & imm10_5 { + xrD = xvbitrevi.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvbitrevi.d; + +#lasx.txt xvbitrevi.d mask=0x77190000 +#0x77190000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvbitrevi.d xrD, xrJ, imm10_6 is op16_31=0x7719 & xrD & xrJ & imm10_6 { + xrD = xvbitrevi.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsat.b; + +#lasx.txt xvsat.b mask=0x77242000 +#0x77242000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvsat.b xrD, xrJ, imm10_3 is op13_31=0x3b921 & xrD & xrJ & imm10_3 { + xrD = xvsat.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvsat.h; + +#lasx.txt xvsat.h mask=0x77244000 +#0x77244000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsat.h xrD, xrJ, imm10_4 is op14_31=0x1dc91 & xrD & xrJ & imm10_4 { + xrD = xvsat.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsat.w; + +#lasx.txt xvsat.w mask=0x77248000 +#0x77248000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsat.w xrD, xrJ, imm10_5 is op15_31=0xee49 & xrD & xrJ & imm10_5 { + xrD = xvsat.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsat.d; + +#lasx.txt xvsat.d mask=0x77250000 +#0x77250000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsat.d xrD, xrJ, imm10_6 is op16_31=0x7725 & xrD & xrJ & imm10_6 { + xrD = xvsat.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsat.bu; + +#lasx.txt xvsat.bu mask=0x77282000 +#0x77282000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvsat.bu xrD, xrJ, imm10_3 is op13_31=0x3b941 & xrD & xrJ & imm10_3 { + xrD = xvsat.bu(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvsat.hu; + +#lasx.txt xvsat.hu mask=0x77284000 +#0x77284000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsat.hu xrD, xrJ, imm10_4 is op14_31=0x1dca1 & xrD & xrJ & imm10_4 { + xrD = xvsat.hu(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsat.wu; + +#lasx.txt xvsat.wu mask=0x77288000 +#0x77288000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsat.wu xrD, xrJ, imm10_5 is op15_31=0xee51 & xrD & xrJ & imm10_5 { + xrD = xvsat.wu(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsat.du; + +#lasx.txt xvsat.du mask=0x77290000 +#0x77290000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsat.du xrD, xrJ, imm10_6 is op16_31=0x7729 & xrD & xrJ & imm10_6 { + xrD = xvsat.du(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvslli.b; + +#lasx.txt xvslli.b mask=0x772c2000 +#0x772c2000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvslli.b xrD, xrJ, imm10_3 is op13_31=0x3b961 & xrD & xrJ & imm10_3 { + xrD = xvslli.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvslli.h; + +#lasx.txt xvslli.h mask=0x772c4000 +#0x772c4000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvslli.h xrD, xrJ, imm10_4 is op14_31=0x1dcb1 & xrD & xrJ & imm10_4 { + xrD = xvslli.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvslli.w; + +#lasx.txt xvslli.w mask=0x772c8000 +#0x772c8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvslli.w xrD, xrJ, imm10_5 is op15_31=0xee59 & xrD & xrJ & imm10_5 { + xrD = xvslli.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvslli.d; + +#lasx.txt xvslli.d mask=0x772d0000 +#0x772d0000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvslli.d xrD, xrJ, imm10_6 is op16_31=0x772d & xrD & xrJ & imm10_6 { + xrD = xvslli.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrli.b; + +#lasx.txt xvsrli.b mask=0x77302000 +#0x77302000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvsrli.b xrD, xrJ, imm10_3 is op13_31=0x3b981 & xrD & xrJ & imm10_3 { + xrD = xvsrli.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvsrli.h; + +#lasx.txt xvsrli.h mask=0x77304000 +#0x77304000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsrli.h xrD, xrJ, imm10_4 is op14_31=0x1dcc1 & xrD & xrJ & imm10_4 { + xrD = xvsrli.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsrli.w; + +#lasx.txt xvsrli.w mask=0x77308000 +#0x77308000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsrli.w xrD, xrJ, imm10_5 is op15_31=0xee61 & xrD & xrJ & imm10_5 { + xrD = xvsrli.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsrli.d; + +#lasx.txt xvsrli.d mask=0x77310000 +#0x77310000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsrli.d xrD, xrJ, imm10_6 is op16_31=0x7731 & xrD & xrJ & imm10_6 { + xrD = xvsrli.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrai.b; + +#lasx.txt xvsrai.b mask=0x77342000 +#0x77342000 0xffffe000 x0:5,x5:5,u10:3 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_3_s0'] +:xvsrai.b xrD, xrJ, imm10_3 is op13_31=0x3b9a1 & xrD & xrJ & imm10_3 { + xrD = xvsrai.b(xrD, xrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop xvsrai.h; + +#lasx.txt xvsrai.h mask=0x77344000 +#0x77344000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsrai.h xrD, xrJ, imm10_4 is op14_31=0x1dcd1 & xrD & xrJ & imm10_4 { + xrD = xvsrai.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsrai.w; + +#lasx.txt xvsrai.w mask=0x77348000 +#0x77348000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsrai.w xrD, xrJ, imm10_5 is op15_31=0xee69 & xrD & xrJ & imm10_5 { + xrD = xvsrai.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsrai.d; + +#lasx.txt xvsrai.d mask=0x77350000 +#0x77350000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsrai.d xrD, xrJ, imm10_6 is op16_31=0x7735 & xrD & xrJ & imm10_6 { + xrD = xvsrai.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrlni.b.h; + +#lasx.txt xvsrlni.b.h mask=0x77404000 +#0x77404000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsrlni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd01 & xrD & xrJ & imm10_4 { + xrD = xvsrlni.b.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsrlni.h.w; + +#lasx.txt xvsrlni.h.w mask=0x77408000 +#0x77408000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsrlni.h.w xrD, xrJ, imm10_5 is op15_31=0xee81 & xrD & xrJ & imm10_5 { + xrD = xvsrlni.h.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsrlni.w.d; + +#lasx.txt xvsrlni.w.d mask=0x77410000 +#0x77410000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsrlni.w.d xrD, xrJ, imm10_6 is op16_31=0x7741 & xrD & xrJ & imm10_6 { + xrD = xvsrlni.w.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrlni.d.q; + +#lasx.txt xvsrlni.d.q mask=0x77420000 +#0x77420000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvsrlni.d.q xrD, xrJ, imm10_7 is op17_31=0x3ba1 & xrD & xrJ & imm10_7 { + xrD = xvsrlni.d.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvsrlrni.b.h; + +#lasx.txt xvsrlrni.b.h mask=0x77444000 +#0x77444000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsrlrni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd11 & xrD & xrJ & imm10_4 { + xrD = xvsrlrni.b.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsrlrni.h.w; + +#lasx.txt xvsrlrni.h.w mask=0x77448000 +#0x77448000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsrlrni.h.w xrD, xrJ, imm10_5 is op15_31=0xee89 & xrD & xrJ & imm10_5 { + xrD = xvsrlrni.h.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsrlrni.w.d; + +#lasx.txt xvsrlrni.w.d mask=0x77450000 +#0x77450000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsrlrni.w.d xrD, xrJ, imm10_6 is op16_31=0x7745 & xrD & xrJ & imm10_6 { + xrD = xvsrlrni.w.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrlrni.d.q; + +#lasx.txt xvsrlrni.d.q mask=0x77460000 +#0x77460000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvsrlrni.d.q xrD, xrJ, imm10_7 is op17_31=0x3ba3 & xrD & xrJ & imm10_7 { + xrD = xvsrlrni.d.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvssrlni.b.h; + +#lasx.txt xvssrlni.b.h mask=0x77484000 +#0x77484000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvssrlni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd21 & xrD & xrJ & imm10_4 { + xrD = xvssrlni.b.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvssrlni.h.w; + +#lasx.txt xvssrlni.h.w mask=0x77488000 +#0x77488000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvssrlni.h.w xrD, xrJ, imm10_5 is op15_31=0xee91 & xrD & xrJ & imm10_5 { + xrD = xvssrlni.h.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvssrlni.w.d; + +#lasx.txt xvssrlni.w.d mask=0x77490000 +#0x77490000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvssrlni.w.d xrD, xrJ, imm10_6 is op16_31=0x7749 & xrD & xrJ & imm10_6 { + xrD = xvssrlni.w.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvssrlni.d.q; + +#lasx.txt xvssrlni.d.q mask=0x774a0000 +#0x774a0000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvssrlni.d.q xrD, xrJ, imm10_7 is op17_31=0x3ba5 & xrD & xrJ & imm10_7 { + xrD = xvssrlni.d.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvssrlni.bu.h; + +#lasx.txt xvssrlni.bu.h mask=0x774c4000 +#0x774c4000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvssrlni.bu.h xrD, xrJ, imm10_4 is op14_31=0x1dd31 & xrD & xrJ & imm10_4 { + xrD = xvssrlni.bu.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvssrlni.hu.w; + +#lasx.txt xvssrlni.hu.w mask=0x774c8000 +#0x774c8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvssrlni.hu.w xrD, xrJ, imm10_5 is op15_31=0xee99 & xrD & xrJ & imm10_5 { + xrD = xvssrlni.hu.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvssrlni.wu.d; + +#lasx.txt xvssrlni.wu.d mask=0x774d0000 +#0x774d0000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvssrlni.wu.d xrD, xrJ, imm10_6 is op16_31=0x774d & xrD & xrJ & imm10_6 { + xrD = xvssrlni.wu.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvssrlni.du.q; + +#lasx.txt xvssrlni.du.q mask=0x774e0000 +#0x774e0000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvssrlni.du.q xrD, xrJ, imm10_7 is op17_31=0x3ba7 & xrD & xrJ & imm10_7 { + xrD = xvssrlni.du.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvssrlrni.b.h; + +#lasx.txt xvssrlrni.b.h mask=0x77504000 +#0x77504000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvssrlrni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd41 & xrD & xrJ & imm10_4 { + xrD = xvssrlrni.b.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvssrlrni.h.w; + +#lasx.txt xvssrlrni.h.w mask=0x77508000 +#0x77508000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvssrlrni.h.w xrD, xrJ, imm10_5 is op15_31=0xeea1 & xrD & xrJ & imm10_5 { + xrD = xvssrlrni.h.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvssrlrni.w.d; + +#lasx.txt xvssrlrni.w.d mask=0x77510000 +#0x77510000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvssrlrni.w.d xrD, xrJ, imm10_6 is op16_31=0x7751 & xrD & xrJ & imm10_6 { + xrD = xvssrlrni.w.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvssrlrni.d.q; + +#lasx.txt xvssrlrni.d.q mask=0x77520000 +#0x77520000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvssrlrni.d.q xrD, xrJ, imm10_7 is op17_31=0x3ba9 & xrD & xrJ & imm10_7 { + xrD = xvssrlrni.d.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvssrlrni.bu.h; + +#lasx.txt xvssrlrni.bu.h mask=0x77544000 +#0x77544000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvssrlrni.bu.h xrD, xrJ, imm10_4 is op14_31=0x1dd51 & xrD & xrJ & imm10_4 { + xrD = xvssrlrni.bu.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvssrlrni.hu.w; + +#lasx.txt xvssrlrni.hu.w mask=0x77548000 +#0x77548000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvssrlrni.hu.w xrD, xrJ, imm10_5 is op15_31=0xeea9 & xrD & xrJ & imm10_5 { + xrD = xvssrlrni.hu.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvssrlrni.wu.d; + +#lasx.txt xvssrlrni.wu.d mask=0x77550000 +#0x77550000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvssrlrni.wu.d xrD, xrJ, imm10_6 is op16_31=0x7755 & xrD & xrJ & imm10_6 { + xrD = xvssrlrni.wu.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvssrlrni.du.q; + +#lasx.txt xvssrlrni.du.q mask=0x77560000 +#0x77560000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvssrlrni.du.q xrD, xrJ, imm10_7 is op17_31=0x3bab & xrD & xrJ & imm10_7 { + xrD = xvssrlrni.du.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvsrani.b.h; + +#lasx.txt xvsrani.b.h mask=0x77584000 +#0x77584000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsrani.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd61 & xrD & xrJ & imm10_4 { + xrD = xvsrani.b.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsrani.h.w; + +#lasx.txt xvsrani.h.w mask=0x77588000 +#0x77588000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsrani.h.w xrD, xrJ, imm10_5 is op15_31=0xeeb1 & xrD & xrJ & imm10_5 { + xrD = xvsrani.h.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsrani.w.d; + +#lasx.txt xvsrani.w.d mask=0x77590000 +#0x77590000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsrani.w.d xrD, xrJ, imm10_6 is op16_31=0x7759 & xrD & xrJ & imm10_6 { + xrD = xvsrani.w.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrani.d.q; + +#lasx.txt xvsrani.d.q mask=0x775a0000 +#0x775a0000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvsrani.d.q xrD, xrJ, imm10_7 is op17_31=0x3bad & xrD & xrJ & imm10_7 { + xrD = xvsrani.d.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvsrarni.b.h; + +#lasx.txt xvsrarni.b.h mask=0x775c4000 +#0x775c4000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvsrarni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd71 & xrD & xrJ & imm10_4 { + xrD = xvsrarni.b.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvsrarni.h.w; + +#lasx.txt xvsrarni.h.w mask=0x775c8000 +#0x775c8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvsrarni.h.w xrD, xrJ, imm10_5 is op15_31=0xeeb9 & xrD & xrJ & imm10_5 { + xrD = xvsrarni.h.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvsrarni.w.d; + +#lasx.txt xvsrarni.w.d mask=0x775d0000 +#0x775d0000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvsrarni.w.d xrD, xrJ, imm10_6 is op16_31=0x775d & xrD & xrJ & imm10_6 { + xrD = xvsrarni.w.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvsrarni.d.q; + +#lasx.txt xvsrarni.d.q mask=0x775e0000 +#0x775e0000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvsrarni.d.q xrD, xrJ, imm10_7 is op17_31=0x3baf & xrD & xrJ & imm10_7 { + xrD = xvsrarni.d.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvssrani.b.h; + +#lasx.txt xvssrani.b.h mask=0x77604000 +#0x77604000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvssrani.b.h xrD, xrJ, imm10_4 is op14_31=0x1dd81 & xrD & xrJ & imm10_4 { + xrD = xvssrani.b.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvssrani.h.w; + +#lasx.txt xvssrani.h.w mask=0x77608000 +#0x77608000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvssrani.h.w xrD, xrJ, imm10_5 is op15_31=0xeec1 & xrD & xrJ & imm10_5 { + xrD = xvssrani.h.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvssrani.w.d; + +#lasx.txt xvssrani.w.d mask=0x77610000 +#0x77610000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvssrani.w.d xrD, xrJ, imm10_6 is op16_31=0x7761 & xrD & xrJ & imm10_6 { + xrD = xvssrani.w.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvssrani.d.q; + +#lasx.txt xvssrani.d.q mask=0x77620000 +#0x77620000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvssrani.d.q xrD, xrJ, imm10_7 is op17_31=0x3bb1 & xrD & xrJ & imm10_7 { + xrD = xvssrani.d.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvssrani.bu.h; + +#lasx.txt xvssrani.bu.h mask=0x77644000 +#0x77644000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvssrani.bu.h xrD, xrJ, imm10_4 is op14_31=0x1dd91 & xrD & xrJ & imm10_4 { + xrD = xvssrani.bu.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvssrani.hu.w; + +#lasx.txt xvssrani.hu.w mask=0x77648000 +#0x77648000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvssrani.hu.w xrD, xrJ, imm10_5 is op15_31=0xeec9 & xrD & xrJ & imm10_5 { + xrD = xvssrani.hu.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvssrani.wu.d; + +#lasx.txt xvssrani.wu.d mask=0x77650000 +#0x77650000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvssrani.wu.d xrD, xrJ, imm10_6 is op16_31=0x7765 & xrD & xrJ & imm10_6 { + xrD = xvssrani.wu.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvssrani.du.q; + +#lasx.txt xvssrani.du.q mask=0x77660000 +#0x77660000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvssrani.du.q xrD, xrJ, imm10_7 is op17_31=0x3bb3 & xrD & xrJ & imm10_7 { + xrD = xvssrani.du.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvssrarni.b.h; + +#lasx.txt xvssrarni.b.h mask=0x77684000 +#0x77684000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvssrarni.b.h xrD, xrJ, imm10_4 is op14_31=0x1dda1 & xrD & xrJ & imm10_4 { + xrD = xvssrarni.b.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvssrarni.h.w; + +#lasx.txt xvssrarni.h.w mask=0x77688000 +#0x77688000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvssrarni.h.w xrD, xrJ, imm10_5 is op15_31=0xeed1 & xrD & xrJ & imm10_5 { + xrD = xvssrarni.h.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvssrarni.w.d; + +#lasx.txt xvssrarni.w.d mask=0x77690000 +#0x77690000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvssrarni.w.d xrD, xrJ, imm10_6 is op16_31=0x7769 & xrD & xrJ & imm10_6 { + xrD = xvssrarni.w.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvssrarni.d.q; + +#lasx.txt xvssrarni.d.q mask=0x776a0000 +#0x776a0000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvssrarni.d.q xrD, xrJ, imm10_7 is op17_31=0x3bb5 & xrD & xrJ & imm10_7 { + xrD = xvssrarni.d.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvssrarni.bu.h; + +#lasx.txt xvssrarni.bu.h mask=0x776c4000 +#0x776c4000 0xffffc000 x0:5,x5:5,u10:4 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_4_s0'] +:xvssrarni.bu.h xrD, xrJ, imm10_4 is op14_31=0x1ddb1 & xrD & xrJ & imm10_4 { + xrD = xvssrarni.bu.h(xrD, xrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop xvssrarni.hu.w; + +#lasx.txt xvssrarni.hu.w mask=0x776c8000 +#0x776c8000 0xffff8000 x0:5,x5:5,u10:5 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_5_s0'] +:xvssrarni.hu.w xrD, xrJ, imm10_5 is op15_31=0xeed9 & xrD & xrJ & imm10_5 { + xrD = xvssrarni.hu.w(xrD, xrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop xvssrarni.wu.d; + +#lasx.txt xvssrarni.wu.d mask=0x776d0000 +#0x776d0000 0xffff0000 x0:5,x5:5,u10:6 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_6_s0'] +:xvssrarni.wu.d xrD, xrJ, imm10_6 is op16_31=0x776d & xrD & xrJ & imm10_6 { + xrD = xvssrarni.wu.d(xrD, xrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop xvssrarni.du.q; + +#lasx.txt xvssrarni.du.q mask=0x776e0000 +#0x776e0000 0xfffe0000 x0:5,x5:5,u10:7 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_7_s0'] +:xvssrarni.du.q xrD, xrJ, imm10_7 is op17_31=0x3bb7 & xrD & xrJ & imm10_7 { + xrD = xvssrarni.du.q(xrD, xrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop xvextrins.d; + +#lasx.txt xvextrins.d mask=0x77800000 +#0x77800000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvextrins.d xrD, xrJ, imm10_8 is op18_31=0x1de0 & xrD & xrJ & imm10_8 { + xrD = xvextrins.d(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvextrins.w; + +#lasx.txt xvextrins.w mask=0x77840000 +#0x77840000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvextrins.w xrD, xrJ, imm10_8 is op18_31=0x1de1 & xrD & xrJ & imm10_8 { + xrD = xvextrins.w(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvextrins.h; + +#lasx.txt xvextrins.h mask=0x77880000 +#0x77880000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvextrins.h xrD, xrJ, imm10_8 is op18_31=0x1de2 & xrD & xrJ & imm10_8 { + xrD = xvextrins.h(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvextrins.b; + +#lasx.txt xvextrins.b mask=0x778c0000 +#0x778c0000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvextrins.b xrD, xrJ, imm10_8 is op18_31=0x1de3 & xrD & xrJ & imm10_8 { + xrD = xvextrins.b(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvshuf4i.b; + +#lasx.txt xvshuf4i.b mask=0x77900000 +#0x77900000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvshuf4i.b xrD, xrJ, imm10_8 is op18_31=0x1de4 & xrD & xrJ & imm10_8 { + xrD = xvshuf4i.b(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvshuf4i.h; + +#lasx.txt xvshuf4i.h mask=0x77940000 +#0x77940000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvshuf4i.h xrD, xrJ, imm10_8 is op18_31=0x1de5 & xrD & xrJ & imm10_8 { + xrD = xvshuf4i.h(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvshuf4i.w; + +#lasx.txt xvshuf4i.w mask=0x77980000 +#0x77980000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvshuf4i.w xrD, xrJ, imm10_8 is op18_31=0x1de6 & xrD & xrJ & imm10_8 { + xrD = xvshuf4i.w(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvshuf4i.d; + +#lasx.txt xvshuf4i.d mask=0x779c0000 +#0x779c0000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvshuf4i.d xrD, xrJ, imm10_8 is op18_31=0x1de7 & xrD & xrJ & imm10_8 { + xrD = xvshuf4i.d(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvbitseli.b; + +#lasx.txt xvbitseli.b mask=0x77c40000 +#0x77c40000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvbitseli.b xrD, xrJ, imm10_8 is op18_31=0x1df1 & xrD & xrJ & imm10_8 { + xrD = xvbitseli.b(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvandi.b; + +#lasx.txt xvandi.b mask=0x77d00000 +#0x77d00000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvandi.b xrD, xrJ, imm10_8 is op18_31=0x1df4 & xrD & xrJ & imm10_8 { + xrD = xvandi.b(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvori.b; + +#lasx.txt xvori.b mask=0x77d40000 +#0x77d40000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvori.b xrD, xrJ, imm10_8 is op18_31=0x1df5 & xrD & xrJ & imm10_8 { + xrD = xvori.b(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvxori.b; + +#lasx.txt xvxori.b mask=0x77d80000 +#0x77d80000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvxori.b xrD, xrJ, imm10_8 is op18_31=0x1df6 & xrD & xrJ & imm10_8 { + xrD = xvxori.b(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvnori.b; + +#lasx.txt xvnori.b mask=0x77dc0000 +#0x77dc0000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvnori.b xrD, xrJ, imm10_8 is op18_31=0x1df7 & xrD & xrJ & imm10_8 { + xrD = xvnori.b(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvldi; + +#lasx.txt xvldi mask=0x77e00000 +#0x77e00000 0xfffc0000 x0:5,s5:13 ['xreg0_5_s0', 'simm5_13_s0'] +:xvldi xrD,simm5_13 is op18_31=0x1df8 & xrD & simm5_13 { + xrD = xvldi(xrD, simm5_13:$(REGSIZE)); +} + +define pcodeop xvpermi.w; + +#lasx.txt xvpermi.w mask=0x77e40000 +#0x77e40000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvpermi.w xrD, xrJ, imm10_8 is op18_31=0x1df9 & xrD & xrJ & imm10_8 { + xrD = xvpermi.w(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvpermi.d; + +#lasx.txt xvpermi.d mask=0x77e80000 +#0x77e80000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvpermi.d xrD, xrJ, imm10_8 is op18_31=0x1dfa & xrD & xrJ & imm10_8 { + xrD = xvpermi.d(xrD, xrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop xvpermi.q; + +#lasx.txt xvpermi.q mask=0x77ec0000 +#0x77ec0000 0xfffc0000 x0:5,x5:5,u10:8 ['xreg0_5_s0', 'xreg5_5_s0', 'imm10_8_s0'] +:xvpermi.q xrD, xrJ, imm10_8 is op18_31=0x1dfb & xrD & xrJ & imm10_8 { + xrD = xvpermi.q(xrD, xrJ, imm10_8:$(REGSIZE)); +} + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lbt.sinc b/Ghidra/Processors/Loongarch/data/languages/lbt.sinc new file mode 100644 index 0000000000..1e0ae9b313 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/lbt.sinc @@ -0,0 +1,1417 @@ +define pcodeop movgr2scr; + +#lbt.txt movgr2scr mask=0x00000800 [@lbt] +#0x00000800 0xfffffc1c cr0:2, r5:5 ['scr0_2_s0', 'reg5_5_s0'] +:movgr2scr lbtrD, RJ is op10_31=0x2 & op2_4=0x0 & lbtrD & RJ { + movgr2scr(lbtrD:1, RJ); +} + +define pcodeop movscr2gr; + +#lbt.txt movscr2gr mask=0x00000c00 [@lbt] +#0x00000c00 0xffffff80 r0:5,cr5:2 ['reg0_5_s0', 'scr5_2_s0'] +:movscr2gr RD, lbtrJ is op7_31=0x18 & RD & lbtrJ { + RD = movscr2gr(RD, lbtrJ:1); +} + +define pcodeop x86mttop; + +#lbt.txt x86mttop mask=0x00007000 [@lbt] +#0x00007000 0xffffff1f u5:3 ['imm5_3_s0'] +:x86mttop imm5_3 is op8_31=0x70 & op0_4=0x0 & imm5_3 { + x86mttop(imm5_3:$(REGSIZE)); +} + +define pcodeop x86mftop; + +#lbt.txt x86mftop mask=0x00007400 [@lbt] +#0x00007400 0xffffffe0 r0:5 ['reg0_5_s0'] +:x86mftop RD is op5_31=0x3a0 & RD { + RD = x86mftop(RD); +} + +define pcodeop setx86loope; + +#lbt.txt x86setloope mask=0x00007800 [@lbt, @orig_name=setx86loope] +#0x00007800 0xfffffc00 r0:5, r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:setx86loope RD, RJ is op10_31=0x1e & RD & RJ { + RD = setx86loope(RD, RJ); +} + +define pcodeop setx86loopne; + +#lbt.txt x86setloopne mask=0x00007c00 [@lbt, @orig_name=setx86loopne] +#0x00007c00 0xfffffc00 r0:5, r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:setx86loopne RD, RJ is op10_31=0x1f & RD & RJ { + RD = setx86loopne(RD, RJ); +} + +define pcodeop x86inc.b; + +#lbt.txt x86inc.b mask=0x00008000 [@lbt] +#0x00008000 0xfffffc1f r5:5 ['reg5_5_s0'] +:x86inc.b RJ is op10_31=0x20 & op0_4=0x0 & RJ { + RJ = x86inc.b(RJ); +} + +define pcodeop x86inc.h; + +#lbt.txt x86inc.h mask=0x00008001 [@lbt] +#0x00008001 0xfffffc1f r5:5 ['reg5_5_s0'] +:x86inc.h RJ is op10_31=0x20 & op0_4=0x1 & RJ { + RJ = x86inc.h(RJ); +} + +define pcodeop x86inc.w; + +#lbt.txt x86inc.w mask=0x00008002 [@lbt] +#0x00008002 0xfffffc1f r5:5 ['reg5_5_s0'] +:x86inc.w RJ is op10_31=0x20 & op0_4=0x2 & RJ { + RJ = x86inc.w(RJ); +} + +define pcodeop x86inc.d; + +#lbt.txt x86inc.d mask=0x00008003 [@lbt] +#0x00008003 0xfffffc1f r5:5 ['reg5_5_s0'] +:x86inc.d RJ is op10_31=0x20 & op0_4=0x3 & RJ { + RJ = x86inc.d(RJ); +} + +define pcodeop x86dec.b; + +#lbt.txt x86dec.b mask=0x00008004 [@lbt] +#0x00008004 0xfffffc1f r5:5 ['reg5_5_s0'] +:x86dec.b RJ is op10_31=0x20 & op0_4=0x4 & RJ { + RJ = x86dec.b(RJ); +} + +define pcodeop x86dec.h; + +#lbt.txt x86dec.h mask=0x00008005 [@lbt] +#0x00008005 0xfffffc1f r5:5 ['reg5_5_s0'] +:x86dec.h RJ is op10_31=0x20 & op0_4=0x5 & RJ { + RJ = x86dec.h(RJ); +} + +define pcodeop x86dec.w; + +#lbt.txt x86dec.w mask=0x00008006 [@lbt] +#0x00008006 0xfffffc1f r5:5 ['reg5_5_s0'] +:x86dec.w RJ is op10_31=0x20 & op0_4=0x6 & RJ { + RJ = x86dec.w(RJ); +} + +define pcodeop x86dec.d; + +#lbt.txt x86dec.d mask=0x00008007 [@lbt] +#0x00008007 0xfffffc1f r5:5 ['reg5_5_s0'] +:x86dec.d RJ is op10_31=0x20 & op0_4=0x7 & RJ { + RJ = x86dec.d(RJ); +} + +define pcodeop x86settm; + +#lbt.txt x86settm mask=0x00008008 [@lbt] +#0x00008008 0xffffffff +:x86settm is instword=0x00008008 { + x86settm(); +} + +define pcodeop x86inctop; + +#lbt.txt x86inctop mask=0x00008009 [@lbt] +#0x00008009 0xffffffff +:x86inctop is instword=0x00008009 { + x86inctop(); +} + +define pcodeop x86clrtm; + +#lbt.txt x86clrtm mask=0x00008028 [@lbt] +#0x00008028 0xffffffff +:x86clrtm is instword=0x00008028 { + x86clrtm(); +} + +define pcodeop x86dectop; + +#lbt.txt x86dectop mask=0x00008029 [@lbt] +#0x00008029 0xffffffff +:x86dectop is instword=0x00008029 { + x86dectop(); +} + +define pcodeop rotr.b; + +#lbt.txt rotr.b mask=0x001a0000 [@lbt] +#0x001a0000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:rotr.b RD, RJ, RK is op15_31=0x34 & RD & RJ & RK { + RD = rotr.b(RD, RJ, RK); +} + +define pcodeop rotr.h; + +#lbt.txt rotr.h mask=0x001a8000 [@lbt] +#0x001a8000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:rotr.h RD, RJ, RK is op15_31=0x35 & RD & RJ & RK { + RD = rotr.h(RD, RJ, RK); +} + +define pcodeop addu12i.w; + +#lbt.txt addu12i.w mask=0x00290000 [@lbt] +#0x00290000 0xffff8000 r0:5, r5:5, s10:5 ['reg0_5_s0', 'reg5_5_s0', 'simm10_5_s0'] +:addu12i.w RD, RJ, simm10_5 is op15_31=0x52 & RD & RJ & simm10_5 { + RD = addu12i.w(RD, RJ, simm10_5:$(REGSIZE)); +} + +define pcodeop addu12i.d; + +#lbt.txt addu12i.d mask=0x00298000 [@lbt] +#0x00298000 0xffff8000 r0:5, r5:5, s10:5 ['reg0_5_s0', 'reg5_5_s0', 'simm10_5_s0'] +:addu12i.d RD, RJ, simm10_5 is op15_31=0x53 & RD & RJ & simm10_5 { + RD = addu12i.d(RD, RJ, simm10_5:$(REGSIZE)); +} + +define pcodeop adc.b; + +#lbt.txt adc.b mask=0x00300000 [@lbt] +#0x00300000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:adc.b RD, RJ, RK is op15_31=0x60 & RD & RJ & RK { + RD = adc.b(RD, RJ, RK); +} + +define pcodeop adc.h; + +#lbt.txt adc.h mask=0x00308000 [@lbt] +#0x00308000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:adc.h RD, RJ, RK is op15_31=0x61 & RD & RJ & RK { + RD = adc.h(RD, RJ, RK); +} + +define pcodeop adc.w; + +#lbt.txt adc.w mask=0x00310000 [@lbt] +#0x00310000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:adc.w RD, RJ, RK is op15_31=0x62 & RD & RJ & RK { + RD = adc.w(RD, RJ, RK); +} + +define pcodeop adc.d; + +#lbt.txt adc.d mask=0x00318000 [@lbt] +#0x00318000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:adc.d RD, RJ, RK is op15_31=0x63 & RD & RJ & RK { + RD = adc.d(RD, RJ, RK); +} + +define pcodeop sbc.b; + +#lbt.txt sbc.b mask=0x00320000 [@lbt] +#0x00320000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sbc.b RD, RJ, RK is op15_31=0x64 & RD & RJ & RK { + RD = sbc.b(RD, RJ, RK); +} + +define pcodeop sbc.h; + +#lbt.txt sbc.h mask=0x00328000 [@lbt] +#0x00328000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sbc.h RD, RJ, RK is op15_31=0x65 & RD & RJ & RK { + RD = sbc.h(RD, RJ, RK); +} + +define pcodeop sbc.w; + +#lbt.txt sbc.w mask=0x00330000 [@lbt] +#0x00330000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sbc.w RD, RJ, RK is op15_31=0x66 & RD & RJ & RK { + RD = sbc.w(RD, RJ, RK); +} + +define pcodeop sbc.d; + +#lbt.txt sbc.d mask=0x00338000 [@lbt] +#0x00338000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:sbc.d RD, RJ, RK is op15_31=0x67 & RD & RJ & RK { + RD = sbc.d(RD, RJ, RK); +} + +define pcodeop rcr.b; + +#lbt.txt rcr.b mask=0x00340000 [@lbt] +#0x00340000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:rcr.b RD, RJ, RK is op15_31=0x68 & RD & RJ & RK { + RD = rcr.b(RD, RJ, RK); +} + +define pcodeop rcr.h; + +#lbt.txt rcr.h mask=0x00348000 [@lbt] +#0x00348000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:rcr.h RD, RJ, RK is op15_31=0x69 & RD & RJ & RK { + RD = rcr.h(RD, RJ, RK); +} + +define pcodeop rcr.w; + +#lbt.txt rcr.w mask=0x00350000 [@lbt] +#0x00350000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:rcr.w RD, RJ, RK is op15_31=0x6a & RD & RJ & RK { + RD = rcr.w(RD, RJ, RK); +} + +define pcodeop rcr.d; + +#lbt.txt rcr.d mask=0x00358000 [@lbt] +#0x00358000 0xffff8000 r0:5, r5:5, r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:rcr.d RD, RJ, RK is op15_31=0x6b & RD & RJ & RK { + RD = rcr.d(RD, RJ, RK); +} + +define pcodeop armmove; + +#lbt.txt armmove mask=0x00364000 [@lbt] +#0x00364000 0xffffc000 r0:5, r5:5,u10:4 ['reg0_5_s0', 'reg5_5_s0', 'imm10_4_s0'] +:armmove RD, RJ, imm10_4 is op14_31=0xd9 & RD & RJ & imm10_4 { + RD = armmove(RD, RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop setx86j; + +#lbt.txt x86setj mask=0x00368000 [@lbt, @orig_name=setx86j] +#0x00368000 0xffffc3e0 r0:5,u10:4 ['reg0_5_s0', 'imm10_4_s0'] +:setx86j RD, imm10_4 is op14_31=0xda & op5_9=0x0 & RD & imm10_4 { + RD = setx86j(RD, imm10_4:$(REGSIZE)); +} + +define pcodeop setarmj; + +#lbt.txt armsetj mask=0x0036c000 [@lbt, @orig_name=setarmj] +#0x0036c000 0xffffc3e0 r0:5,u10:4 ['reg0_5_s0', 'imm10_4_s0'] +:setarmj RD, imm10_4 is op14_31=0xdb & op5_9=0x0 & RD & imm10_4 { + RD = setarmj(RD, imm10_4:$(REGSIZE)); +} + +define pcodeop armadd.w; + +#lbt.txt armadd.w mask=0x00370010 [@lbt] +#0x00370010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armadd.w RJ, RK, imm0_4 is op15_31=0x6e & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armadd.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armsub.w; + +#lbt.txt armsub.w mask=0x00378010 [@lbt] +#0x00378010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armsub.w RJ, RK, imm0_4 is op15_31=0x6f & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armsub.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armadc.w; + +#lbt.txt armadc.w mask=0x00380010 [@lbt] +#0x00380010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armadc.w RJ, RK, imm0_4 is op15_31=0x70 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armadc.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armsbc.w; + +#lbt.txt armsbc.w mask=0x00388010 [@lbt] +#0x00388010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armsbc.w RJ, RK, imm0_4 is op15_31=0x71 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armsbc.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armand.w; + +#lbt.txt armand.w mask=0x00390010 [@lbt] +#0x00390010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armand.w RJ, RK, imm0_4 is op15_31=0x72 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armand.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armor.w; + +#lbt.txt armor.w mask=0x00398010 [@lbt] +#0x00398010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armor.w RJ, RK, imm0_4 is op15_31=0x73 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armor.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armxor.w; + +#lbt.txt armxor.w mask=0x003a0010 [@lbt] +#0x003a0010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armxor.w RJ, RK, imm0_4 is op15_31=0x74 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armxor.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armsll.w; + +#lbt.txt armsll.w mask=0x003a8010 [@lbt] +#0x003a8010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armsll.w RJ, RK, imm0_4 is op15_31=0x75 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armsll.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armsrl.w; + +#lbt.txt armsrl.w mask=0x003b0010 [@lbt] +#0x003b0010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armsrl.w RJ, RK, imm0_4 is op15_31=0x76 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armsrl.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armsra.w; + +#lbt.txt armsra.w mask=0x003b8010 [@lbt] +#0x003b8010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armsra.w RJ, RK, imm0_4 is op15_31=0x77 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armsra.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armrotr.w; + +#lbt.txt armrotr.w mask=0x003c0010 [@lbt] +#0x003c0010 0xffff8010 r5:5, r10:5,u0:4 ['reg5_5_s0', 'reg10_5_s0', 'imm0_4_s0'] +:armrotr.w RJ, RK, imm0_4 is op15_31=0x78 & op4_4=0x1 & RJ & RK & imm0_4 { + RJ = armrotr.w(RJ, RK, imm0_4:$(REGSIZE)); +} + +define pcodeop armslli.w; + +#lbt.txt armslli.w mask=0x003c8010 [@lbt, @orig_fmt=JUk5Ud4] +#0x003c8010 0xffff8010 r5:5,u10:5,u0:4 ['reg5_5_s0', 'imm10_5_s0', 'imm0_4_s0'] +:armslli.w RJ, imm0_4, imm10_5 is op15_31=0x79 & op4_4=0x1 & RJ & imm0_4 & imm10_5 { + RJ = armslli.w(RJ, imm0_4:$(REGSIZE), imm10_5:$(REGSIZE)); +} + +define pcodeop armsrli.w; + +#lbt.txt armsrli.w mask=0x003d0010 [@lbt, @orig_fmt=JUk5Ud4] +#0x003d0010 0xffff8010 r5:5,u10:5,u0:4 ['reg5_5_s0', 'imm10_5_s0', 'imm0_4_s0'] +:armsrli.w RJ, imm0_4, imm10_5 is op15_31=0x7a & op4_4=0x1 & RJ & imm0_4 & imm10_5 { + RJ = armsrli.w(RJ, imm0_4:$(REGSIZE), imm10_5:$(REGSIZE)); +} + +define pcodeop armsrai.w; + +#lbt.txt armsrai.w mask=0x003d8010 [@lbt, @orig_fmt=JUk5Ud4] +#0x003d8010 0xffff8010 r5:5,u10:5,u0:4 ['reg5_5_s0', 'imm10_5_s0', 'imm0_4_s0'] +:armsrai.w RJ, imm0_4, imm10_5 is op15_31=0x7b & op4_4=0x1 & RJ & imm0_4 & imm10_5 { + RJ = armsrai.w(RJ, imm0_4:$(REGSIZE), imm10_5:$(REGSIZE)); +} + +define pcodeop armrotri.w; + +#lbt.txt armrotri.w mask=0x003e0010 [@lbt, @orig_fmt=JUk5Ud4] +#0x003e0010 0xffff8010 r5:5,u10:5,u0:4 ['reg5_5_s0', 'imm10_5_s0', 'imm0_4_s0'] +:armrotri.w RJ, imm0_4, imm10_5 is op15_31=0x7c & op4_4=0x1 & RJ & imm0_4 & imm10_5 { + RJ = armrotri.w(RJ, imm0_4:$(REGSIZE), imm10_5:$(REGSIZE)); +} + +define pcodeop x86mul.b; + +#lbt.txt x86mul.b mask=0x003e8000 [@lbt] +#0x003e8000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86mul.b RJ, RK is op15_31=0x7d & op0_4=0x0 & RJ & RK { + RJ = x86mul.b(RJ, RK); +} + +define pcodeop x86mul.h; + +#lbt.txt x86mul.h mask=0x003e8001 [@lbt] +#0x003e8001 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86mul.h RJ, RK is op15_31=0x7d & op0_4=0x1 & RJ & RK { + RJ = x86mul.h(RJ, RK); +} + +define pcodeop x86mul.w; + +#lbt.txt x86mul.w mask=0x003e8002 [@lbt] +#0x003e8002 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86mul.w RJ, RK is op15_31=0x7d & op0_4=0x2 & RJ & RK { + RJ = x86mul.w(RJ, RK); +} + +define pcodeop x86mul.d; + +#lbt.txt x86mul.d mask=0x003e8003 [@lbt] +#0x003e8003 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86mul.d RJ, RK is op15_31=0x7d & op0_4=0x3 & RJ & RK { + RJ = x86mul.d(RJ, RK); +} + +define pcodeop x86mul.bu; + +#lbt.txt x86mul.bu mask=0x003e8004 [@lbt] +#0x003e8004 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86mul.bu RJ, RK is op15_31=0x7d & op0_4=0x4 & RJ & RK { + RJ = x86mul.bu(RJ, RK); +} + +define pcodeop x86mul.hu; + +#lbt.txt x86mul.hu mask=0x003e8005 [@lbt] +#0x003e8005 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86mul.hu RJ, RK is op15_31=0x7d & op0_4=0x5 & RJ & RK { + RJ = x86mul.hu(RJ, RK); +} + +define pcodeop x86mul.wu; + +#lbt.txt x86mul.wu mask=0x003e8006 [@lbt] +#0x003e8006 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86mul.wu RJ, RK is op15_31=0x7d & op0_4=0x6 & RJ & RK { + RJ = x86mul.wu(RJ, RK); +} + +define pcodeop x86mul.du; + +#lbt.txt x86mul.du mask=0x003e8007 [@lbt] +#0x003e8007 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86mul.du RJ, RK is op15_31=0x7d & op0_4=0x7 & RJ & RK { + RJ = x86mul.du(RJ, RK); +} + +define pcodeop x86add.wu; + +#lbt.txt x86add.wu mask=0x003f0000 [@lbt] +#0x003f0000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86add.wu RJ, RK is op15_31=0x7e & op0_4=0x0 & RJ & RK { + RJ = x86add.wu(RJ, RK); +} + +define pcodeop x86add.du; + +#lbt.txt x86add.du mask=0x003f0001 [@lbt] +#0x003f0001 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86add.du RJ, RK is op15_31=0x7e & op0_4=0x1 & RJ & RK { + RJ = x86add.du(RJ, RK); +} + +define pcodeop x86sub.wu; + +#lbt.txt x86sub.wu mask=0x003f0002 [@lbt] +#0x003f0002 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sub.wu RJ, RK is op15_31=0x7e & op0_4=0x2 & RJ & RK { + RJ = x86sub.wu(RJ, RK); +} + +define pcodeop x86sub.du; + +#lbt.txt x86sub.du mask=0x003f0003 [@lbt] +#0x003f0003 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sub.du RJ, RK is op15_31=0x7e & op0_4=0x3 & RJ & RK { + RJ = x86sub.du(RJ, RK); +} + +define pcodeop x86add.b; + +#lbt.txt x86add.b mask=0x003f0004 [@lbt] +#0x003f0004 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86add.b RJ, RK is op15_31=0x7e & op0_4=0x4 & RJ & RK { + RJ = x86add.b(RJ, RK); +} + +define pcodeop x86add.h; + +#lbt.txt x86add.h mask=0x003f0005 [@lbt] +#0x003f0005 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86add.h RJ, RK is op15_31=0x7e & op0_4=0x5 & RJ & RK { + RJ = x86add.h(RJ, RK); +} + +define pcodeop x86add.w; + +#lbt.txt x86add.w mask=0x003f0006 [@lbt] +#0x003f0006 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86add.w RJ, RK is op15_31=0x7e & op0_4=0x6 & RJ & RK { + RJ = x86add.w(RJ, RK); +} + +define pcodeop x86add.d; + +#lbt.txt x86add.d mask=0x003f0007 [@lbt] +#0x003f0007 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86add.d RJ, RK is op15_31=0x7e & op0_4=0x7 & RJ & RK { + RJ = x86add.d(RJ, RK); +} + +define pcodeop x86sub.b; + +#lbt.txt x86sub.b mask=0x003f0008 [@lbt] +#0x003f0008 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sub.b RJ, RK is op15_31=0x7e & op0_4=0x8 & RJ & RK { + RJ = x86sub.b(RJ, RK); +} + +define pcodeop x86sub.h; + +#lbt.txt x86sub.h mask=0x003f0009 [@lbt] +#0x003f0009 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sub.h RJ, RK is op15_31=0x7e & op0_4=0x9 & RJ & RK { + RJ = x86sub.h(RJ, RK); +} + +define pcodeop x86sub.w; + +#lbt.txt x86sub.w mask=0x003f000a [@lbt] +#0x003f000a 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sub.w RJ, RK is op15_31=0x7e & op0_4=0xa & RJ & RK { + RJ = x86sub.w(RJ, RK); +} + +define pcodeop x86sub.d; + +#lbt.txt x86sub.d mask=0x003f000b [@lbt] +#0x003f000b 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sub.d RJ, RK is op15_31=0x7e & op0_4=0xb & RJ & RK { + RJ = x86sub.d(RJ, RK); +} + +define pcodeop x86adc.b; + +#lbt.txt x86adc.b mask=0x003f000c [@lbt] +#0x003f000c 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86adc.b RJ, RK is op15_31=0x7e & op0_4=0xc & RJ & RK { + RJ = x86adc.b(RJ, RK); +} + +define pcodeop x86adc.h; + +#lbt.txt x86adc.h mask=0x003f000d [@lbt] +#0x003f000d 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86adc.h RJ, RK is op15_31=0x7e & op0_4=0xd & RJ & RK { + RJ = x86adc.h(RJ, RK); +} + +define pcodeop x86adc.w; + +#lbt.txt x86adc.w mask=0x003f000e [@lbt] +#0x003f000e 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86adc.w RJ, RK is op15_31=0x7e & op0_4=0xe & RJ & RK { + RJ = x86adc.w(RJ, RK); +} + +define pcodeop x86adc.d; + +#lbt.txt x86adc.d mask=0x003f000f [@lbt] +#0x003f000f 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86adc.d RJ, RK is op15_31=0x7e & op0_4=0xf & RJ & RK { + RJ = x86adc.d(RJ, RK); +} + +define pcodeop x86sbc.b; + +#lbt.txt x86sbc.b mask=0x003f0010 [@lbt] +#0x003f0010 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sbc.b RJ, RK is op15_31=0x7e & op0_4=0x10 & RJ & RK { + RJ = x86sbc.b(RJ, RK); +} + +define pcodeop x86sbc.h; + +#lbt.txt x86sbc.h mask=0x003f0011 [@lbt] +#0x003f0011 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sbc.h RJ, RK is op15_31=0x7e & op0_4=0x11 & RJ & RK { + RJ = x86sbc.h(RJ, RK); +} + +define pcodeop x86sbc.w; + +#lbt.txt x86sbc.w mask=0x003f0012 [@lbt] +#0x003f0012 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sbc.w RJ, RK is op15_31=0x7e & op0_4=0x12 & RJ & RK { + RJ = x86sbc.w(RJ, RK); +} + +define pcodeop x86sbc.d; + +#lbt.txt x86sbc.d mask=0x003f0013 [@lbt] +#0x003f0013 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sbc.d RJ, RK is op15_31=0x7e & op0_4=0x13 & RJ & RK { + RJ = x86sbc.d(RJ, RK); +} + +define pcodeop x86sll.b; + +#lbt.txt x86sll.b mask=0x003f0014 [@lbt] +#0x003f0014 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sll.b RJ, RK is op15_31=0x7e & op0_4=0x14 & RJ & RK { + RJ = x86sll.b(RJ, RK); +} + +define pcodeop x86sll.h; + +#lbt.txt x86sll.h mask=0x003f0015 [@lbt] +#0x003f0015 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sll.h RJ, RK is op15_31=0x7e & op0_4=0x15 & RJ & RK { + RJ = x86sll.h(RJ, RK); +} + +define pcodeop x86sll.w; + +#lbt.txt x86sll.w mask=0x003f0016 [@lbt] +#0x003f0016 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sll.w RJ, RK is op15_31=0x7e & op0_4=0x16 & RJ & RK { + RJ = x86sll.w(RJ, RK); +} + +define pcodeop x86sll.d; + +#lbt.txt x86sll.d mask=0x003f0017 [@lbt] +#0x003f0017 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sll.d RJ, RK is op15_31=0x7e & op0_4=0x17 & RJ & RK { + RJ = x86sll.d(RJ, RK); +} + +define pcodeop x86srl.b; + +#lbt.txt x86srl.b mask=0x003f0018 [@lbt] +#0x003f0018 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86srl.b RJ, RK is op15_31=0x7e & op0_4=0x18 & RJ & RK { + RJ = x86srl.b(RJ, RK); +} + +define pcodeop x86srl.h; + +#lbt.txt x86srl.h mask=0x003f0019 [@lbt] +#0x003f0019 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86srl.h RJ, RK is op15_31=0x7e & op0_4=0x19 & RJ & RK { + RJ = x86srl.h(RJ, RK); +} + +define pcodeop x86srl.w; + +#lbt.txt x86srl.w mask=0x003f001a [@lbt] +#0x003f001a 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86srl.w RJ, RK is op15_31=0x7e & op0_4=0x1a & RJ & RK { + RJ = x86srl.w(RJ, RK); +} + +define pcodeop x86srl.d; + +#lbt.txt x86srl.d mask=0x003f001b [@lbt] +#0x003f001b 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86srl.d RJ, RK is op15_31=0x7e & op0_4=0x1b & RJ & RK { + RJ = x86srl.d(RJ, RK); +} + +define pcodeop x86sra.b; + +#lbt.txt x86sra.b mask=0x003f001c [@lbt] +#0x003f001c 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sra.b RJ, RK is op15_31=0x7e & op0_4=0x1c & RJ & RK { + RJ = x86sra.b(RJ, RK); +} + +define pcodeop x86sra.h; + +#lbt.txt x86sra.h mask=0x003f001d [@lbt] +#0x003f001d 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sra.h RJ, RK is op15_31=0x7e & op0_4=0x1d & RJ & RK { + RJ = x86sra.h(RJ, RK); +} + +define pcodeop x86sra.w; + +#lbt.txt x86sra.w mask=0x003f001e [@lbt] +#0x003f001e 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sra.w RJ, RK is op15_31=0x7e & op0_4=0x1e & RJ & RK { + RJ = x86sra.w(RJ, RK); +} + +define pcodeop x86sra.d; + +#lbt.txt x86sra.d mask=0x003f001f [@lbt] +#0x003f001f 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86sra.d RJ, RK is op15_31=0x7e & op0_4=0x1f & RJ & RK { + RJ = x86sra.d(RJ, RK); +} + +define pcodeop x86rotr.b; + +#lbt.txt x86rotr.b mask=0x003f8000 [@lbt] +#0x003f8000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rotr.b RJ, RK is op15_31=0x7f & op0_4=0x0 & RJ & RK { + RJ = x86rotr.b(RJ, RK); +} + +define pcodeop x86rotr.h; + +#lbt.txt x86rotr.h mask=0x003f8001 [@lbt] +#0x003f8001 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rotr.h RJ, RK is op15_31=0x7f & op0_4=0x1 & RJ & RK { + RJ = x86rotr.h(RJ, RK); +} + +define pcodeop x86rotr.d; + +#lbt.txt x86rotr.d mask=0x003f8002 [@lbt] +#0x003f8002 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rotr.d RJ, RK is op15_31=0x7f & op0_4=0x2 & RJ & RK { + RJ = x86rotr.d(RJ, RK); +} + +define pcodeop x86rotr.w; + +#lbt.txt x86rotr.w mask=0x003f8003 [@lbt] +#0x003f8003 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rotr.w RJ, RK is op15_31=0x7f & op0_4=0x3 & RJ & RK { + RJ = x86rotr.w(RJ, RK); +} + +define pcodeop x86rotl.b; + +#lbt.txt x86rotl.b mask=0x003f8004 [@lbt] +#0x003f8004 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rotl.b RJ, RK is op15_31=0x7f & op0_4=0x4 & RJ & RK { + RJ = x86rotl.b(RJ, RK); +} + +define pcodeop x86rotl.h; + +#lbt.txt x86rotl.h mask=0x003f8005 [@lbt] +#0x003f8005 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rotl.h RJ, RK is op15_31=0x7f & op0_4=0x5 & RJ & RK { + RJ = x86rotl.h(RJ, RK); +} + +define pcodeop x86rotl.w; + +#lbt.txt x86rotl.w mask=0x003f8006 [@lbt] +#0x003f8006 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rotl.w RJ, RK is op15_31=0x7f & op0_4=0x6 & RJ & RK { + RJ = x86rotl.w(RJ, RK); +} + +define pcodeop x86rotl.d; + +#lbt.txt x86rotl.d mask=0x003f8007 [@lbt] +#0x003f8007 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rotl.d RJ, RK is op15_31=0x7f & op0_4=0x7 & RJ & RK { + RJ = x86rotl.d(RJ, RK); +} + +define pcodeop x86rcr.b; + +#lbt.txt x86rcr.b mask=0x003f8008 [@lbt] +#0x003f8008 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rcr.b RJ, RK is op15_31=0x7f & op0_4=0x8 & RJ & RK { + RJ = x86rcr.b(RJ, RK); +} + +define pcodeop x86rcr.h; + +#lbt.txt x86rcr.h mask=0x003f8009 [@lbt] +#0x003f8009 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rcr.h RJ, RK is op15_31=0x7f & op0_4=0x9 & RJ & RK { + RJ = x86rcr.h(RJ, RK); +} + +define pcodeop x86rcr.w; + +#lbt.txt x86rcr.w mask=0x003f800a [@lbt] +#0x003f800a 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rcr.w RJ, RK is op15_31=0x7f & op0_4=0xa & RJ & RK { + RJ = x86rcr.w(RJ, RK); +} + +define pcodeop x86rcr.d; + +#lbt.txt x86rcr.d mask=0x003f800b [@lbt] +#0x003f800b 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rcr.d RJ, RK is op15_31=0x7f & op0_4=0xb & RJ & RK { + RJ = x86rcr.d(RJ, RK); +} + +define pcodeop x86rcl.b; + +#lbt.txt x86rcl.b mask=0x003f800c [@lbt] +#0x003f800c 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rcl.b RJ, RK is op15_31=0x7f & op0_4=0xc & RJ & RK { + RJ = x86rcl.b(RJ, RK); +} + +define pcodeop x86rcl.h; + +#lbt.txt x86rcl.h mask=0x003f800d [@lbt] +#0x003f800d 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rcl.h RJ, RK is op15_31=0x7f & op0_4=0xd & RJ & RK { + RJ = x86rcl.h(RJ, RK); +} + +define pcodeop x86rcl.w; + +#lbt.txt x86rcl.w mask=0x003f800e [@lbt] +#0x003f800e 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rcl.w RJ, RK is op15_31=0x7f & op0_4=0xe & RJ & RK { + RJ = x86rcl.w(RJ, RK); +} + +define pcodeop x86rcl.d; + +#lbt.txt x86rcl.d mask=0x003f800f [@lbt] +#0x003f800f 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86rcl.d RJ, RK is op15_31=0x7f & op0_4=0xf & RJ & RK { + RJ = x86rcl.d(RJ, RK); +} + +define pcodeop x86and.b; + +#lbt.txt x86and.b mask=0x003f8010 [@lbt] +#0x003f8010 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86and.b RJ, RK is op15_31=0x7f & op0_4=0x10 & RJ & RK { + RJ = x86and.b(RJ, RK); +} + +define pcodeop x86and.h; + +#lbt.txt x86and.h mask=0x003f8011 [@lbt] +#0x003f8011 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86and.h RJ, RK is op15_31=0x7f & op0_4=0x11 & RJ & RK { + RJ = x86and.h(RJ, RK); +} + +define pcodeop x86and.w; + +#lbt.txt x86and.w mask=0x003f8012 [@lbt] +#0x003f8012 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86and.w RJ, RK is op15_31=0x7f & op0_4=0x12 & RJ & RK { + RJ = x86and.w(RJ, RK); +} + +define pcodeop x86and.d; + +#lbt.txt x86and.d mask=0x003f8013 [@lbt] +#0x003f8013 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86and.d RJ, RK is op15_31=0x7f & op0_4=0x13 & RJ & RK { + RJ = x86and.d(RJ, RK); +} + +define pcodeop x86or.b; + +#lbt.txt x86or.b mask=0x003f8014 [@lbt] +#0x003f8014 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86or.b RJ, RK is op15_31=0x7f & op0_4=0x14 & RJ & RK { + RJ = x86or.b(RJ, RK); +} + +define pcodeop x86or.h; + +#lbt.txt x86or.h mask=0x003f8015 [@lbt] +#0x003f8015 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86or.h RJ, RK is op15_31=0x7f & op0_4=0x15 & RJ & RK { + RJ = x86or.h(RJ, RK); +} + +define pcodeop x86or.w; + +#lbt.txt x86or.w mask=0x003f8016 [@lbt] +#0x003f8016 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86or.w RJ, RK is op15_31=0x7f & op0_4=0x16 & RJ & RK { + RJ = x86or.w(RJ, RK); +} + +define pcodeop x86or.d; + +#lbt.txt x86or.d mask=0x003f8017 [@lbt] +#0x003f8017 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86or.d RJ, RK is op15_31=0x7f & op0_4=0x17 & RJ & RK { + RJ = x86or.d(RJ, RK); +} + +define pcodeop x86xor.b; + +#lbt.txt x86xor.b mask=0x003f8018 [@lbt] +#0x003f8018 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86xor.b RJ, RK is op15_31=0x7f & op0_4=0x18 & RJ & RK { + RJ = x86xor.b(RJ, RK); +} + +define pcodeop x86xor.h; + +#lbt.txt x86xor.h mask=0x003f8019 [@lbt] +#0x003f8019 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86xor.h RJ, RK is op15_31=0x7f & op0_4=0x19 & RJ & RK { + RJ = x86xor.h(RJ, RK); +} + +define pcodeop x86xor.w; + +#lbt.txt x86xor.w mask=0x003f801a [@lbt] +#0x003f801a 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86xor.w RJ, RK is op15_31=0x7f & op0_4=0x1a & RJ & RK { + RJ = x86xor.w(RJ, RK); +} + +define pcodeop x86xor.d; + +#lbt.txt x86xor.d mask=0x003f801b [@lbt] +#0x003f801b 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] +:x86xor.d RJ, RK is op15_31=0x7f & op0_4=0x1b & RJ & RK { + RJ = x86xor.d(RJ, RK); +} + +define pcodeop armnot.w; + +#lbt.txt armnot.w mask=0x003fc01c [@lbt] +#0x003fc01c 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:armnot.w RJ, imm10_4 is op14_31=0xff & op0_4=0x1c & RJ & imm10_4 { + RJ = armnot.w(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop armmov.w; + +#lbt.txt armmov.w mask=0x003fc01d [@lbt] +#0x003fc01d 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:armmov.w RJ, imm10_4 is op14_31=0xff & op0_4=0x1d & RJ & imm10_4 { + RJ = armmov.w(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop armmov.d; + +#lbt.txt armmov.d mask=0x003fc01e [@lbt] +#0x003fc01e 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:armmov.d RJ, imm10_4 is op14_31=0xff & op0_4=0x1e & RJ & imm10_4 { + RJ = armmov.d(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop armrrx.w; + +#lbt.txt armrrx.w mask=0x003fc01f [@lbt] +#0x003fc01f 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:armrrx.w RJ, imm10_4 is op14_31=0xff & op0_4=0x1f & RJ & imm10_4 { + RJ = armrrx.w(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop rotri.b; + +#lbt.txt rotri.b mask=0x004c2000 [@lbt] +#0x004c2000 0xffffe000 r0:5, r5:5,u10:3 ['reg0_5_s0', 'reg5_5_s0', 'imm10_3_s0'] +:rotri.b RD, RJ, imm10_3 is op13_31=0x261 & RD & RJ & imm10_3 { + RD = rotri.b(RD, RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop rotri.h; + +#lbt.txt rotri.h mask=0x004c4000 [@lbt] +#0x004c4000 0xffffc000 r0:5, r5:5,u10:4 ['reg0_5_s0', 'reg5_5_s0', 'imm10_4_s0'] +:rotri.h RD, RJ, imm10_4 is op14_31=0x131 & RD & RJ & imm10_4 { + RD = rotri.h(RD, RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop rcri.b; + +#lbt.txt rcri.b mask=0x00502000 [@lbt] +#0x00502000 0xffffe000 r0:5, r5:5,u10:3 ['reg0_5_s0', 'reg5_5_s0', 'imm10_3_s0'] +:rcri.b RD, RJ, imm10_3 is op13_31=0x281 & RD & RJ & imm10_3 { + RD = rcri.b(RD, RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop rcri.h; + +#lbt.txt rcri.h mask=0x00504000 [@lbt] +#0x00504000 0xffffc000 r0:5, r5:5,u10:4 ['reg0_5_s0', 'reg5_5_s0', 'imm10_4_s0'] +:rcri.h RD, RJ, imm10_4 is op14_31=0x141 & RD & RJ & imm10_4 { + RD = rcri.h(RD, RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop rcri.w; + +#lbt.txt rcri.w mask=0x00508000 [@lbt] +#0x00508000 0xffff8000 r0:5, r5:5,u10:5 ['reg0_5_s0', 'reg5_5_s0', 'imm10_5_s0'] +:rcri.w RD, RJ, imm10_5 is op15_31=0xa1 & RD & RJ & imm10_5 { + RD = rcri.w(RD, RJ, imm10_5:$(REGSIZE)); +} + +define pcodeop rcri.d; + +#lbt.txt rcri.d mask=0x00510000 [@lbt] +#0x00510000 0xffff0000 r0:5, r5:5,u10:6 ['reg0_5_s0', 'reg5_5_s0', 'imm10_6_s0'] +:rcri.d RD, RJ, imm10_6 is op16_31=0x51 & RD & RJ & imm10_6 { + RD = rcri.d(RD, RJ, imm10_6:$(REGSIZE)); +} + +define pcodeop x86slli.b; + +#lbt.txt x86slli.b mask=0x00542000 [@lbt] +#0x00542000 0xffffe01f r5:5,u10:3 ['reg5_5_s0', 'imm10_3_s0'] +:x86slli.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x0 & RJ & imm10_3 { + RJ = x86slli.b(RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop x86srli.b; + +#lbt.txt x86srli.b mask=0x00542004 [@lbt] +#0x00542004 0xffffe01f r5:5,u10:3 ['reg5_5_s0', 'imm10_3_s0'] +:x86srli.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x4 & RJ & imm10_3 { + RJ = x86srli.b(RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop x86srai.b; + +#lbt.txt x86srai.b mask=0x00542008 [@lbt] +#0x00542008 0xffffe01f r5:5,u10:3 ['reg5_5_s0', 'imm10_3_s0'] +:x86srai.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x8 & RJ & imm10_3 { + RJ = x86srai.b(RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop x86rotri.b; + +#lbt.txt x86rotri.b mask=0x0054200c [@lbt] +#0x0054200c 0xffffe01f r5:5,u10:3 ['reg5_5_s0', 'imm10_3_s0'] +:x86rotri.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0xc & RJ & imm10_3 { + RJ = x86rotri.b(RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop x86rcri.b; + +#lbt.txt x86rcri.b mask=0x00542010 [@lbt] +#0x00542010 0xffffe01f r5:5,u10:3 ['reg5_5_s0', 'imm10_3_s0'] +:x86rcri.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x10 & RJ & imm10_3 { + RJ = x86rcri.b(RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop x86rotli.b; + +#lbt.txt x86rotli.b mask=0x00542014 [@lbt] +#0x00542014 0xffffe01f r5:5,u10:3 ['reg5_5_s0', 'imm10_3_s0'] +:x86rotli.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x14 & RJ & imm10_3 { + RJ = x86rotli.b(RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop x86rcli.b; + +#lbt.txt x86rcli.b mask=0x00542018 [@lbt] +#0x00542018 0xffffe01f r5:5,u10:3 ['reg5_5_s0', 'imm10_3_s0'] +:x86rcli.b RJ, imm10_3 is op13_31=0x2a1 & op0_4=0x18 & RJ & imm10_3 { + RJ = x86rcli.b(RJ, imm10_3:$(REGSIZE)); +} + +define pcodeop x86slli.h; + +#lbt.txt x86slli.h mask=0x00544001 [@lbt] +#0x00544001 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:x86slli.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x1 & RJ & imm10_4 { + RJ = x86slli.h(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop x86srli.h; + +#lbt.txt x86srli.h mask=0x00544005 [@lbt] +#0x00544005 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:x86srli.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x5 & RJ & imm10_4 { + RJ = x86srli.h(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop x86srai.h; + +#lbt.txt x86srai.h mask=0x00544009 [@lbt] +#0x00544009 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:x86srai.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x9 & RJ & imm10_4 { + RJ = x86srai.h(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop x86rotri.h; + +#lbt.txt x86rotri.h mask=0x0054400d [@lbt] +#0x0054400d 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:x86rotri.h RJ, imm10_4 is op14_31=0x151 & op0_4=0xd & RJ & imm10_4 { + RJ = x86rotri.h(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop x86rcri.h; + +#lbt.txt x86rcri.h mask=0x00544011 [@lbt] +#0x00544011 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:x86rcri.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x11 & RJ & imm10_4 { + RJ = x86rcri.h(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop x86rotli.h; + +#lbt.txt x86rotli.h mask=0x00544015 [@lbt] +#0x00544015 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:x86rotli.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x15 & RJ & imm10_4 { + RJ = x86rotli.h(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop x86rcli.h; + +#lbt.txt x86rcli.h mask=0x00544019 [@lbt] +#0x00544019 0xffffc01f r5:5,u10:4 ['reg5_5_s0', 'imm10_4_s0'] +:x86rcli.h RJ, imm10_4 is op14_31=0x151 & op0_4=0x19 & RJ & imm10_4 { + RJ = x86rcli.h(RJ, imm10_4:$(REGSIZE)); +} + +define pcodeop x86slli.w; + +#lbt.txt x86slli.w mask=0x00548002 [@lbt] +#0x00548002 0xffff801f r5:5,u10:5 ['reg5_5_s0', 'imm10_5_s0'] +:x86slli.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x2 & RJ & imm10_5 { + RJ = x86slli.w(RJ, imm10_5:$(REGSIZE)); +} + +define pcodeop x86srli.w; + +#lbt.txt x86srli.w mask=0x00548006 [@lbt] +#0x00548006 0xffff801f r5:5,u10:5 ['reg5_5_s0', 'imm10_5_s0'] +:x86srli.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x6 & RJ & imm10_5 { + RJ = x86srli.w(RJ, imm10_5:$(REGSIZE)); +} + +define pcodeop x86srai.w; + +#lbt.txt x86srai.w mask=0x0054800a [@lbt] +#0x0054800a 0xffff801f r5:5,u10:5 ['reg5_5_s0', 'imm10_5_s0'] +:x86srai.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0xa & RJ & imm10_5 { + RJ = x86srai.w(RJ, imm10_5:$(REGSIZE)); +} + +define pcodeop x86rotri.w; + +#lbt.txt x86rotri.w mask=0x0054800e [@lbt] +#0x0054800e 0xffff801f r5:5,u10:5 ['reg5_5_s0', 'imm10_5_s0'] +:x86rotri.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0xe & RJ & imm10_5 { + RJ = x86rotri.w(RJ, imm10_5:$(REGSIZE)); +} + +define pcodeop x86rcri.w; + +#lbt.txt x86rcri.w mask=0x00548012 [@lbt] +#0x00548012 0xffff801f r5:5,u10:5 ['reg5_5_s0', 'imm10_5_s0'] +:x86rcri.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x12 & RJ & imm10_5 { + RJ = x86rcri.w(RJ, imm10_5:$(REGSIZE)); +} + +define pcodeop x86rotli.w; + +#lbt.txt x86rotli.w mask=0x00548016 [@lbt] +#0x00548016 0xffff801f r5:5,u10:5 ['reg5_5_s0', 'imm10_5_s0'] +:x86rotli.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x16 & RJ & imm10_5 { + RJ = x86rotli.w(RJ, imm10_5:$(REGSIZE)); +} + +define pcodeop x86rcli.w; + +#lbt.txt x86rcli.w mask=0x0054801a [@lbt] +#0x0054801a 0xffff801f r5:5,u10:5 ['reg5_5_s0', 'imm10_5_s0'] +:x86rcli.w RJ, imm10_5 is op15_31=0xa9 & op0_4=0x1a & RJ & imm10_5 { + RJ = x86rcli.w(RJ, imm10_5:$(REGSIZE)); +} + +define pcodeop x86slli.d; + +#lbt.txt x86slli.d mask=0x00550003 [@lbt] +#0x00550003 0xffff001f r5:5,u10:6 ['reg5_5_s0', 'imm10_6_s0'] +:x86slli.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x3 & RJ & imm10_6 { + RJ = x86slli.d(RJ, imm10_6:$(REGSIZE)); +} + +define pcodeop x86srli.d; + +#lbt.txt x86srli.d mask=0x00550007 [@lbt] +#0x00550007 0xffff001f r5:5,u10:6 ['reg5_5_s0', 'imm10_6_s0'] +:x86srli.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x7 & RJ & imm10_6 { + RJ = x86srli.d(RJ, imm10_6:$(REGSIZE)); +} + +define pcodeop x86srai.d; + +#lbt.txt x86srai.d mask=0x0055000b [@lbt] +#0x0055000b 0xffff001f r5:5,u10:6 ['reg5_5_s0', 'imm10_6_s0'] +:x86srai.d RJ, imm10_6 is op16_31=0x55 & op0_4=0xb & RJ & imm10_6 { + RJ = x86srai.d(RJ, imm10_6:$(REGSIZE)); +} + +define pcodeop x86rotri.d; + +#lbt.txt x86rotri.d mask=0x0055000f [@lbt] +#0x0055000f 0xffff001f r5:5,u10:6 ['reg5_5_s0', 'imm10_6_s0'] +:x86rotri.d RJ, imm10_6 is op16_31=0x55 & op0_4=0xf & RJ & imm10_6 { + RJ = x86rotri.d(RJ, imm10_6:$(REGSIZE)); +} + +define pcodeop x86rcri.d; + +#lbt.txt x86rcri.d mask=0x00550013 [@lbt] +#0x00550013 0xffff001f r5:5,u10:6 ['reg5_5_s0', 'imm10_6_s0'] +:x86rcri.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x13 & RJ & imm10_6 { + RJ = x86rcri.d(RJ, imm10_6:$(REGSIZE)); +} + +define pcodeop x86rotli.d; + +#lbt.txt x86rotli.d mask=0x00550017 [@lbt] +#0x00550017 0xffff001f r5:5,u10:6 ['reg5_5_s0', 'imm10_6_s0'] +:x86rotli.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x17 & RJ & imm10_6 { + RJ = x86rotli.d(RJ, imm10_6:$(REGSIZE)); +} + +define pcodeop x86rcli.d; + +#lbt.txt x86rcli.d mask=0x0055001b [@lbt] +#0x0055001b 0xffff001f r5:5,u10:6 ['reg5_5_s0', 'imm10_6_s0'] +:x86rcli.d RJ, imm10_6 is op16_31=0x55 & op0_4=0x1b & RJ & imm10_6 { + RJ = x86rcli.d(RJ, imm10_6:$(REGSIZE)); +} + +define pcodeop x86settag; + +#lbt.txt x86settag mask=0x00580000 [@lbt] +#0x00580000 0xfffc0000 r0:5,u5:5,u10:8 ['reg0_5_s0', 'imm5_5_s0', 'imm10_8_s0'] +:x86settag RD, imm5_5, imm10_8 is op18_31=0x16 & RD & imm5_5 & imm10_8 { + RD = x86settag(RD, imm5_5:$(REGSIZE), imm10_8:$(REGSIZE)); +} + +define pcodeop x86mfflag; + +#lbt.txt x86mfflag mask=0x005c0000 [@lbt] +#0x005c0000 0xfffc03e0 r0:5,u10:8 ['reg0_5_s0', 'imm10_8_s0'] +:x86mfflag RD, imm10_8 is op18_31=0x17 & op5_9=0x0 & RD & imm10_8 { + RD = x86mfflag(RD, imm10_8:$(REGSIZE)); +} + +define pcodeop x86mtflag; + +#lbt.txt x86mtflag mask=0x005c0020 [@lbt] +#0x005c0020 0xfffc03e0 r0:5,u10:8 ['reg0_5_s0', 'imm10_8_s0'] +:x86mtflag RD, imm10_8 is op18_31=0x17 & op5_9=0x1 & RD & imm10_8 { + RD = x86mtflag(RD, imm10_8:$(REGSIZE)); +} + +define pcodeop armmfflag; + +#lbt.txt armmfflag mask=0x005c0040 [@lbt] +#0x005c0040 0xfffc03e0 r0:5,u10:8 ['reg0_5_s0', 'imm10_8_s0'] +:armmfflag RD, imm10_8 is op18_31=0x17 & op5_9=0x2 & RD & imm10_8 { + RD = armmfflag(RD, imm10_8:$(REGSIZE)); +} + +define pcodeop armmtflag; + +#lbt.txt armmtflag mask=0x005c0060 [@lbt] +#0x005c0060 0xfffc03e0 r0:5,u10:8 ['reg0_5_s0', 'imm10_8_s0'] +:armmtflag RD, imm10_8 is op18_31=0x17 & op5_9=0x3 & RD & imm10_8 { + RD = armmtflag(RD, imm10_8:$(REGSIZE)); +} + +define pcodeop fcvt.ld.d; + +#lbt.txt fcvt.ld.d mask=0x0114e000 [@lbt] +#0x0114e000 0xfffffc00 f0:5,f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fcvt.ld.d drD,drJ is op10_31=0x4538 & drD & drJ { + drD = fcvt.ld.d(drD, drJ); +} + +define pcodeop fcvt.ud.d; + +#lbt.txt fcvt.ud.d mask=0x0114e400 [@lbt] +#0x0114e400 0xfffffc00 f0:5,f5:5 ['freg0_5_s0', 'freg5_5_s0'] +:fcvt.ud.d drD,drJ is op10_31=0x4539 & drD & drJ { + drD = fcvt.ud.d(drD, drJ); +} + +define pcodeop fcvt.d.ld; + +#lbt.txt fcvt.d.ld mask=0x01150000 [@lbt] +#0x01150000 0xffff8000 f0:5,f5:5,f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] +:fcvt.d.ld drD,drJ,drK is op16_31=0x115 & drD & drJ & drK { + drD = fcvt.d.ld(drD, drJ, drK); +} + +define pcodeop ldl.w; + +#lbt.txt ldl.w mask=0x2e000000 [@lbt] +#0x2e000000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:ldl.w RD, RJ, simm10_12 is op22_31=0xb8 & RD & RJ & simm10_12 { + RD = ldl.w(RD, RJ, simm10_12:$(REGSIZE)); +} + +define pcodeop ldr.w; + +#lbt.txt ldr.w mask=0x2e400000 [@lbt] +#0x2e400000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:ldr.w RD, RJ, simm10_12 is op22_31=0xb9 & RD & RJ & simm10_12 { + RD = ldr.w(RD, RJ, simm10_12:$(REGSIZE)); +} + +define pcodeop ldl.d; + +#lbt.txt ldl.d mask=0x2e800000 [@lbt] +#0x2e800000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:ldl.d RD, RJ, simm10_12 is op22_31=0xba & RD & RJ & simm10_12 { + RD = ldl.d(RD, RJ, simm10_12:$(REGSIZE)); +} + +define pcodeop ldr.d; + +#lbt.txt ldr.d mask=0x2ec00000 [@lbt] +#0x2ec00000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:ldr.d RD, RJ, simm10_12 is op22_31=0xbb & RD & RJ & simm10_12 { + RD = ldr.d(RD, RJ, simm10_12:$(REGSIZE)); +} + +define pcodeop stl.w; + +#lbt.txt stl.w mask=0x2f000000 [@lbt] +#0x2f000000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:stl.w RD, RJ, simm10_12 is op22_31=0xbc & RD & RJ & simm10_12 { + RD = stl.w(RD, RJ, simm10_12:$(REGSIZE)); +} + +define pcodeop str.w; + +#lbt.txt str.w mask=0x2f400000 [@lbt] +#0x2f400000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:str.w RD, RJ, simm10_12 is op22_31=0xbd & RD & RJ & simm10_12 { + RD = str.w(RD, RJ, simm10_12:$(REGSIZE)); +} + +define pcodeop stl.d; + +#lbt.txt stl.d mask=0x2f800000 [@lbt] +#0x2f800000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:stl.d RD, RJ, simm10_12 is op22_31=0xbe & RD & RJ & simm10_12 { + RD = stl.d(RD, RJ, simm10_12:$(REGSIZE)); +} + +define pcodeop str.d; + +#lbt.txt str.d mask=0x2fc00000 [@lbt] +#0x2fc00000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:str.d RD, RJ, simm10_12 is op22_31=0xbf & RD & RJ & simm10_12 { + RD = str.d(RD, RJ, simm10_12:$(REGSIZE)); +} + +define pcodeop jiscr0; + +#lbt.txt jiscr0 mask=0x48000200 [@lbt, @orig_fmt=Sd5k16ps2] +#0x48000200 0xfc0003e0 s0:5|10:16<<2 ['simm0_0_s2'] +:jiscr0 Rel26 is op26_31=0x12 & op5_9=0x10 & Rel26 { + jiscr0(Rel26); +} + +define pcodeop jiscr1; + +#lbt.txt jiscr1 mask=0x48000300 [@lbt, @orig_fmt=Sd5k16ps2] +#0x48000300 0xfc0003e0 s0:5|10:16<<2 ['simm0_0_s2'] +:jiscr1 Rel26 is op26_31=0x12 & op5_9=0x18 & off16 & Rel26 { + jiscr1(Rel26); +} + + diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs b/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs new file mode 100644 index 0000000000..656cf52644 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs @@ -0,0 +1,60 @@ + + + + + Loongson Architecture + + + + + + Loongson Architecture + + + + + + + Loongson Architecture + + + + + Loongson Architecture + + + + + \ No newline at end of file diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch.opinion b/Ghidra/Processors/Loongarch/data/languages/loongarch.opinion new file mode 100644 index 0000000000..ad603eb9fa --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch.opinion @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32.pspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32.pspec new file mode 100644 index 0000000000..6d69eb0db1 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32.pspec @@ -0,0 +1,10 @@ + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec new file mode 100644 index 0000000000..02232078e4 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec @@ -0,0 +1,14 @@ +@define REGSIZE 4 +@define FREGSIZE 4 +@define ADDRSIZE 4 +@include "loongarch_main.sinc" +@include "Loongarch32_Instructions.sinc" +@include "privileged-32.sinc" +@include "float_Instructions.sinc" +@include "double_Instructions.sinc" + + +@include "lasx.sinc" +@include "lbt.sinc" +@include "lsx.sinc" +@include "lvz.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec new file mode 100644 index 0000000000..ef017d2e39 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec @@ -0,0 +1,13 @@ +@define REGSIZE 4 +@define FREGSIZE 8 +@define ADDRSIZE 4 +@include "loongarch_main.sinc" +@include "Loongarch32_Instructions.sinc" +@include "privileged-32.sinc" +@include "float_Instructions.sinc" +@include "double_Instructions.sinc" + +#@include "lasx.sinc" +#@include "lbt.sinc" +#@include "lsx.sinc" +#@include "lvz.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64.pspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64.pspec new file mode 100644 index 0000000000..6d69eb0db1 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64.pspec @@ -0,0 +1,10 @@ + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec new file mode 100644 index 0000000000..5d5ea02720 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec @@ -0,0 +1,21 @@ +@define LA64 "" + +@define REGSIZE 8 +@define FREGSIZE 4 +@define ADDRSIZE 8 +@include "loongarch_main.sinc" +@include "Loongarch32_Instructions.sinc" +@include "Loongarch64_Instructions.sinc" +@include "privileged-32.sinc" +@include "privileged-64.sinc" +@include "float_Instructions.sinc" +@include "double_Instructions.sinc" + + +@include "lasx.sinc" +@include "lbt.sinc" +@include "lsx.sinc" +@include "lvz.sinc" + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec new file mode 100644 index 0000000000..627012062e --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec @@ -0,0 +1,17 @@ +@define LA64 "" + +@define REGSIZE 8 +@define FREGSIZE 8 +@define ADDRSIZE 8 +@include "loongarch_main.sinc" +@include "Loongarch32_Instructions.sinc" +@include "Loongarch64_Instructions.sinc" +@include "privileged-32.sinc" +@include "privileged-64.sinc" +@include "float_Instructions.sinc" +@include "double_Instructions.sinc" + +@include "lasx.sinc" +@include "lbt.sinc" +@include "lsx.sinc" +@include "lvz.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc new file mode 100644 index 0000000000..e7991ef90f --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc @@ -0,0 +1,564 @@ + +define endian=little; + +define alignment=1; + +define space ram type=ram_space size=$(REGSIZE) default; +define space register type=register_space size=4; + +define register offset=0x0 size=8 [ + pc scr0 scr1 scr2 scr3 +]; + +define register offset=0x40 size=1 [ + fcc0 fcc1 fcc2 fcc3 fcc4 fcc5 fcc6 fcc7 +]; + +define register offset=0x48 size=4 [ + fcsr +]; + +# ABI names: +# "$zero", "$ra", "$tp", "$sp", "$a0", "$a1", "$a2", "$a3", +# "$a4", "$a5", "$a6", "$a7", "$t0", "$t1", "$t2", "$t3", +# "$t4", "$t5", "$t6", "$t7", "$t8", "$x", "$fp", "$s0", +# "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8", + +# GPR General Purpose Registers +define register offset=0x100 size=$(REGSIZE) [ + zero ra tp sp a0 a1 a2 a3 + a4 a5 a6 a7 t0 t1 t2 t3 + t4 t5 t6 t7 t8 r21 fp s0 + s1 s2 s3 s4 s5 s6 s7 s8 +]; + +@ifdef LA64 + +define register offset=0x100 size=4 [ + r0_lo r0_hi ra_lo ra_hi tp_lo tp_hi sp_lo sp_hi + a0_lo a0_hi a1_lo a1_hi a2_lo a2_hi a3_lo a3_hi + a4_lo a4_hi a5_lo a5_hi a6_lo a6_hi a7_lo a7_hi + t0_lo t0_hi t1_lo t1_hi t2_lo t2_hi t3_lo t3_hi + t4_lo t4_hi t5_lo t5_hi t6_lo t6_hi t7_lo t7_hi + t8_lo t8_hi r21_lo r21_hi fp_lo fp_hi s0_lo s0_hi + s1_lo s1_hi s2_lo s2_hi s3_lo s3_hi s4_lo s4_hi + s5_lo s5_hi s6_lo s6_hi s7_lo s7_hi s8_lo s8_hi +]; + +@endif + +# Floating Point registers (either 32- or 64-bit) +@if FREGSIZE == "4" +define register offset=0x1000 size=4 [ + fa0 _ _ _ _ _ _ _ fa1 _ _ _ _ _ _ _ + fa2 _ _ _ _ _ _ _ fa3 _ _ _ _ _ _ _ + fa4 _ _ _ _ _ _ _ fa5 _ _ _ _ _ _ _ + fa6 _ _ _ _ _ _ _ fa7 _ _ _ _ _ _ _ + ft0 _ _ _ _ _ _ _ ft1 _ _ _ _ _ _ _ + ft2 _ _ _ _ _ _ _ ft3 _ _ _ _ _ _ _ + ft4 _ _ _ _ _ _ _ ft5 _ _ _ _ _ _ _ + ft6 _ _ _ _ _ _ _ ft7 _ _ _ _ _ _ _ + ft8 _ _ _ _ _ _ _ ft9 _ _ _ _ _ _ _ + ft10 _ _ _ _ _ _ _ ft11 _ _ _ _ _ _ _ + ft12 _ _ _ _ _ _ _ ft13 _ _ _ _ _ _ _ + ft14 _ _ _ _ _ _ _ ft15 _ _ _ _ _ _ _ + fs0 _ _ _ _ _ _ _ fs1 _ _ _ _ _ _ _ + fs2 _ _ _ _ _ _ _ fs3 _ _ _ _ _ _ _ + fs4 _ _ _ _ _ _ _ fs5 _ _ _ _ _ _ _ + fs6 _ _ _ _ _ _ _ fs7 _ _ _ _ _ _ _ +]; + +define register offset=0x1000 size=8 [ + fa0_1 _ _ _ fa2_3 _ _ _ + fa4_5 _ _ _ fa6_7 _ _ _ + ft8_9 _ _ _ ft10_11 _ _ _ + ft12_13 _ _ _ ft14_15 _ _ _ + ft16_17 _ _ _ ft18_19 _ _ _ + ft20_21 _ _ _ ft22_23 _ _ _ + fs24_25 _ _ _ fs26_27 _ _ _ + fs28_29 _ _ _ fs30_31 _ _ _ +]; + +@else + +define register offset=0x1000 size=4 [ + fa0_lo _ _ _ _ _ _ _ fa1_lo _ _ _ _ _ _ _ + fa2_lo _ _ _ _ _ _ _ fa3_lo _ _ _ _ _ _ _ + fa4_lo _ _ _ _ _ _ _ fa5_lo _ _ _ _ _ _ _ + fa6_lo _ _ _ _ _ _ _ fa7_lo _ _ _ _ _ _ _ + ft0_lo _ _ _ _ _ _ _ ft1_lo _ _ _ _ _ _ _ + ft2_lo _ _ _ _ _ _ _ ft3_lo _ _ _ _ _ _ _ + ft4_lo _ _ _ _ _ _ _ ft5_lo _ _ _ _ _ _ _ + ft6_lo _ _ _ _ _ _ _ ft7_lo _ _ _ _ _ _ _ + ft8_lo _ _ _ _ _ _ _ ft9_lo _ _ _ _ _ _ _ + ft10_lo _ _ _ _ _ _ _ ft11_lo _ _ _ _ _ _ _ + ft12_lo _ _ _ _ _ _ _ ft13_lo _ _ _ _ _ _ _ + ft14_lo _ _ _ _ _ _ _ ft15_lo _ _ _ _ _ _ _ + fs0_lo _ _ _ _ _ _ _ fs1_lo _ _ _ _ _ _ _ + fs2_lo _ _ _ _ _ _ _ fs3_lo _ _ _ _ _ _ _ + fs4_lo _ _ _ _ _ _ _ fs5_lo _ _ _ _ _ _ _ + fs6_lo _ _ _ _ _ _ _ fs7_lo _ _ _ _ _ _ _ +]; + +define register offset=0x1000 size=8 [ + fa0 _ _ _ fa1 _ _ _ fa2 _ _ _ fa3 _ _ _ + fa4 _ _ _ fa5 _ _ _ fa6 _ _ _ fa7 _ _ _ + ft0 _ _ _ ft1 _ _ _ ft2 _ _ _ ft3 _ _ _ + ft4 _ _ _ ft5 _ _ _ ft6 _ _ _ ft7 _ _ _ + ft8 _ _ _ ft9 _ _ _ ft10 _ _ _ ft11 _ _ _ + ft12 _ _ _ ft13 _ _ _ ft14 _ _ _ ft15 _ _ _ + fs0 _ _ _ fs1 _ _ _ fs2 _ _ _ fs3 _ _ _ + fs4 _ _ _ fs5 _ _ _ fs6 _ _ _ fs7 _ _ _ +]; + +@endif #FREGSIZE == 32 + +# SIMD eXtension 256-bit registers (lsx) +# overlaps the floating point registers above +define register offset=0x1000 size=16 [ + v0 _ v1 _ v2 _ v3 _ v4 _ v5 _ v6 _ v7 _ + v8 _ v9 _ v10 _ v11 _ v12 _ v13 _ v14 _ v15 _ + v16 _ v17 _ v18 _ v19 _ v20 _ v21 _ v22 _ v23 _ + v24 _ v25 _ v26 _ v27 _ v28 _ v29 _ v30 _ v31 _ +]; + +# AdVanced SIMD eXtension 256-bit registers (lasx) +# overlaps the floating point registers above +define register offset=0x1000 size=32 [ + x0 x1 x2 x3 x4 x5 x6 x7 + x8 x9 x10 x11 x12 x13 x14 x15 + x16 x17 x18 x19 x20 x21 x22 x23 + x24 x25 x26 x27 x28 x29 x30 x31 +]; + +@define CSR_OFFSET "0x2000" #used for the csr instructions csrxchg/cssrd/cssrw +define register offset=$(CSR_OFFSET) size=$(REGSIZE) [ + crmd prmd euen misc ecfg estat era badv + badi csr9 csr10 csr11 eentry csr13 csr14 csr15 + tlbidx tlbehi tlbelo0 tlbelo1 csr20 csr21 csr22 csr23 + asid pgdl pgdh pgd pwcl pwch stlbps rvacfg + cpuid prcfg1 prcfg2 prcfg3 csr36 csr37 csr38 csr39 + csr40 csr41 csr42 csr43 csr44 csr45 csr46 csr47 + save0 save1 save2 save3 save4 save5 save6 save7 + save8 save9 save10 save11 save12 save13 save14 save15 + tid tcfg tval cntc ticlr csr69 csr70 csr71 + csr72 csr73 csr74 csr75 csr76 csr78 csr79 + csr80 csr81 csr82 csr83 csr84 csr85 csr86 csr87 + csr88 csr89 csr90 csr91 csr92 csr93 csr94 csr95 + llbctl csr97 csr98 csr99 csr100 csr101 csr102 csr103 + csr104 csr105 csr106 csr107 csr108 csr109 csr110 csr111 + csr112 csr113 csr114 csr115 csr116 csr117 csr118 csr119 + csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127 + impctl1 impctl2 csr130 csr131 csr132 csr133 csr134 csr135 + tlbrentry tlbrbadv tlbrera tlbrsave tlbrelo0 tlbrelo1 tlbrehi tlbrprmd + merrctl merrinfo1 merrinfo2 merrentry merrera merrsave csr150 csr151 + ctag csr153 csr154 csr155 csr156 csr157 csr158 csr159 + csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167 + csr168 csr169 csr170 csr171 csr172 csr173 csr174 csr175 + csr176 csr177 csr178 csr179 csr180 csr181 csr182 csr183 + csr184 csr185 csr186 csr187 csr188 csr189 csr190 csr191 + csr192 csr193 csr194 csr195 csr196 csr197 csr198 csr199 + csr200 csr201 csr202 csr203 csr204 csr205 csr206 csr207 + csr208 csr209 csr210 csr211 csr212 csr213 csr214 csr215 + csr216 csr217 csr218 csr219 csr220 csr221 csr222 csr223 + csr224 csr225 csr226 csr227 csr228 csr229 csr230 csr231 + csr232 csr233 csr234 csr235 csr236 csr237 csr238 csr239 + csr240 csr241 csr242 csr243 csr244 csr245 csr246 csr247 + csr248 csr249 csr250 csr251 csr252 csr253 csr254 csr255 + csr256 csr257 csr258 csr259 csr260 csr261 csr262 csr263 + +]; + +# Dummy registers for floating point comparison +define register offset=0x5000 size=4 [ + FCMP1 FCMP2 +]; + +define register offset=0x5008 size=1 [ + FCMPR +]; + +define register offset=0x5100 size=8 [ + DCMP1 DCMP2 +]; + +define register offset=0x5110 size=1 [ + DCMPR +]; + +define register offset=0x50 size=4 contextreg; +define context contextreg +phase = (0,1) +; + +define token instr(32) + instword = ( 0,31) + op26_31 = (26,31) + op25_31 = (25,31) + op24_31 = (24,31) + op23_31 = (23,31) + op22_31 = (22,31) + op21_31 = (21,31) + op20_31 = (20,31) + op19_31 = (19,31) + op18_31 = (18,31) + op18_19 = (18,19) + op17_31 = (17,31) + op16_31 = (16,31) + op15_31 = (15,31) + op15_15 = (15,15) + op14_31 = (14,31) + op13_31 = (13,31) + op12_31 = (12,31) + op11_31 = (11,31) + op10_31 = (10,31) + op8_31 = ( 8,31) + op8_9 = ( 8, 9) + op7_31 = ( 7,31) + op5_9 = ( 5, 9) + op5_31 = ( 5,31) + op4_4 = ( 4, 4) + op3_4 = ( 3, 4) + op2_4 = ( 2, 4) + op0_2 = ( 0, 2) + op0_4 = ( 0, 4) + op0_31 = ( 0,31) + + cond = (16,19) + cond_s = (15,15) + + simm5_20 = ( 5,24) signed + simm5_13 = ( 5,17) signed + simm10_9 = (10,18) signed + simm10_8 = (10,17) signed + simm10_5 = (10,14) signed + simm10_14 = (10,23) signed + offs16 = (10,25) signed + off16 = (10,25) + simm10_12 = (10,21) signed + simm10_11 = (10,20) signed + simm10_10 = (10,19) signed + simm0_5 = ( 0, 4) signed + simm0_10 = ( 0, 9) signed + + rK = (10,14) + rK32 = (10,14) + + rJ = ( 5, 9) + rJ32 = ( 5, 9) + + rD = ( 0, 4) + rD32 = ( 0, 4) + + xrK = (10,14) + xrJ = ( 5, 9) + xrD = ( 0, 4) + xrA = (15,19) + + vrK = (10,14) + vrJ = ( 5, 9) + vrD = ( 0, 4) + vrA = (15,19) + + lbtrJ = ( 5, 6) + lbtrD = ( 0, 1) + + frK = (10,14) + frJ = ( 5, 9) + frD = ( 0, 4) + frA = (15,19) + + drK = (10,14) + drJ = ( 5, 9) + drD = ( 0, 4) + drA = (15,19) + + fccJ = ( 5, 7) + fccD = ( 0, 2) + fccA = (15,17) + + imm5_5 = ( 5, 9) + imm5_3 = ( 5, 7) + imm18_5 = (18,22) + imm18_4 = (18,21) + imm18_3 = (18,20) + imm18_2 = (18,19) + imm18_1 = (18,18) + imm16_6 = (16,21) + imm16_5 = (16,20) + imm15_3 = (15,17) + imm15_2 = (15,16) + imm10_8 = (10,17) + imm10_7 = (10,16) + imm10_6 = (10,15) + imm10_5 = (10,14) + imm10_4 = (10,13) + imm10_3 = (10,12) + imm10_2 = (10,11) + imm10_14 = (10,23) + imm10_12 = (10,21) + imm10_1 = (10,10) + imm0_5 = ( 0, 4) + imm0_4 = ( 0, 3) + imm0_15 = ( 0,14) +; + +attach variables [ rD rJ rK ] [ + zero ra tp sp a0 a1 a2 a3 + a4 a5 a6 a7 t0 t1 t2 t3 + t4 t5 t6 t7 t8 r21 fp s0 + s1 s2 s3 s4 s5 s6 s7 s8 +]; + +@ifdef LA64 +attach variables [ rD32 rJ32 rK32 ] [ + r0_lo ra_lo tp_lo sp_lo + a0_lo a1_lo a2_lo a3_lo + a4_lo a5_lo a6_lo a7_lo + t0_lo t1_lo t2_lo t3_lo + t4_lo t5_lo t6_lo t7_lo + t8_lo r21_lo fp_lo s0_lo + s1_lo s2_lo s3_lo s4_lo + s5_lo s6_lo s7_lo s8_lo +]; + +@else +# For LA32 these are the same as rD, rJ, rK +attach variables [ rD32 rJ32 rK32 ] [ + zero ra tp sp a0 a1 a2 a3 + a4 a5 a6 a7 t0 t1 t2 t3 + t4 t5 t6 t7 t8 r21 fp s0 + s1 s2 s3 s4 s5 s6 s7 s8 +]; + +@endif + + +@if FREGSIZE == "8" +# For 64-bit floating point single instruction operands use only the low part +attach variables [ frD frJ frK ] [ + fa0_lo fa1_lo fa2_lo fa3_lo fa4_lo fa5_lo fa6_lo fa7_lo + ft0_lo ft1_lo ft2_lo ft3_lo ft4_lo ft5_lo ft6_lo ft7_lo + ft8_lo ft9_lo ft10_lo ft11_lo ft12_lo ft13_lo ft14_lo ft15_lo + fs0_lo fs1_lo fs2_lo fs3_lo fs4_lo fs5_lo fs6_lo fs7_lo +]; + +attach variables [ drD drJ drK ] [ + fa0 fa1 fa2 fa3 fa4 fa5 fa6 fa7 + ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 + ft8 ft9 ft10 ft11 ft12 ft13 ft14 ft15 + fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7 +]; + +@else + +attach variables [ frD frJ frK ] [ + fa0 fa1 fa2 fa3 fa4 fa5 fa6 fa7 + ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 + ft8 ft9 ft10 ft11 ft12 ft13 ft14 ft15 + fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7 +]; + +# For 64-bit floating point Double instruction operands need to bond two 32-bit FPRs +attach variables [ drD drJ drK ] [ + fa0_1 _ fa2_3 _ fa4_5 _ fa6_7 _ + ft8_9 _ ft10_11 _ ft12_13 _ ft14_15 _ + ft16_17 _ ft18_19 _ ft20_21 _ ft22_23 _ + fs24_25 _ fs26_27 _ fs28_29 _ fs30_31 _ +]; + +@endif + + +attach variables [vrD vrJ vrK vrA] [ + v0 v1 v2 v3 v4 v5 v6 v7 + v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 + v24 v25 v26 v27 v28 v29 v30 v31 +]; + + +attach variables [xrD xrJ xrK xrA] [ + x0 x1 x2 x3 x4 x5 x6 x7 + x8 x9 x10 x11 x12 x13 x14 x15 + x16 x17 x18 x19 x20 x21 x22 x23 + x24 x25 x26 x27 x28 x29 x30 x31 +]; + + +attach variables [ fccD fccJ fccA] [ + fcc0 fcc1 fcc2 fcc3 fcc4 fcc5 fcc6 fcc7 +]; +# Register subconstructors +RD: rD is rD { export rD; } + +RDsrc: rD is rD { export rD; } +RDsrc: rD is rD & rD=0 { export 0:$(REGSIZE); } + +RJ: rJ is rJ { export rJ; } + +RJsrc: rJ is rJ { export rJ; } +RJsrc: rJ is rJ & rJ=0 { export 0:$(REGSIZE); } + +RK: rK is rK { export rK; } + +RKsrc: rK is rK { export rK; } +RKsrc: rK is rK & rK=0 { export 0:$(REGSIZE); } + +RD32: rD is rD & rD32 { export rD32; } + +RD32src: rD is rD & rD32 { export rD32; } +RD32src: rD is rD & rD32=0 { export 0:4; } + +RJ32: rJ is rJ & rJ32 { export rJ32; } + +RJ32src: rJ is rJ & rJ32 { export rJ32; } +RJ32src: rJ is rJ & rJ32=0 { export 0:4; } + +RK32: rK is rK & rK32 { export rK32; } + +RK32src: rK is rK & rK32 { export rK32; } +RK32src: rK is rK & rK32=0 { export 0:4; } + +@if FREGSIZE == "8" +FRD: drD is drD { export drD; } +FRJ: drJ is drJ { export drJ; } +FRK: drK is drK { export drK; } +@else +FRD: frD is frD { export frD; } +FRJ: frJ is frJ { export frJ; } +FRK: frK is frK { export frK; } +@endif + +# Immediate operand sub-constructors +addu16_imm: val is offs16 [val = offs16 << 16;] { export *[const]:$(REGSIZE) val; } + +alsl_shift: sa2 is imm15_2 [sa2 = imm15_2 + 1;] { export *[const]:1 sa2; } + +ldst_addr: RJsrc(simm10_12) is RJsrc & simm10_12 { local vaddr:$(REGSIZE) = RJsrc + simm10_12; export vaddr; } + +ldstptr_addr: RJsrc(voffs) is RJsrc & simm10_14 [voffs = (simm10_14 << 2);] { local vaddr:$(REGSIZE) = RJsrc + voffs; export vaddr; } + +ldstx_addr: RJsrc(RKsrc) is RJsrc & RKsrc { local vaddr:$(REGSIZE) = RJsrc + RKsrc; export vaddr; } + +pcadd2: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 2);] { export *[const]:$(REGSIZE) reloffs; } +pcadd12: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; } +pcala12: reloffs is simm5_20 [reloffs = (inst_start & ~0xfff) + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; } +pcadd18: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 18);] { export *[const]:$(REGSIZE) reloffs; } + +Rel16: reloc is offs16 [ reloc = inst_start + (offs16 << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel21: reloc is off16 & simm0_5 [ reloc = inst_start + (((simm0_5 << 16) + off16) << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel26: reloc is off16 & simm0_10 [ reloc = inst_start + (((simm0_10 << 16) | off16) << 2); ] { export *:$(ADDRSIZE) reloc; } + +RelJ16: RJsrc, offs16 is RJsrc & offs16 { local tmp:$(ADDRSIZE) = RJsrc + (offs16 << 2); export tmp; } + +simm12i: immed is simm5_20 [immed = simm5_20 << 12;] { export *[const]:$(REGSIZE) immed; } + + +# general pcodeops +define pcodeop break; +define pcodeop cpucfg; + +define pcodeop addr_bound_exception; +define pcodeop bound_check_exception; + +define pcodeop crc_ieee802.3; +define pcodeop crc_castagnoli; + +define pcodeop dbcl; + +define pcodeop dbar; +define pcodeop ibar; + +define pcodeop iocsrrd; +define pcodeop iocsrwr; + +define pcodeop preld_loadl1cache; +define pcodeop preld_storel1cache; +define pcodeop preld_nop; + +define pcodeop preldx_loadl1cache; +define pcodeop preldx_storel1cache; +define pcodeop preldx_nop; + +# param: 0 = low word, 1 = high word, 2 = both (for rdtime.d) +define pcodeop rdtime.counter; +define pcodeop rdtime.counterid; +define pcodeop syscall; + +define pcodeop f_scaleb; +define pcodeop f_logb; +define pcodeop f_class; +define pcodeop round_even; + +# +# MACROS +# +macro bitrev32(input, output) { + local v = input; + v = ((v & 0xffff0000) >> 16) | ((v & 0x0000ffff) << 16); + v = ((v & 0xff00ff00) >> 8) | ((v & 0x00ff00ff) << 8); + v = ((v & 0xf0f0f0f0) >> 4) | ((v & 0x0f0f0f0f) << 4); + v = ((v & 0xcccccccc) >> 2) | ((v & 0x33333333) << 2); + v = ((v & 0xaaaaaaaa) >> 1) | ((v & 0x55555555) << 1); + output = v; +} + +macro bitrev64(input, output) { + local v = input; + v = ((v & 0xffffffff00000000) >> 32) | ((v & 0x00000000ffffffff) << 32); + v = ((v & 0xffff0000ffff0000) >> 16) | ((v & 0x0000ffff0000ffff) << 16); + v = ((v & 0xff00ff00ff00ff00) >> 8) | ((v & 0x00ff00ff00ff00ff) << 8); + v = ((v & 0xf0f0f0f0f0f0f0f0) >> 4) | ((v & 0x0f0f0f0f0f0f0f0f) << 4); + v = ((v & 0xcccccccccccccccc) >> 2) | ((v & 0x3333333333333333) << 2); + v = ((v & 0xaaaaaaaaaaaaaaaa) >> 1) | ((v & 0x5555555555555555) << 1); + output = v; +} + +macro byterev(input, output) { + local v = input; + v = ((v & 0xf0) >> 4) | ((v & 0x0f) << 4); + v = ((v & 0xcc) >> 2) | ((v & 0x33) << 2); + v = ((v & 0xaa) >> 1) | ((v & 0x55) << 1); + output = v; +} + +macro byterev32(input, output) { + local v = input; + v = ((v & 0xf0f0f0f0) >> 4) | ((v & 0x0f0f0f0f) << 4); + v = ((v & 0xcccccccc) >> 2) | ((v & 0x33333333) << 2); + v = ((v & 0xaaaaaaaa) >> 1) | ((v & 0x55555555) << 1); + output = v; +} + +macro byterev64(input, output) { + local v = input; + v = ((v & 0xf0f0f0f0f0f0f0f0) >> 4) | ((v & 0x0f0f0f0f0f0f0f0f) << 4); + v = ((v & 0xcccccccccccccccc) >> 2) | ((v & 0x3333333333333333) << 2); + v = ((v & 0xaaaaaaaaaaaaaaaa) >> 1) | ((v & 0x5555555555555555) << 1); + output = v; +} + +macro tzcount32(input, count) { + count = 32; + local v = input & (-input); + count = count - zext(v != 0); + count = count - 16 * zext((v & 0x0000ffff) != 0); + count = count - 8 * zext((v & 0x00ff00ff) != 0); + count = count - 4 * zext((v & 0x0f0f0f0f) != 0); + count = count - 2 * zext((v & 0x33333333) != 0); + count = count - 1 * zext((v & 0x55555555) != 0); +} + +macro tzcount64(input, count) { + count = 64; + local v:8 = input & (-input); + count = count - 1 * zext(v != 0); + count = count - 32 * zext((v & 0x00000000ffffffff) != 0); + count = count - 16 * zext((v & 0x0000ffff0000ffff) != 0); + count = count - 8 * zext((v & 0x00ff00ff00ff00ff) != 0); + count = count - 4 * zext((v & 0x0f0f0f0f0f0f0f0f) != 0); + count = count - 2 * zext((v & 0x3333333333333333) != 0); + count = count - 1 * zext((v & 0x5555555555555555) != 0); +} + diff --git a/Ghidra/Processors/Loongarch/data/languages/lp64d.cspec b/Ghidra/Processors/Loongarch/data/languages/lp64d.cspec new file mode 100644 index 0000000000..169416602e --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/lp64d.cspec @@ -0,0 +1,128 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec b/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec new file mode 100644 index 0000000000..d5c1de2c9a --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lsx.sinc b/Ghidra/Processors/Loongarch/data/languages/lsx.sinc new file mode 100644 index 0000000000..af1259713f --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/lsx.sinc @@ -0,0 +1,5706 @@ +define pcodeop vfmadd.s; + +#lsx.txt vfmadd.s mask=0x09100000 +#0x09100000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vfmadd.s vrD, vrJ, vrK, vrA is op20_31=0x91 & vrD & vrJ & vrK & vrA { + vrD = vfmadd.s(vrD, vrJ, vrK, vrA); +} + +define pcodeop vfmadd.d; + +#lsx.txt vfmadd.d mask=0x09200000 +#0x09200000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vfmadd.d vrD, vrJ, vrK, vrA is op20_31=0x92 & vrD & vrJ & vrK & vrA { + vrD = vfmadd.d(vrD, vrJ, vrK, vrA); +} + +define pcodeop vfmsub.s; + +#lsx.txt vfmsub.s mask=0x09500000 +#0x09500000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vfmsub.s vrD, vrJ, vrK, vrA is op20_31=0x95 & vrD & vrJ & vrK & vrA { + vrD = vfmsub.s(vrD, vrJ, vrK, vrA); +} + +define pcodeop vfmsub.d; + +#lsx.txt vfmsub.d mask=0x09600000 +#0x09600000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vfmsub.d vrD, vrJ, vrK, vrA is op20_31=0x96 & vrD & vrJ & vrK & vrA { + vrD = vfmsub.d(vrD, vrJ, vrK, vrA); +} + +define pcodeop vfnmadd.s; + +#lsx.txt vfnmadd.s mask=0x09900000 +#0x09900000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vfnmadd.s vrD, vrJ, vrK, vrA is op20_31=0x99 & vrD & vrJ & vrK & vrA { + vrD = vfnmadd.s(vrD, vrJ, vrK, vrA); +} + +define pcodeop vfnmadd.d; + +#lsx.txt vfnmadd.d mask=0x09a00000 +#0x09a00000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vfnmadd.d vrD, vrJ, vrK, vrA is op20_31=0x9a & vrD & vrJ & vrK & vrA { + vrD = vfnmadd.d(vrD, vrJ, vrK, vrA); +} + +define pcodeop vfnmsub.s; + +#lsx.txt vfnmsub.s mask=0x09d00000 +#0x09d00000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vfnmsub.s vrD, vrJ, vrK, vrA is op20_31=0x9d & vrD & vrJ & vrK & vrA { + vrD = vfnmsub.s(vrD, vrJ, vrK, vrA); +} + +define pcodeop vfnmsub.d; + +#lsx.txt vfnmsub.d mask=0x09e00000 +#0x09e00000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vfnmsub.d vrD, vrJ, vrK, vrA is op20_31=0x9e & vrD & vrJ & vrK & vrA { + vrD = vfnmsub.d(vrD, vrJ, vrK, vrA); +} + +define pcodeop vfcmp.caf.s; + +#lsx.txt vfcmp.caf.s mask=0x0c500000 +#0x0c500000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.caf.s vrD, vrJ, vrK is op15_31=0x18a0 & vrD & vrJ & vrK { + vrD = vfcmp.caf.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.saf.s; + +#lsx.txt vfcmp.saf.s mask=0x0c508000 +#0x0c508000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.saf.s vrD, vrJ, vrK is op15_31=0x18a1 & vrD & vrJ & vrK { + vrD = vfcmp.saf.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.clt.s; + +#lsx.txt vfcmp.clt.s mask=0x0c510000 +#0x0c510000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.clt.s vrD, vrJ, vrK is op15_31=0x18a2 & vrD & vrJ & vrK { + vrD = vfcmp.clt.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.slt.s; + +#lsx.txt vfcmp.slt.s mask=0x0c518000 +#0x0c518000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.slt.s vrD, vrJ, vrK is op15_31=0x18a3 & vrD & vrJ & vrK { + vrD = vfcmp.slt.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.ceq.s; + +#lsx.txt vfcmp.ceq.s mask=0x0c520000 +#0x0c520000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.ceq.s vrD, vrJ, vrK is op15_31=0x18a4 & vrD & vrJ & vrK { + vrD = vfcmp.ceq.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.seq.s; + +#lsx.txt vfcmp.seq.s mask=0x0c528000 +#0x0c528000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.seq.s vrD, vrJ, vrK is op15_31=0x18a5 & vrD & vrJ & vrK { + vrD = vfcmp.seq.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cle.s; + +#lsx.txt vfcmp.cle.s mask=0x0c530000 +#0x0c530000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cle.s vrD, vrJ, vrK is op15_31=0x18a6 & vrD & vrJ & vrK { + vrD = vfcmp.cle.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sle.s; + +#lsx.txt vfcmp.sle.s mask=0x0c538000 +#0x0c538000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sle.s vrD, vrJ, vrK is op15_31=0x18a7 & vrD & vrJ & vrK { + vrD = vfcmp.sle.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cun.s; + +#lsx.txt vfcmp.cun.s mask=0x0c540000 +#0x0c540000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cun.s vrD, vrJ, vrK is op15_31=0x18a8 & vrD & vrJ & vrK { + vrD = vfcmp.cun.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sun.s; + +#lsx.txt vfcmp.sun.s mask=0x0c548000 +#0x0c548000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sun.s vrD, vrJ, vrK is op15_31=0x18a9 & vrD & vrJ & vrK { + vrD = vfcmp.sun.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cult.s; + +#lsx.txt vfcmp.cult.s mask=0x0c550000 +#0x0c550000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cult.s vrD, vrJ, vrK is op15_31=0x18aa & vrD & vrJ & vrK { + vrD = vfcmp.cult.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sult.s; + +#lsx.txt vfcmp.sult.s mask=0x0c558000 +#0x0c558000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sult.s vrD, vrJ, vrK is op15_31=0x18ab & vrD & vrJ & vrK { + vrD = vfcmp.sult.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cueq.s; + +#lsx.txt vfcmp.cueq.s mask=0x0c560000 +#0x0c560000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cueq.s vrD, vrJ, vrK is op15_31=0x18ac & vrD & vrJ & vrK { + vrD = vfcmp.cueq.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sueq.s; + +#lsx.txt vfcmp.sueq.s mask=0x0c568000 +#0x0c568000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sueq.s vrD, vrJ, vrK is op15_31=0x18ad & vrD & vrJ & vrK { + vrD = vfcmp.sueq.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cule.s; + +#lsx.txt vfcmp.cule.s mask=0x0c570000 +#0x0c570000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cule.s vrD, vrJ, vrK is op15_31=0x18ae & vrD & vrJ & vrK { + vrD = vfcmp.cule.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sule.s; + +#lsx.txt vfcmp.sule.s mask=0x0c578000 +#0x0c578000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sule.s vrD, vrJ, vrK is op15_31=0x18af & vrD & vrJ & vrK { + vrD = vfcmp.sule.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cne.s; + +#lsx.txt vfcmp.cne.s mask=0x0c580000 +#0x0c580000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cne.s vrD, vrJ, vrK is op15_31=0x18b0 & vrD & vrJ & vrK { + vrD = vfcmp.cne.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sne.s; + +#lsx.txt vfcmp.sne.s mask=0x0c588000 +#0x0c588000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sne.s vrD, vrJ, vrK is op15_31=0x18b1 & vrD & vrJ & vrK { + vrD = vfcmp.sne.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cor.s; + +#lsx.txt vfcmp.cor.s mask=0x0c5a0000 +#0x0c5a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cor.s vrD, vrJ, vrK is op15_31=0x18b4 & vrD & vrJ & vrK { + vrD = vfcmp.cor.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sor.s; + +#lsx.txt vfcmp.sor.s mask=0x0c5a8000 +#0x0c5a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sor.s vrD, vrJ, vrK is op15_31=0x18b5 & vrD & vrJ & vrK { + vrD = vfcmp.sor.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cune.s; + +#lsx.txt vfcmp.cune.s mask=0x0c5c0000 +#0x0c5c0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cune.s vrD, vrJ, vrK is op15_31=0x18b8 & vrD & vrJ & vrK { + vrD = vfcmp.cune.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sune.s; + +#lsx.txt vfcmp.sune.s mask=0x0c5c8000 +#0x0c5c8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sune.s vrD, vrJ, vrK is op15_31=0x18b9 & vrD & vrJ & vrK { + vrD = vfcmp.sune.s(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.caf.d; + +#lsx.txt vfcmp.caf.d mask=0x0c600000 +#0x0c600000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.caf.d vrD, vrJ, vrK is op15_31=0x18c0 & vrD & vrJ & vrK { + vrD = vfcmp.caf.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.saf.d; + +#lsx.txt vfcmp.saf.d mask=0x0c608000 +#0x0c608000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.saf.d vrD, vrJ, vrK is op15_31=0x18c1 & vrD & vrJ & vrK { + vrD = vfcmp.saf.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.clt.d; + +#lsx.txt vfcmp.clt.d mask=0x0c610000 +#0x0c610000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.clt.d vrD, vrJ, vrK is op15_31=0x18c2 & vrD & vrJ & vrK { + vrD = vfcmp.clt.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.slt.d; + +#lsx.txt vfcmp.slt.d mask=0x0c618000 +#0x0c618000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.slt.d vrD, vrJ, vrK is op15_31=0x18c3 & vrD & vrJ & vrK { + vrD = vfcmp.slt.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.ceq.d; + +#lsx.txt vfcmp.ceq.d mask=0x0c620000 +#0x0c620000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.ceq.d vrD, vrJ, vrK is op15_31=0x18c4 & vrD & vrJ & vrK { + vrD = vfcmp.ceq.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.seq.d; + +#lsx.txt vfcmp.seq.d mask=0x0c628000 +#0x0c628000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.seq.d vrD, vrJ, vrK is op15_31=0x18c5 & vrD & vrJ & vrK { + vrD = vfcmp.seq.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cle.d; + +#lsx.txt vfcmp.cle.d mask=0x0c630000 +#0x0c630000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cle.d vrD, vrJ, vrK is op15_31=0x18c6 & vrD & vrJ & vrK { + vrD = vfcmp.cle.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sle.d; + +#lsx.txt vfcmp.sle.d mask=0x0c638000 +#0x0c638000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sle.d vrD, vrJ, vrK is op15_31=0x18c7 & vrD & vrJ & vrK { + vrD = vfcmp.sle.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cun.d; + +#lsx.txt vfcmp.cun.d mask=0x0c640000 +#0x0c640000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cun.d vrD, vrJ, vrK is op15_31=0x18c8 & vrD & vrJ & vrK { + vrD = vfcmp.cun.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sun.d; + +#lsx.txt vfcmp.sun.d mask=0x0c648000 +#0x0c648000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sun.d vrD, vrJ, vrK is op15_31=0x18c9 & vrD & vrJ & vrK { + vrD = vfcmp.sun.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cult.d; + +#lsx.txt vfcmp.cult.d mask=0x0c650000 +#0x0c650000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cult.d vrD, vrJ, vrK is op15_31=0x18ca & vrD & vrJ & vrK { + vrD = vfcmp.cult.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sult.d; + +#lsx.txt vfcmp.sult.d mask=0x0c658000 +#0x0c658000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sult.d vrD, vrJ, vrK is op15_31=0x18cb & vrD & vrJ & vrK { + vrD = vfcmp.sult.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cueq.d; + +#lsx.txt vfcmp.cueq.d mask=0x0c660000 +#0x0c660000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cueq.d vrD, vrJ, vrK is op15_31=0x18cc & vrD & vrJ & vrK { + vrD = vfcmp.cueq.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sueq.d; + +#lsx.txt vfcmp.sueq.d mask=0x0c668000 +#0x0c668000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sueq.d vrD, vrJ, vrK is op15_31=0x18cd & vrD & vrJ & vrK { + vrD = vfcmp.sueq.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cule.d; + +#lsx.txt vfcmp.cule.d mask=0x0c670000 +#0x0c670000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cule.d vrD, vrJ, vrK is op15_31=0x18ce & vrD & vrJ & vrK { + vrD = vfcmp.cule.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sule.d; + +#lsx.txt vfcmp.sule.d mask=0x0c678000 +#0x0c678000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sule.d vrD, vrJ, vrK is op15_31=0x18cf & vrD & vrJ & vrK { + vrD = vfcmp.sule.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cne.d; + +#lsx.txt vfcmp.cne.d mask=0x0c680000 +#0x0c680000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cne.d vrD, vrJ, vrK is op15_31=0x18d0 & vrD & vrJ & vrK { + vrD = vfcmp.cne.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sne.d; + +#lsx.txt vfcmp.sne.d mask=0x0c688000 +#0x0c688000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sne.d vrD, vrJ, vrK is op15_31=0x18d1 & vrD & vrJ & vrK { + vrD = vfcmp.sne.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cor.d; + +#lsx.txt vfcmp.cor.d mask=0x0c6a0000 +#0x0c6a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cor.d vrD, vrJ, vrK is op15_31=0x18d4 & vrD & vrJ & vrK { + vrD = vfcmp.cor.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sor.d; + +#lsx.txt vfcmp.sor.d mask=0x0c6a8000 +#0x0c6a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sor.d vrD, vrJ, vrK is op15_31=0x18d5 & vrD & vrJ & vrK { + vrD = vfcmp.sor.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.cune.d; + +#lsx.txt vfcmp.cune.d mask=0x0c6c0000 +#0x0c6c0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.cune.d vrD, vrJ, vrK is op15_31=0x18d8 & vrD & vrJ & vrK { + vrD = vfcmp.cune.d(vrD, vrJ, vrK); +} + +define pcodeop vfcmp.sune.d; + +#lsx.txt vfcmp.sune.d mask=0x0c6c8000 +#0x0c6c8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcmp.sune.d vrD, vrJ, vrK is op15_31=0x18d9 & vrD & vrJ & vrK { + vrD = vfcmp.sune.d(vrD, vrJ, vrK); +} + +define pcodeop vbitsel.v; + +#lsx.txt vbitsel.v mask=0x0d100000 +#0x0d100000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vbitsel.v vrD, vrJ, vrK, vrA is op20_31=0xd1 & vrD & vrJ & vrK & vrA { + vrD = vbitsel.v(vrD, vrJ, vrK, vrA); +} + +define pcodeop vshuf.b; + +#lsx.txt vshuf.b mask=0x0d500000 +#0x0d500000 0xfff00000 v0:5,v5:5,v10:5,v15:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0', 'vreg15_5_s0'] +:vshuf.b vrD, vrJ, vrK, vrA is op20_31=0xd5 & vrD & vrJ & vrK & vrA { + vrD = vshuf.b(vrD, vrJ, vrK, vrA); +} + +define pcodeop vld; + +#lsx.txt vld mask=0x2c000000 +#0x2c000000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:vld vrD, RJsrc, simm10_12 is op22_31=0xb0 & vrD & RJsrc & simm10_12 { + vrD = vld(vrD, RJsrc, simm10_12:$(REGSIZE)); +} + +define pcodeop vst; + +#lsx.txt vst mask=0x2c400000 +#0x2c400000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:vst vrD, RJsrc, simm10_12 is op22_31=0xb1 & vrD & RJsrc & simm10_12 { + vrD = vst(vrD, RJsrc, simm10_12:$(REGSIZE)); +} + +define pcodeop vldrepl.d; + +#lsx.txt vldrepl.d mask=0x30100000 [@orig_fmt=VdJSk9ps3] +#0x30100000 0xfff80000 v0:5, r5:5, so10:9<<3 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_9_s0'] +#TODO: FIX RELATIVE OFFSET +:vldrepl.d vrD, RJsrc, simm10_9 is op19_31=0x602 & vrD & RJsrc & simm10_9 { + vrD = vldrepl.d(vrD, RJsrc, simm10_9:$(REGSIZE)); +} + +define pcodeop vldrepl.w; + +#lsx.txt vldrepl.w mask=0x30200000 [@orig_fmt=VdJSk10ps2] +#0x30200000 0xfff00000 v0:5, r5:5, so10:10<<2 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_10_s0'] +#TODO: FIX RELATIVE OFFSET +:vldrepl.w vrD, RJsrc, simm10_10 is op20_31=0x302 & vrD & RJsrc & simm10_10 { + vrD = vldrepl.w(vrD, RJsrc, simm10_10:$(REGSIZE)); +} + +define pcodeop vldrepl.h; + +#lsx.txt vldrepl.h mask=0x30400000 [@orig_fmt=VdJSk11ps1] +#0x30400000 0xffe00000 v0:5, r5:5, so10:11<<1 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_11_s0'] +#TODO: FIX RELATIVE OFFSET +:vldrepl.h vrD, RJsrc, simm10_11 is op21_31=0x182 & vrD & RJsrc & simm10_11 { + vrD = vldrepl.h(vrD, RJsrc, simm10_11:$(REGSIZE)); +} + +define pcodeop vldrepl.b; + +#lsx.txt vldrepl.b mask=0x30800000 +#0x30800000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] +#TODO: FIX RELATIVE OFFSET +:vldrepl.b vrD, RJsrc, simm10_12 is op22_31=0xc2 & vrD & RJsrc & simm10_12 { + vrD = vldrepl.b(vrD, RJsrc, simm10_12:$(REGSIZE)); +} + +define pcodeop vstelm.d; + +#lsx.txt vstelm.d mask=0x31100000 [@orig_fmt=VdJSk8ps3Un1] +#0x31100000 0xfff80000 v0:5, r5:5, so10:8<<3,u18:1 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_1_s0'] +#TODO: FIX RELATIVE OFFSET +:vstelm.d vrD, RJsrc, simm10_8, imm18_1 is op19_31=0x622 & vrD & RJsrc & simm10_8 & imm18_1 { + vrD = vstelm.d(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_1:$(REGSIZE)); +} + +define pcodeop vstelm.w; + +#lsx.txt vstelm.w mask=0x31200000 [@orig_fmt=VdJSk8ps2Un2] +#0x31200000 0xfff00000 v0:5, r5:5, so10:8<<2,u18:2 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_2_s0'] +#TODO: FIX RELATIVE OFFSET +:vstelm.w vrD, RJsrc, simm10_8, imm18_2 is op20_31=0x312 & vrD & RJsrc & simm10_8 & imm18_2 { + vrD = vstelm.w(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_2:$(REGSIZE)); +} + +define pcodeop vstelm.h; + +#lsx.txt vstelm.h mask=0x31400000 [@orig_fmt=VdJSk8ps1Un3] +#0x31400000 0xffe00000 v0:5, r5:5, so10:8<<1,u18:3 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_3_s0'] +#TODO: FIX RELATIVE OFFSET +:vstelm.h vrD, RJsrc, simm10_8, imm18_3 is op21_31=0x18a & vrD & RJsrc & simm10_8 & imm18_3 { + vrD = vstelm.h(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_3:$(REGSIZE)); +} + +define pcodeop vstelm.b; + +#lsx.txt vstelm.b mask=0x31800000 +#0x31800000 0xffc00000 v0:5, r5:5, so10:8,u18:4 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_4_s0'] +#TODO: FIX RELATIVE OFFSET +:vstelm.b vrD, RJsrc, simm10_8, imm18_4 is op22_31=0xc6 & vrD & RJsrc & simm10_8 & imm18_4 { + vrD = vstelm.b(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_4:$(REGSIZE)); +} + +define pcodeop vldx; + +#lsx.txt vldx mask=0x38400000 +#0x38400000 0xffff8000 v0:5, r5:5, r10:5 ['vreg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:vldx vrD, RJsrc, RKsrc is op15_31=0x7080 & vrD & RJsrc & RKsrc { + vrD = vldx(vrD, RJsrc, RKsrc); +} + +define pcodeop vstx; + +#lsx.txt vstx mask=0x38440000 +#0x38440000 0xffff8000 v0:5, r5:5, r10:5 ['vreg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:vstx vrD, RJsrc, RKsrc is op15_31=0x7088 & vrD & RJsrc & RKsrc { + vrD = vstx(vrD, RJsrc, RKsrc); +} + +define pcodeop vseq.b; + +#lsx.txt vseq.b mask=0x70000000 +#0x70000000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vseq.b vrD, vrJ, vrK is op15_31=0xe000 & vrD & vrJ & vrK { + vrD = vseq.b(vrD, vrJ, vrK); +} + +define pcodeop vseq.h; + +#lsx.txt vseq.h mask=0x70008000 +#0x70008000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vseq.h vrD, vrJ, vrK is op15_31=0xe001 & vrD & vrJ & vrK { + vrD = vseq.h(vrD, vrJ, vrK); +} + +define pcodeop vseq.w; + +#lsx.txt vseq.w mask=0x70010000 +#0x70010000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vseq.w vrD, vrJ, vrK is op15_31=0xe002 & vrD & vrJ & vrK { + vrD = vseq.w(vrD, vrJ, vrK); +} + +define pcodeop vseq.d; + +#lsx.txt vseq.d mask=0x70018000 +#0x70018000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vseq.d vrD, vrJ, vrK is op15_31=0xe003 & vrD & vrJ & vrK { + vrD = vseq.d(vrD, vrJ, vrK); +} + +define pcodeop vsle.b; + +#lsx.txt vsle.b mask=0x70020000 +#0x70020000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsle.b vrD, vrJ, vrK is op15_31=0xe004 & vrD & vrJ & vrK { + vrD = vsle.b(vrD, vrJ, vrK); +} + +define pcodeop vsle.h; + +#lsx.txt vsle.h mask=0x70028000 +#0x70028000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsle.h vrD, vrJ, vrK is op15_31=0xe005 & vrD & vrJ & vrK { + vrD = vsle.h(vrD, vrJ, vrK); +} + +define pcodeop vsle.w; + +#lsx.txt vsle.w mask=0x70030000 +#0x70030000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsle.w vrD, vrJ, vrK is op15_31=0xe006 & vrD & vrJ & vrK { + vrD = vsle.w(vrD, vrJ, vrK); +} + +define pcodeop vsle.d; + +#lsx.txt vsle.d mask=0x70038000 +#0x70038000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsle.d vrD, vrJ, vrK is op15_31=0xe007 & vrD & vrJ & vrK { + vrD = vsle.d(vrD, vrJ, vrK); +} + +define pcodeop vsle.bu; + +#lsx.txt vsle.bu mask=0x70040000 +#0x70040000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsle.bu vrD, vrJ, vrK is op15_31=0xe008 & vrD & vrJ & vrK { + vrD = vsle.bu(vrD, vrJ, vrK); +} + +define pcodeop vsle.hu; + +#lsx.txt vsle.hu mask=0x70048000 +#0x70048000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsle.hu vrD, vrJ, vrK is op15_31=0xe009 & vrD & vrJ & vrK { + vrD = vsle.hu(vrD, vrJ, vrK); +} + +define pcodeop vsle.wu; + +#lsx.txt vsle.wu mask=0x70050000 +#0x70050000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsle.wu vrD, vrJ, vrK is op15_31=0xe00a & vrD & vrJ & vrK { + vrD = vsle.wu(vrD, vrJ, vrK); +} + +define pcodeop vsle.du; + +#lsx.txt vsle.du mask=0x70058000 +#0x70058000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsle.du vrD, vrJ, vrK is op15_31=0xe00b & vrD & vrJ & vrK { + vrD = vsle.du(vrD, vrJ, vrK); +} + +define pcodeop vslt.b; + +#lsx.txt vslt.b mask=0x70060000 +#0x70060000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vslt.b vrD, vrJ, vrK is op15_31=0xe00c & vrD & vrJ & vrK { + vrD = vslt.b(vrD, vrJ, vrK); +} + +define pcodeop vslt.h; + +#lsx.txt vslt.h mask=0x70068000 +#0x70068000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vslt.h vrD, vrJ, vrK is op15_31=0xe00d & vrD & vrJ & vrK { + vrD = vslt.h(vrD, vrJ, vrK); +} + +define pcodeop vslt.w; + +#lsx.txt vslt.w mask=0x70070000 +#0x70070000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vslt.w vrD, vrJ, vrK is op15_31=0xe00e & vrD & vrJ & vrK { + vrD = vslt.w(vrD, vrJ, vrK); +} + +define pcodeop vslt.d; + +#lsx.txt vslt.d mask=0x70078000 +#0x70078000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vslt.d vrD, vrJ, vrK is op15_31=0xe00f & vrD & vrJ & vrK { + vrD = vslt.d(vrD, vrJ, vrK); +} + +define pcodeop vslt.bu; + +#lsx.txt vslt.bu mask=0x70080000 +#0x70080000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vslt.bu vrD, vrJ, vrK is op15_31=0xe010 & vrD & vrJ & vrK { + vrD = vslt.bu(vrD, vrJ, vrK); +} + +define pcodeop vslt.hu; + +#lsx.txt vslt.hu mask=0x70088000 +#0x70088000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vslt.hu vrD, vrJ, vrK is op15_31=0xe011 & vrD & vrJ & vrK { + vrD = vslt.hu(vrD, vrJ, vrK); +} + +define pcodeop vslt.wu; + +#lsx.txt vslt.wu mask=0x70090000 +#0x70090000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vslt.wu vrD, vrJ, vrK is op15_31=0xe012 & vrD & vrJ & vrK { + vrD = vslt.wu(vrD, vrJ, vrK); +} + +define pcodeop vslt.du; + +#lsx.txt vslt.du mask=0x70098000 +#0x70098000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vslt.du vrD, vrJ, vrK is op15_31=0xe013 & vrD & vrJ & vrK { + vrD = vslt.du(vrD, vrJ, vrK); +} + +define pcodeop vadd.b; + +#lsx.txt vadd.b mask=0x700a0000 +#0x700a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadd.b vrD, vrJ, vrK is op15_31=0xe014 & vrD & vrJ & vrK { + vrD = vadd.b(vrD, vrJ, vrK); +} + +define pcodeop vadd.h; + +#lsx.txt vadd.h mask=0x700a8000 +#0x700a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadd.h vrD, vrJ, vrK is op15_31=0xe015 & vrD & vrJ & vrK { + vrD = vadd.h(vrD, vrJ, vrK); +} + +define pcodeop vadd.w; + +#lsx.txt vadd.w mask=0x700b0000 +#0x700b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadd.w vrD, vrJ, vrK is op15_31=0xe016 & vrD & vrJ & vrK { + vrD = vadd.w(vrD, vrJ, vrK); +} + +define pcodeop vadd.d; + +#lsx.txt vadd.d mask=0x700b8000 +#0x700b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadd.d vrD, vrJ, vrK is op15_31=0xe017 & vrD & vrJ & vrK { + vrD = vadd.d(vrD, vrJ, vrK); +} + +define pcodeop vsub.b; + +#lsx.txt vsub.b mask=0x700c0000 +#0x700c0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsub.b vrD, vrJ, vrK is op15_31=0xe018 & vrD & vrJ & vrK { + vrD = vsub.b(vrD, vrJ, vrK); +} + +define pcodeop vsub.h; + +#lsx.txt vsub.h mask=0x700c8000 +#0x700c8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsub.h vrD, vrJ, vrK is op15_31=0xe019 & vrD & vrJ & vrK { + vrD = vsub.h(vrD, vrJ, vrK); +} + +define pcodeop vsub.w; + +#lsx.txt vsub.w mask=0x700d0000 +#0x700d0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsub.w vrD, vrJ, vrK is op15_31=0xe01a & vrD & vrJ & vrK { + vrD = vsub.w(vrD, vrJ, vrK); +} + +define pcodeop vsub.d; + +#lsx.txt vsub.d mask=0x700d8000 +#0x700d8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsub.d vrD, vrJ, vrK is op15_31=0xe01b & vrD & vrJ & vrK { + vrD = vsub.d(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.h.b; + +#lsx.txt vaddwev.h.b mask=0x701e0000 +#0x701e0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.h.b vrD, vrJ, vrK is op15_31=0xe03c & vrD & vrJ & vrK { + vrD = vaddwev.h.b(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.w.h; + +#lsx.txt vaddwev.w.h mask=0x701e8000 +#0x701e8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.w.h vrD, vrJ, vrK is op15_31=0xe03d & vrD & vrJ & vrK { + vrD = vaddwev.w.h(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.d.w; + +#lsx.txt vaddwev.d.w mask=0x701f0000 +#0x701f0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.d.w vrD, vrJ, vrK is op15_31=0xe03e & vrD & vrJ & vrK { + vrD = vaddwev.d.w(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.q.d; + +#lsx.txt vaddwev.q.d mask=0x701f8000 +#0x701f8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.q.d vrD, vrJ, vrK is op15_31=0xe03f & vrD & vrJ & vrK { + vrD = vaddwev.q.d(vrD, vrJ, vrK); +} + +define pcodeop vsubwev.h.b; + +#lsx.txt vsubwev.h.b mask=0x70200000 +#0x70200000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwev.h.b vrD, vrJ, vrK is op15_31=0xe040 & vrD & vrJ & vrK { + vrD = vsubwev.h.b(vrD, vrJ, vrK); +} + +define pcodeop vsubwev.w.h; + +#lsx.txt vsubwev.w.h mask=0x70208000 +#0x70208000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwev.w.h vrD, vrJ, vrK is op15_31=0xe041 & vrD & vrJ & vrK { + vrD = vsubwev.w.h(vrD, vrJ, vrK); +} + +define pcodeop vsubwev.d.w; + +#lsx.txt vsubwev.d.w mask=0x70210000 +#0x70210000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwev.d.w vrD, vrJ, vrK is op15_31=0xe042 & vrD & vrJ & vrK { + vrD = vsubwev.d.w(vrD, vrJ, vrK); +} + +define pcodeop vsubwev.q.d; + +#lsx.txt vsubwev.q.d mask=0x70218000 +#0x70218000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwev.q.d vrD, vrJ, vrK is op15_31=0xe043 & vrD & vrJ & vrK { + vrD = vsubwev.q.d(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.h.b; + +#lsx.txt vaddwod.h.b mask=0x70220000 +#0x70220000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.h.b vrD, vrJ, vrK is op15_31=0xe044 & vrD & vrJ & vrK { + vrD = vaddwod.h.b(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.w.h; + +#lsx.txt vaddwod.w.h mask=0x70228000 +#0x70228000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.w.h vrD, vrJ, vrK is op15_31=0xe045 & vrD & vrJ & vrK { + vrD = vaddwod.w.h(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.d.w; + +#lsx.txt vaddwod.d.w mask=0x70230000 +#0x70230000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.d.w vrD, vrJ, vrK is op15_31=0xe046 & vrD & vrJ & vrK { + vrD = vaddwod.d.w(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.q.d; + +#lsx.txt vaddwod.q.d mask=0x70238000 +#0x70238000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.q.d vrD, vrJ, vrK is op15_31=0xe047 & vrD & vrJ & vrK { + vrD = vaddwod.q.d(vrD, vrJ, vrK); +} + +define pcodeop vsubwod.h.b; + +#lsx.txt vsubwod.h.b mask=0x70240000 +#0x70240000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwod.h.b vrD, vrJ, vrK is op15_31=0xe048 & vrD & vrJ & vrK { + vrD = vsubwod.h.b(vrD, vrJ, vrK); +} + +define pcodeop vsubwod.w.h; + +#lsx.txt vsubwod.w.h mask=0x70248000 +#0x70248000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwod.w.h vrD, vrJ, vrK is op15_31=0xe049 & vrD & vrJ & vrK { + vrD = vsubwod.w.h(vrD, vrJ, vrK); +} + +define pcodeop vsubwod.d.w; + +#lsx.txt vsubwod.d.w mask=0x70250000 +#0x70250000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwod.d.w vrD, vrJ, vrK is op15_31=0xe04a & vrD & vrJ & vrK { + vrD = vsubwod.d.w(vrD, vrJ, vrK); +} + +define pcodeop vsubwod.q.d; + +#lsx.txt vsubwod.q.d mask=0x70258000 +#0x70258000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwod.q.d vrD, vrJ, vrK is op15_31=0xe04b & vrD & vrJ & vrK { + vrD = vsubwod.q.d(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.h.bu; + +#lsx.txt vaddwev.h.bu mask=0x702e0000 +#0x702e0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.h.bu vrD, vrJ, vrK is op15_31=0xe05c & vrD & vrJ & vrK { + vrD = vaddwev.h.bu(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.w.hu; + +#lsx.txt vaddwev.w.hu mask=0x702e8000 +#0x702e8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.w.hu vrD, vrJ, vrK is op15_31=0xe05d & vrD & vrJ & vrK { + vrD = vaddwev.w.hu(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.d.wu; + +#lsx.txt vaddwev.d.wu mask=0x702f0000 +#0x702f0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.d.wu vrD, vrJ, vrK is op15_31=0xe05e & vrD & vrJ & vrK { + vrD = vaddwev.d.wu(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.q.du; + +#lsx.txt vaddwev.q.du mask=0x702f8000 +#0x702f8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.q.du vrD, vrJ, vrK is op15_31=0xe05f & vrD & vrJ & vrK { + vrD = vaddwev.q.du(vrD, vrJ, vrK); +} + +define pcodeop vsubwev.h.bu; + +#lsx.txt vsubwev.h.bu mask=0x70300000 +#0x70300000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwev.h.bu vrD, vrJ, vrK is op15_31=0xe060 & vrD & vrJ & vrK { + vrD = vsubwev.h.bu(vrD, vrJ, vrK); +} + +define pcodeop vsubwev.w.hu; + +#lsx.txt vsubwev.w.hu mask=0x70308000 +#0x70308000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwev.w.hu vrD, vrJ, vrK is op15_31=0xe061 & vrD & vrJ & vrK { + vrD = vsubwev.w.hu(vrD, vrJ, vrK); +} + +define pcodeop vsubwev.d.wu; + +#lsx.txt vsubwev.d.wu mask=0x70310000 +#0x70310000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwev.d.wu vrD, vrJ, vrK is op15_31=0xe062 & vrD & vrJ & vrK { + vrD = vsubwev.d.wu(vrD, vrJ, vrK); +} + +define pcodeop vsubwev.q.du; + +#lsx.txt vsubwev.q.du mask=0x70318000 +#0x70318000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwev.q.du vrD, vrJ, vrK is op15_31=0xe063 & vrD & vrJ & vrK { + vrD = vsubwev.q.du(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.h.bu; + +#lsx.txt vaddwod.h.bu mask=0x70320000 +#0x70320000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.h.bu vrD, vrJ, vrK is op15_31=0xe064 & vrD & vrJ & vrK { + vrD = vaddwod.h.bu(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.w.hu; + +#lsx.txt vaddwod.w.hu mask=0x70328000 +#0x70328000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.w.hu vrD, vrJ, vrK is op15_31=0xe065 & vrD & vrJ & vrK { + vrD = vaddwod.w.hu(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.d.wu; + +#lsx.txt vaddwod.d.wu mask=0x70330000 +#0x70330000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.d.wu vrD, vrJ, vrK is op15_31=0xe066 & vrD & vrJ & vrK { + vrD = vaddwod.d.wu(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.q.du; + +#lsx.txt vaddwod.q.du mask=0x70338000 +#0x70338000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.q.du vrD, vrJ, vrK is op15_31=0xe067 & vrD & vrJ & vrK { + vrD = vaddwod.q.du(vrD, vrJ, vrK); +} + +define pcodeop vsubwod.h.bu; + +#lsx.txt vsubwod.h.bu mask=0x70340000 +#0x70340000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwod.h.bu vrD, vrJ, vrK is op15_31=0xe068 & vrD & vrJ & vrK { + vrD = vsubwod.h.bu(vrD, vrJ, vrK); +} + +define pcodeop vsubwod.w.hu; + +#lsx.txt vsubwod.w.hu mask=0x70348000 +#0x70348000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwod.w.hu vrD, vrJ, vrK is op15_31=0xe069 & vrD & vrJ & vrK { + vrD = vsubwod.w.hu(vrD, vrJ, vrK); +} + +define pcodeop vsubwod.d.wu; + +#lsx.txt vsubwod.d.wu mask=0x70350000 +#0x70350000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwod.d.wu vrD, vrJ, vrK is op15_31=0xe06a & vrD & vrJ & vrK { + vrD = vsubwod.d.wu(vrD, vrJ, vrK); +} + +define pcodeop vsubwod.q.du; + +#lsx.txt vsubwod.q.du mask=0x70358000 +#0x70358000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsubwod.q.du vrD, vrJ, vrK is op15_31=0xe06b & vrD & vrJ & vrK { + vrD = vsubwod.q.du(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.h.bu.b; + +#lsx.txt vaddwev.h.bu.b mask=0x703e0000 +#0x703e0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.h.bu.b vrD, vrJ, vrK is op15_31=0xe07c & vrD & vrJ & vrK { + vrD = vaddwev.h.bu.b(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.w.hu.h; + +#lsx.txt vaddwev.w.hu.h mask=0x703e8000 +#0x703e8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.w.hu.h vrD, vrJ, vrK is op15_31=0xe07d & vrD & vrJ & vrK { + vrD = vaddwev.w.hu.h(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.d.wu.w; + +#lsx.txt vaddwev.d.wu.w mask=0x703f0000 +#0x703f0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.d.wu.w vrD, vrJ, vrK is op15_31=0xe07e & vrD & vrJ & vrK { + vrD = vaddwev.d.wu.w(vrD, vrJ, vrK); +} + +define pcodeop vaddwev.q.du.d; + +#lsx.txt vaddwev.q.du.d mask=0x703f8000 +#0x703f8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwev.q.du.d vrD, vrJ, vrK is op15_31=0xe07f & vrD & vrJ & vrK { + vrD = vaddwev.q.du.d(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.h.bu.b; + +#lsx.txt vaddwod.h.bu.b mask=0x70400000 +#0x70400000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.h.bu.b vrD, vrJ, vrK is op15_31=0xe080 & vrD & vrJ & vrK { + vrD = vaddwod.h.bu.b(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.w.hu.h; + +#lsx.txt vaddwod.w.hu.h mask=0x70408000 +#0x70408000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.w.hu.h vrD, vrJ, vrK is op15_31=0xe081 & vrD & vrJ & vrK { + vrD = vaddwod.w.hu.h(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.d.wu.w; + +#lsx.txt vaddwod.d.wu.w mask=0x70410000 +#0x70410000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.d.wu.w vrD, vrJ, vrK is op15_31=0xe082 & vrD & vrJ & vrK { + vrD = vaddwod.d.wu.w(vrD, vrJ, vrK); +} + +define pcodeop vaddwod.q.du.d; + +#lsx.txt vaddwod.q.du.d mask=0x70418000 +#0x70418000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vaddwod.q.du.d vrD, vrJ, vrK is op15_31=0xe083 & vrD & vrJ & vrK { + vrD = vaddwod.q.du.d(vrD, vrJ, vrK); +} + +define pcodeop vsadd.b; + +#lsx.txt vsadd.b mask=0x70460000 +#0x70460000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsadd.b vrD, vrJ, vrK is op15_31=0xe08c & vrD & vrJ & vrK { + vrD = vsadd.b(vrD, vrJ, vrK); +} + +define pcodeop vsadd.h; + +#lsx.txt vsadd.h mask=0x70468000 +#0x70468000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsadd.h vrD, vrJ, vrK is op15_31=0xe08d & vrD & vrJ & vrK { + vrD = vsadd.h(vrD, vrJ, vrK); +} + +define pcodeop vsadd.w; + +#lsx.txt vsadd.w mask=0x70470000 +#0x70470000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsadd.w vrD, vrJ, vrK is op15_31=0xe08e & vrD & vrJ & vrK { + vrD = vsadd.w(vrD, vrJ, vrK); +} + +define pcodeop vsadd.d; + +#lsx.txt vsadd.d mask=0x70478000 +#0x70478000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsadd.d vrD, vrJ, vrK is op15_31=0xe08f & vrD & vrJ & vrK { + vrD = vsadd.d(vrD, vrJ, vrK); +} + +define pcodeop vssub.b; + +#lsx.txt vssub.b mask=0x70480000 +#0x70480000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssub.b vrD, vrJ, vrK is op15_31=0xe090 & vrD & vrJ & vrK { + vrD = vssub.b(vrD, vrJ, vrK); +} + +define pcodeop vssub.h; + +#lsx.txt vssub.h mask=0x70488000 +#0x70488000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssub.h vrD, vrJ, vrK is op15_31=0xe091 & vrD & vrJ & vrK { + vrD = vssub.h(vrD, vrJ, vrK); +} + +define pcodeop vssub.w; + +#lsx.txt vssub.w mask=0x70490000 +#0x70490000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssub.w vrD, vrJ, vrK is op15_31=0xe092 & vrD & vrJ & vrK { + vrD = vssub.w(vrD, vrJ, vrK); +} + +define pcodeop vssub.d; + +#lsx.txt vssub.d mask=0x70498000 +#0x70498000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssub.d vrD, vrJ, vrK is op15_31=0xe093 & vrD & vrJ & vrK { + vrD = vssub.d(vrD, vrJ, vrK); +} + +define pcodeop vsadd.bu; + +#lsx.txt vsadd.bu mask=0x704a0000 +#0x704a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsadd.bu vrD, vrJ, vrK is op15_31=0xe094 & vrD & vrJ & vrK { + vrD = vsadd.bu(vrD, vrJ, vrK); +} + +define pcodeop vsadd.hu; + +#lsx.txt vsadd.hu mask=0x704a8000 +#0x704a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsadd.hu vrD, vrJ, vrK is op15_31=0xe095 & vrD & vrJ & vrK { + vrD = vsadd.hu(vrD, vrJ, vrK); +} + +define pcodeop vsadd.wu; + +#lsx.txt vsadd.wu mask=0x704b0000 +#0x704b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsadd.wu vrD, vrJ, vrK is op15_31=0xe096 & vrD & vrJ & vrK { + vrD = vsadd.wu(vrD, vrJ, vrK); +} + +define pcodeop vsadd.du; + +#lsx.txt vsadd.du mask=0x704b8000 +#0x704b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsadd.du vrD, vrJ, vrK is op15_31=0xe097 & vrD & vrJ & vrK { + vrD = vsadd.du(vrD, vrJ, vrK); +} + +define pcodeop vssub.bu; + +#lsx.txt vssub.bu mask=0x704c0000 +#0x704c0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssub.bu vrD, vrJ, vrK is op15_31=0xe098 & vrD & vrJ & vrK { + vrD = vssub.bu(vrD, vrJ, vrK); +} + +define pcodeop vssub.hu; + +#lsx.txt vssub.hu mask=0x704c8000 +#0x704c8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssub.hu vrD, vrJ, vrK is op15_31=0xe099 & vrD & vrJ & vrK { + vrD = vssub.hu(vrD, vrJ, vrK); +} + +define pcodeop vssub.wu; + +#lsx.txt vssub.wu mask=0x704d0000 +#0x704d0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssub.wu vrD, vrJ, vrK is op15_31=0xe09a & vrD & vrJ & vrK { + vrD = vssub.wu(vrD, vrJ, vrK); +} + +define pcodeop vssub.du; + +#lsx.txt vssub.du mask=0x704d8000 +#0x704d8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssub.du vrD, vrJ, vrK is op15_31=0xe09b & vrD & vrJ & vrK { + vrD = vssub.du(vrD, vrJ, vrK); +} + +define pcodeop vhaddw.h.b; + +#lsx.txt vhaddw.h.b mask=0x70540000 +#0x70540000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhaddw.h.b vrD, vrJ, vrK is op15_31=0xe0a8 & vrD & vrJ & vrK { + vrD = vhaddw.h.b(vrD, vrJ, vrK); +} + +define pcodeop vhaddw.w.h; + +#lsx.txt vhaddw.w.h mask=0x70548000 +#0x70548000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhaddw.w.h vrD, vrJ, vrK is op15_31=0xe0a9 & vrD & vrJ & vrK { + vrD = vhaddw.w.h(vrD, vrJ, vrK); +} + +define pcodeop vhaddw.d.w; + +#lsx.txt vhaddw.d.w mask=0x70550000 +#0x70550000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhaddw.d.w vrD, vrJ, vrK is op15_31=0xe0aa & vrD & vrJ & vrK { + vrD = vhaddw.d.w(vrD, vrJ, vrK); +} + +define pcodeop vhaddw.q.d; + +#lsx.txt vhaddw.q.d mask=0x70558000 +#0x70558000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhaddw.q.d vrD, vrJ, vrK is op15_31=0xe0ab & vrD & vrJ & vrK { + vrD = vhaddw.q.d(vrD, vrJ, vrK); +} + +define pcodeop vhsubw.h.b; + +#lsx.txt vhsubw.h.b mask=0x70560000 +#0x70560000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhsubw.h.b vrD, vrJ, vrK is op15_31=0xe0ac & vrD & vrJ & vrK { + vrD = vhsubw.h.b(vrD, vrJ, vrK); +} + +define pcodeop vhsubw.w.h; + +#lsx.txt vhsubw.w.h mask=0x70568000 +#0x70568000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhsubw.w.h vrD, vrJ, vrK is op15_31=0xe0ad & vrD & vrJ & vrK { + vrD = vhsubw.w.h(vrD, vrJ, vrK); +} + +define pcodeop vhsubw.d.w; + +#lsx.txt vhsubw.d.w mask=0x70570000 +#0x70570000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhsubw.d.w vrD, vrJ, vrK is op15_31=0xe0ae & vrD & vrJ & vrK { + vrD = vhsubw.d.w(vrD, vrJ, vrK); +} + +define pcodeop vhsubw.q.d; + +#lsx.txt vhsubw.q.d mask=0x70578000 +#0x70578000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhsubw.q.d vrD, vrJ, vrK is op15_31=0xe0af & vrD & vrJ & vrK { + vrD = vhsubw.q.d(vrD, vrJ, vrK); +} + +define pcodeop vhaddw.hu.bu; + +#lsx.txt vhaddw.hu.bu mask=0x70580000 +#0x70580000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhaddw.hu.bu vrD, vrJ, vrK is op15_31=0xe0b0 & vrD & vrJ & vrK { + vrD = vhaddw.hu.bu(vrD, vrJ, vrK); +} + +define pcodeop vhaddw.wu.hu; + +#lsx.txt vhaddw.wu.hu mask=0x70588000 +#0x70588000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhaddw.wu.hu vrD, vrJ, vrK is op15_31=0xe0b1 & vrD & vrJ & vrK { + vrD = vhaddw.wu.hu(vrD, vrJ, vrK); +} + +define pcodeop vhaddw.du.wu; + +#lsx.txt vhaddw.du.wu mask=0x70590000 +#0x70590000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhaddw.du.wu vrD, vrJ, vrK is op15_31=0xe0b2 & vrD & vrJ & vrK { + vrD = vhaddw.du.wu(vrD, vrJ, vrK); +} + +define pcodeop vhaddw.qu.du; + +#lsx.txt vhaddw.qu.du mask=0x70598000 +#0x70598000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhaddw.qu.du vrD, vrJ, vrK is op15_31=0xe0b3 & vrD & vrJ & vrK { + vrD = vhaddw.qu.du(vrD, vrJ, vrK); +} + +define pcodeop vhsubw.hu.bu; + +#lsx.txt vhsubw.hu.bu mask=0x705a0000 +#0x705a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhsubw.hu.bu vrD, vrJ, vrK is op15_31=0xe0b4 & vrD & vrJ & vrK { + vrD = vhsubw.hu.bu(vrD, vrJ, vrK); +} + +define pcodeop vhsubw.wu.hu; + +#lsx.txt vhsubw.wu.hu mask=0x705a8000 +#0x705a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhsubw.wu.hu vrD, vrJ, vrK is op15_31=0xe0b5 & vrD & vrJ & vrK { + vrD = vhsubw.wu.hu(vrD, vrJ, vrK); +} + +define pcodeop vhsubw.du.wu; + +#lsx.txt vhsubw.du.wu mask=0x705b0000 +#0x705b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhsubw.du.wu vrD, vrJ, vrK is op15_31=0xe0b6 & vrD & vrJ & vrK { + vrD = vhsubw.du.wu(vrD, vrJ, vrK); +} + +define pcodeop vhsubw.qu.du; + +#lsx.txt vhsubw.qu.du mask=0x705b8000 +#0x705b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vhsubw.qu.du vrD, vrJ, vrK is op15_31=0xe0b7 & vrD & vrJ & vrK { + vrD = vhsubw.qu.du(vrD, vrJ, vrK); +} + +define pcodeop vadda.b; + +#lsx.txt vadda.b mask=0x705c0000 +#0x705c0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadda.b vrD, vrJ, vrK is op15_31=0xe0b8 & vrD & vrJ & vrK { + vrD = vadda.b(vrD, vrJ, vrK); +} + +define pcodeop vadda.h; + +#lsx.txt vadda.h mask=0x705c8000 +#0x705c8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadda.h vrD, vrJ, vrK is op15_31=0xe0b9 & vrD & vrJ & vrK { + vrD = vadda.h(vrD, vrJ, vrK); +} + +define pcodeop vadda.w; + +#lsx.txt vadda.w mask=0x705d0000 +#0x705d0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadda.w vrD, vrJ, vrK is op15_31=0xe0ba & vrD & vrJ & vrK { + vrD = vadda.w(vrD, vrJ, vrK); +} + +define pcodeop vadda.d; + +#lsx.txt vadda.d mask=0x705d8000 +#0x705d8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadda.d vrD, vrJ, vrK is op15_31=0xe0bb & vrD & vrJ & vrK { + vrD = vadda.d(vrD, vrJ, vrK); +} + +define pcodeop vabsd.b; + +#lsx.txt vabsd.b mask=0x70600000 +#0x70600000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vabsd.b vrD, vrJ, vrK is op15_31=0xe0c0 & vrD & vrJ & vrK { + vrD = vabsd.b(vrD, vrJ, vrK); +} + +define pcodeop vabsd.h; + +#lsx.txt vabsd.h mask=0x70608000 +#0x70608000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vabsd.h vrD, vrJ, vrK is op15_31=0xe0c1 & vrD & vrJ & vrK { + vrD = vabsd.h(vrD, vrJ, vrK); +} + +define pcodeop vabsd.w; + +#lsx.txt vabsd.w mask=0x70610000 +#0x70610000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vabsd.w vrD, vrJ, vrK is op15_31=0xe0c2 & vrD & vrJ & vrK { + vrD = vabsd.w(vrD, vrJ, vrK); +} + +define pcodeop vabsd.d; + +#lsx.txt vabsd.d mask=0x70618000 +#0x70618000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vabsd.d vrD, vrJ, vrK is op15_31=0xe0c3 & vrD & vrJ & vrK { + vrD = vabsd.d(vrD, vrJ, vrK); +} + +define pcodeop vabsd.bu; + +#lsx.txt vabsd.bu mask=0x70620000 +#0x70620000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vabsd.bu vrD, vrJ, vrK is op15_31=0xe0c4 & vrD & vrJ & vrK { + vrD = vabsd.bu(vrD, vrJ, vrK); +} + +define pcodeop vabsd.hu; + +#lsx.txt vabsd.hu mask=0x70628000 +#0x70628000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vabsd.hu vrD, vrJ, vrK is op15_31=0xe0c5 & vrD & vrJ & vrK { + vrD = vabsd.hu(vrD, vrJ, vrK); +} + +define pcodeop vabsd.wu; + +#lsx.txt vabsd.wu mask=0x70630000 +#0x70630000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vabsd.wu vrD, vrJ, vrK is op15_31=0xe0c6 & vrD & vrJ & vrK { + vrD = vabsd.wu(vrD, vrJ, vrK); +} + +define pcodeop vabsd.du; + +#lsx.txt vabsd.du mask=0x70638000 +#0x70638000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vabsd.du vrD, vrJ, vrK is op15_31=0xe0c7 & vrD & vrJ & vrK { + vrD = vabsd.du(vrD, vrJ, vrK); +} + +define pcodeop vavg.b; + +#lsx.txt vavg.b mask=0x70640000 +#0x70640000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavg.b vrD, vrJ, vrK is op15_31=0xe0c8 & vrD & vrJ & vrK { + vrD = vavg.b(vrD, vrJ, vrK); +} + +define pcodeop vavg.h; + +#lsx.txt vavg.h mask=0x70648000 +#0x70648000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavg.h vrD, vrJ, vrK is op15_31=0xe0c9 & vrD & vrJ & vrK { + vrD = vavg.h(vrD, vrJ, vrK); +} + +define pcodeop vavg.w; + +#lsx.txt vavg.w mask=0x70650000 +#0x70650000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavg.w vrD, vrJ, vrK is op15_31=0xe0ca & vrD & vrJ & vrK { + vrD = vavg.w(vrD, vrJ, vrK); +} + +define pcodeop vavg.d; + +#lsx.txt vavg.d mask=0x70658000 +#0x70658000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavg.d vrD, vrJ, vrK is op15_31=0xe0cb & vrD & vrJ & vrK { + vrD = vavg.d(vrD, vrJ, vrK); +} + +define pcodeop vavg.bu; + +#lsx.txt vavg.bu mask=0x70660000 +#0x70660000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavg.bu vrD, vrJ, vrK is op15_31=0xe0cc & vrD & vrJ & vrK { + vrD = vavg.bu(vrD, vrJ, vrK); +} + +define pcodeop vavg.hu; + +#lsx.txt vavg.hu mask=0x70668000 +#0x70668000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavg.hu vrD, vrJ, vrK is op15_31=0xe0cd & vrD & vrJ & vrK { + vrD = vavg.hu(vrD, vrJ, vrK); +} + +define pcodeop vavg.wu; + +#lsx.txt vavg.wu mask=0x70670000 +#0x70670000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavg.wu vrD, vrJ, vrK is op15_31=0xe0ce & vrD & vrJ & vrK { + vrD = vavg.wu(vrD, vrJ, vrK); +} + +define pcodeop vavg.du; + +#lsx.txt vavg.du mask=0x70678000 +#0x70678000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavg.du vrD, vrJ, vrK is op15_31=0xe0cf & vrD & vrJ & vrK { + vrD = vavg.du(vrD, vrJ, vrK); +} + +define pcodeop vavgr.b; + +#lsx.txt vavgr.b mask=0x70680000 +#0x70680000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavgr.b vrD, vrJ, vrK is op15_31=0xe0d0 & vrD & vrJ & vrK { + vrD = vavgr.b(vrD, vrJ, vrK); +} + +define pcodeop vavgr.h; + +#lsx.txt vavgr.h mask=0x70688000 +#0x70688000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavgr.h vrD, vrJ, vrK is op15_31=0xe0d1 & vrD & vrJ & vrK { + vrD = vavgr.h(vrD, vrJ, vrK); +} + +define pcodeop vavgr.w; + +#lsx.txt vavgr.w mask=0x70690000 +#0x70690000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavgr.w vrD, vrJ, vrK is op15_31=0xe0d2 & vrD & vrJ & vrK { + vrD = vavgr.w(vrD, vrJ, vrK); +} + +define pcodeop vavgr.d; + +#lsx.txt vavgr.d mask=0x70698000 +#0x70698000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavgr.d vrD, vrJ, vrK is op15_31=0xe0d3 & vrD & vrJ & vrK { + vrD = vavgr.d(vrD, vrJ, vrK); +} + +define pcodeop vavgr.bu; + +#lsx.txt vavgr.bu mask=0x706a0000 +#0x706a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavgr.bu vrD, vrJ, vrK is op15_31=0xe0d4 & vrD & vrJ & vrK { + vrD = vavgr.bu(vrD, vrJ, vrK); +} + +define pcodeop vavgr.hu; + +#lsx.txt vavgr.hu mask=0x706a8000 +#0x706a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavgr.hu vrD, vrJ, vrK is op15_31=0xe0d5 & vrD & vrJ & vrK { + vrD = vavgr.hu(vrD, vrJ, vrK); +} + +define pcodeop vavgr.wu; + +#lsx.txt vavgr.wu mask=0x706b0000 +#0x706b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavgr.wu vrD, vrJ, vrK is op15_31=0xe0d6 & vrD & vrJ & vrK { + vrD = vavgr.wu(vrD, vrJ, vrK); +} + +define pcodeop vavgr.du; + +#lsx.txt vavgr.du mask=0x706b8000 +#0x706b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vavgr.du vrD, vrJ, vrK is op15_31=0xe0d7 & vrD & vrJ & vrK { + vrD = vavgr.du(vrD, vrJ, vrK); +} + +define pcodeop vmax.b; + +#lsx.txt vmax.b mask=0x70700000 +#0x70700000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmax.b vrD, vrJ, vrK is op15_31=0xe0e0 & vrD & vrJ & vrK { + vrD = vmax.b(vrD, vrJ, vrK); +} + +define pcodeop vmax.h; + +#lsx.txt vmax.h mask=0x70708000 +#0x70708000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmax.h vrD, vrJ, vrK is op15_31=0xe0e1 & vrD & vrJ & vrK { + vrD = vmax.h(vrD, vrJ, vrK); +} + +define pcodeop vmax.w; + +#lsx.txt vmax.w mask=0x70710000 +#0x70710000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmax.w vrD, vrJ, vrK is op15_31=0xe0e2 & vrD & vrJ & vrK { + vrD = vmax.w(vrD, vrJ, vrK); +} + +define pcodeop vmax.d; + +#lsx.txt vmax.d mask=0x70718000 +#0x70718000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmax.d vrD, vrJ, vrK is op15_31=0xe0e3 & vrD & vrJ & vrK { + vrD = vmax.d(vrD, vrJ, vrK); +} + +define pcodeop vmin.b; + +#lsx.txt vmin.b mask=0x70720000 +#0x70720000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmin.b vrD, vrJ, vrK is op15_31=0xe0e4 & vrD & vrJ & vrK { + vrD = vmin.b(vrD, vrJ, vrK); +} + +define pcodeop vmin.h; + +#lsx.txt vmin.h mask=0x70728000 +#0x70728000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmin.h vrD, vrJ, vrK is op15_31=0xe0e5 & vrD & vrJ & vrK { + vrD = vmin.h(vrD, vrJ, vrK); +} + +define pcodeop vmin.w; + +#lsx.txt vmin.w mask=0x70730000 +#0x70730000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmin.w vrD, vrJ, vrK is op15_31=0xe0e6 & vrD & vrJ & vrK { + vrD = vmin.w(vrD, vrJ, vrK); +} + +define pcodeop vmin.d; + +#lsx.txt vmin.d mask=0x70738000 +#0x70738000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmin.d vrD, vrJ, vrK is op15_31=0xe0e7 & vrD & vrJ & vrK { + vrD = vmin.d(vrD, vrJ, vrK); +} + +define pcodeop vmax.bu; + +#lsx.txt vmax.bu mask=0x70740000 +#0x70740000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmax.bu vrD, vrJ, vrK is op15_31=0xe0e8 & vrD & vrJ & vrK { + vrD = vmax.bu(vrD, vrJ, vrK); +} + +define pcodeop vmax.hu; + +#lsx.txt vmax.hu mask=0x70748000 +#0x70748000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmax.hu vrD, vrJ, vrK is op15_31=0xe0e9 & vrD & vrJ & vrK { + vrD = vmax.hu(vrD, vrJ, vrK); +} + +define pcodeop vmax.wu; + +#lsx.txt vmax.wu mask=0x70750000 +#0x70750000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmax.wu vrD, vrJ, vrK is op15_31=0xe0ea & vrD & vrJ & vrK { + vrD = vmax.wu(vrD, vrJ, vrK); +} + +define pcodeop vmax.du; + +#lsx.txt vmax.du mask=0x70758000 +#0x70758000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmax.du vrD, vrJ, vrK is op15_31=0xe0eb & vrD & vrJ & vrK { + vrD = vmax.du(vrD, vrJ, vrK); +} + +define pcodeop vmin.bu; + +#lsx.txt vmin.bu mask=0x70760000 +#0x70760000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmin.bu vrD, vrJ, vrK is op15_31=0xe0ec & vrD & vrJ & vrK { + vrD = vmin.bu(vrD, vrJ, vrK); +} + +define pcodeop vmin.hu; + +#lsx.txt vmin.hu mask=0x70768000 +#0x70768000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmin.hu vrD, vrJ, vrK is op15_31=0xe0ed & vrD & vrJ & vrK { + vrD = vmin.hu(vrD, vrJ, vrK); +} + +define pcodeop vmin.wu; + +#lsx.txt vmin.wu mask=0x70770000 +#0x70770000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmin.wu vrD, vrJ, vrK is op15_31=0xe0ee & vrD & vrJ & vrK { + vrD = vmin.wu(vrD, vrJ, vrK); +} + +define pcodeop vmin.du; + +#lsx.txt vmin.du mask=0x70778000 +#0x70778000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmin.du vrD, vrJ, vrK is op15_31=0xe0ef & vrD & vrJ & vrK { + vrD = vmin.du(vrD, vrJ, vrK); +} + +define pcodeop vmul.b; + +#lsx.txt vmul.b mask=0x70840000 +#0x70840000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmul.b vrD, vrJ, vrK is op15_31=0xe108 & vrD & vrJ & vrK { + vrD = vmul.b(vrD, vrJ, vrK); +} + +define pcodeop vmul.h; + +#lsx.txt vmul.h mask=0x70848000 +#0x70848000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmul.h vrD, vrJ, vrK is op15_31=0xe109 & vrD & vrJ & vrK { + vrD = vmul.h(vrD, vrJ, vrK); +} + +define pcodeop vmul.w; + +#lsx.txt vmul.w mask=0x70850000 +#0x70850000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmul.w vrD, vrJ, vrK is op15_31=0xe10a & vrD & vrJ & vrK { + vrD = vmul.w(vrD, vrJ, vrK); +} + +define pcodeop vmul.d; + +#lsx.txt vmul.d mask=0x70858000 +#0x70858000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmul.d vrD, vrJ, vrK is op15_31=0xe10b & vrD & vrJ & vrK { + vrD = vmul.d(vrD, vrJ, vrK); +} + +define pcodeop vmuh.b; + +#lsx.txt vmuh.b mask=0x70860000 +#0x70860000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmuh.b vrD, vrJ, vrK is op15_31=0xe10c & vrD & vrJ & vrK { + vrD = vmuh.b(vrD, vrJ, vrK); +} + +define pcodeop vmuh.h; + +#lsx.txt vmuh.h mask=0x70868000 +#0x70868000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmuh.h vrD, vrJ, vrK is op15_31=0xe10d & vrD & vrJ & vrK { + vrD = vmuh.h(vrD, vrJ, vrK); +} + +define pcodeop vmuh.w; + +#lsx.txt vmuh.w mask=0x70870000 +#0x70870000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmuh.w vrD, vrJ, vrK is op15_31=0xe10e & vrD & vrJ & vrK { + vrD = vmuh.w(vrD, vrJ, vrK); +} + +define pcodeop vmuh.d; + +#lsx.txt vmuh.d mask=0x70878000 +#0x70878000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmuh.d vrD, vrJ, vrK is op15_31=0xe10f & vrD & vrJ & vrK { + vrD = vmuh.d(vrD, vrJ, vrK); +} + +define pcodeop vmuh.bu; + +#lsx.txt vmuh.bu mask=0x70880000 +#0x70880000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmuh.bu vrD, vrJ, vrK is op15_31=0xe110 & vrD & vrJ & vrK { + vrD = vmuh.bu(vrD, vrJ, vrK); +} + +define pcodeop vmuh.hu; + +#lsx.txt vmuh.hu mask=0x70888000 +#0x70888000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmuh.hu vrD, vrJ, vrK is op15_31=0xe111 & vrD & vrJ & vrK { + vrD = vmuh.hu(vrD, vrJ, vrK); +} + +define pcodeop vmuh.wu; + +#lsx.txt vmuh.wu mask=0x70890000 +#0x70890000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmuh.wu vrD, vrJ, vrK is op15_31=0xe112 & vrD & vrJ & vrK { + vrD = vmuh.wu(vrD, vrJ, vrK); +} + +define pcodeop vmuh.du; + +#lsx.txt vmuh.du mask=0x70898000 +#0x70898000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmuh.du vrD, vrJ, vrK is op15_31=0xe113 & vrD & vrJ & vrK { + vrD = vmuh.du(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.h.b; + +#lsx.txt vmulwev.h.b mask=0x70900000 +#0x70900000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.h.b vrD, vrJ, vrK is op15_31=0xe120 & vrD & vrJ & vrK { + vrD = vmulwev.h.b(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.w.h; + +#lsx.txt vmulwev.w.h mask=0x70908000 +#0x70908000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.w.h vrD, vrJ, vrK is op15_31=0xe121 & vrD & vrJ & vrK { + vrD = vmulwev.w.h(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.d.w; + +#lsx.txt vmulwev.d.w mask=0x70910000 +#0x70910000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.d.w vrD, vrJ, vrK is op15_31=0xe122 & vrD & vrJ & vrK { + vrD = vmulwev.d.w(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.q.d; + +#lsx.txt vmulwev.q.d mask=0x70918000 +#0x70918000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.q.d vrD, vrJ, vrK is op15_31=0xe123 & vrD & vrJ & vrK { + vrD = vmulwev.q.d(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.h.b; + +#lsx.txt vmulwod.h.b mask=0x70920000 +#0x70920000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.h.b vrD, vrJ, vrK is op15_31=0xe124 & vrD & vrJ & vrK { + vrD = vmulwod.h.b(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.w.h; + +#lsx.txt vmulwod.w.h mask=0x70928000 +#0x70928000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.w.h vrD, vrJ, vrK is op15_31=0xe125 & vrD & vrJ & vrK { + vrD = vmulwod.w.h(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.d.w; + +#lsx.txt vmulwod.d.w mask=0x70930000 +#0x70930000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.d.w vrD, vrJ, vrK is op15_31=0xe126 & vrD & vrJ & vrK { + vrD = vmulwod.d.w(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.q.d; + +#lsx.txt vmulwod.q.d mask=0x70938000 +#0x70938000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.q.d vrD, vrJ, vrK is op15_31=0xe127 & vrD & vrJ & vrK { + vrD = vmulwod.q.d(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.h.bu; + +#lsx.txt vmulwev.h.bu mask=0x70980000 +#0x70980000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.h.bu vrD, vrJ, vrK is op15_31=0xe130 & vrD & vrJ & vrK { + vrD = vmulwev.h.bu(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.w.hu; + +#lsx.txt vmulwev.w.hu mask=0x70988000 +#0x70988000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.w.hu vrD, vrJ, vrK is op15_31=0xe131 & vrD & vrJ & vrK { + vrD = vmulwev.w.hu(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.d.wu; + +#lsx.txt vmulwev.d.wu mask=0x70990000 +#0x70990000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.d.wu vrD, vrJ, vrK is op15_31=0xe132 & vrD & vrJ & vrK { + vrD = vmulwev.d.wu(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.q.du; + +#lsx.txt vmulwev.q.du mask=0x70998000 +#0x70998000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.q.du vrD, vrJ, vrK is op15_31=0xe133 & vrD & vrJ & vrK { + vrD = vmulwev.q.du(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.h.bu; + +#lsx.txt vmulwod.h.bu mask=0x709a0000 +#0x709a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.h.bu vrD, vrJ, vrK is op15_31=0xe134 & vrD & vrJ & vrK { + vrD = vmulwod.h.bu(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.w.hu; + +#lsx.txt vmulwod.w.hu mask=0x709a8000 +#0x709a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.w.hu vrD, vrJ, vrK is op15_31=0xe135 & vrD & vrJ & vrK { + vrD = vmulwod.w.hu(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.d.wu; + +#lsx.txt vmulwod.d.wu mask=0x709b0000 +#0x709b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.d.wu vrD, vrJ, vrK is op15_31=0xe136 & vrD & vrJ & vrK { + vrD = vmulwod.d.wu(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.q.du; + +#lsx.txt vmulwod.q.du mask=0x709b8000 +#0x709b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.q.du vrD, vrJ, vrK is op15_31=0xe137 & vrD & vrJ & vrK { + vrD = vmulwod.q.du(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.h.bu.b; + +#lsx.txt vmulwev.h.bu.b mask=0x70a00000 +#0x70a00000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.h.bu.b vrD, vrJ, vrK is op15_31=0xe140 & vrD & vrJ & vrK { + vrD = vmulwev.h.bu.b(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.w.hu.h; + +#lsx.txt vmulwev.w.hu.h mask=0x70a08000 +#0x70a08000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.w.hu.h vrD, vrJ, vrK is op15_31=0xe141 & vrD & vrJ & vrK { + vrD = vmulwev.w.hu.h(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.d.wu.w; + +#lsx.txt vmulwev.d.wu.w mask=0x70a10000 +#0x70a10000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.d.wu.w vrD, vrJ, vrK is op15_31=0xe142 & vrD & vrJ & vrK { + vrD = vmulwev.d.wu.w(vrD, vrJ, vrK); +} + +define pcodeop vmulwev.q.du.d; + +#lsx.txt vmulwev.q.du.d mask=0x70a18000 +#0x70a18000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwev.q.du.d vrD, vrJ, vrK is op15_31=0xe143 & vrD & vrJ & vrK { + vrD = vmulwev.q.du.d(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.h.bu.b; + +#lsx.txt vmulwod.h.bu.b mask=0x70a20000 +#0x70a20000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.h.bu.b vrD, vrJ, vrK is op15_31=0xe144 & vrD & vrJ & vrK { + vrD = vmulwod.h.bu.b(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.w.hu.h; + +#lsx.txt vmulwod.w.hu.h mask=0x70a28000 +#0x70a28000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.w.hu.h vrD, vrJ, vrK is op15_31=0xe145 & vrD & vrJ & vrK { + vrD = vmulwod.w.hu.h(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.d.wu.w; + +#lsx.txt vmulwod.d.wu.w mask=0x70a30000 +#0x70a30000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.d.wu.w vrD, vrJ, vrK is op15_31=0xe146 & vrD & vrJ & vrK { + vrD = vmulwod.d.wu.w(vrD, vrJ, vrK); +} + +define pcodeop vmulwod.q.du.d; + +#lsx.txt vmulwod.q.du.d mask=0x70a38000 +#0x70a38000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmulwod.q.du.d vrD, vrJ, vrK is op15_31=0xe147 & vrD & vrJ & vrK { + vrD = vmulwod.q.du.d(vrD, vrJ, vrK); +} + +define pcodeop vmadd.b; + +#lsx.txt vmadd.b mask=0x70a80000 +#0x70a80000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmadd.b vrD, vrJ, vrK is op15_31=0xe150 & vrD & vrJ & vrK { + vrD = vmadd.b(vrD, vrJ, vrK); +} + +define pcodeop vmadd.h; + +#lsx.txt vmadd.h mask=0x70a88000 +#0x70a88000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmadd.h vrD, vrJ, vrK is op15_31=0xe151 & vrD & vrJ & vrK { + vrD = vmadd.h(vrD, vrJ, vrK); +} + +define pcodeop vmadd.w; + +#lsx.txt vmadd.w mask=0x70a90000 +#0x70a90000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmadd.w vrD, vrJ, vrK is op15_31=0xe152 & vrD & vrJ & vrK { + vrD = vmadd.w(vrD, vrJ, vrK); +} + +define pcodeop vmadd.d; + +#lsx.txt vmadd.d mask=0x70a98000 +#0x70a98000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmadd.d vrD, vrJ, vrK is op15_31=0xe153 & vrD & vrJ & vrK { + vrD = vmadd.d(vrD, vrJ, vrK); +} + +define pcodeop vmsub.b; + +#lsx.txt vmsub.b mask=0x70aa0000 +#0x70aa0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmsub.b vrD, vrJ, vrK is op15_31=0xe154 & vrD & vrJ & vrK { + vrD = vmsub.b(vrD, vrJ, vrK); +} + +define pcodeop vmsub.h; + +#lsx.txt vmsub.h mask=0x70aa8000 +#0x70aa8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmsub.h vrD, vrJ, vrK is op15_31=0xe155 & vrD & vrJ & vrK { + vrD = vmsub.h(vrD, vrJ, vrK); +} + +define pcodeop vmsub.w; + +#lsx.txt vmsub.w mask=0x70ab0000 +#0x70ab0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmsub.w vrD, vrJ, vrK is op15_31=0xe156 & vrD & vrJ & vrK { + vrD = vmsub.w(vrD, vrJ, vrK); +} + +define pcodeop vmsub.d; + +#lsx.txt vmsub.d mask=0x70ab8000 +#0x70ab8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmsub.d vrD, vrJ, vrK is op15_31=0xe157 & vrD & vrJ & vrK { + vrD = vmsub.d(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.h.b; + +#lsx.txt vmaddwev.h.b mask=0x70ac0000 +#0x70ac0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.h.b vrD, vrJ, vrK is op15_31=0xe158 & vrD & vrJ & vrK { + vrD = vmaddwev.h.b(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.w.h; + +#lsx.txt vmaddwev.w.h mask=0x70ac8000 +#0x70ac8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.w.h vrD, vrJ, vrK is op15_31=0xe159 & vrD & vrJ & vrK { + vrD = vmaddwev.w.h(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.d.w; + +#lsx.txt vmaddwev.d.w mask=0x70ad0000 +#0x70ad0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.d.w vrD, vrJ, vrK is op15_31=0xe15a & vrD & vrJ & vrK { + vrD = vmaddwev.d.w(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.q.d; + +#lsx.txt vmaddwev.q.d mask=0x70ad8000 +#0x70ad8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.q.d vrD, vrJ, vrK is op15_31=0xe15b & vrD & vrJ & vrK { + vrD = vmaddwev.q.d(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.h.b; + +#lsx.txt vmaddwod.h.b mask=0x70ae0000 +#0x70ae0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.h.b vrD, vrJ, vrK is op15_31=0xe15c & vrD & vrJ & vrK { + vrD = vmaddwod.h.b(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.w.h; + +#lsx.txt vmaddwod.w.h mask=0x70ae8000 +#0x70ae8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.w.h vrD, vrJ, vrK is op15_31=0xe15d & vrD & vrJ & vrK { + vrD = vmaddwod.w.h(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.d.w; + +#lsx.txt vmaddwod.d.w mask=0x70af0000 +#0x70af0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.d.w vrD, vrJ, vrK is op15_31=0xe15e & vrD & vrJ & vrK { + vrD = vmaddwod.d.w(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.q.d; + +#lsx.txt vmaddwod.q.d mask=0x70af8000 +#0x70af8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.q.d vrD, vrJ, vrK is op15_31=0xe15f & vrD & vrJ & vrK { + vrD = vmaddwod.q.d(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.h.bu; + +#lsx.txt vmaddwev.h.bu mask=0x70b40000 +#0x70b40000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.h.bu vrD, vrJ, vrK is op15_31=0xe168 & vrD & vrJ & vrK { + vrD = vmaddwev.h.bu(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.w.hu; + +#lsx.txt vmaddwev.w.hu mask=0x70b48000 +#0x70b48000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.w.hu vrD, vrJ, vrK is op15_31=0xe169 & vrD & vrJ & vrK { + vrD = vmaddwev.w.hu(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.d.wu; + +#lsx.txt vmaddwev.d.wu mask=0x70b50000 +#0x70b50000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.d.wu vrD, vrJ, vrK is op15_31=0xe16a & vrD & vrJ & vrK { + vrD = vmaddwev.d.wu(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.q.du; + +#lsx.txt vmaddwev.q.du mask=0x70b58000 +#0x70b58000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.q.du vrD, vrJ, vrK is op15_31=0xe16b & vrD & vrJ & vrK { + vrD = vmaddwev.q.du(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.h.bu; + +#lsx.txt vmaddwod.h.bu mask=0x70b60000 +#0x70b60000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.h.bu vrD, vrJ, vrK is op15_31=0xe16c & vrD & vrJ & vrK { + vrD = vmaddwod.h.bu(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.w.hu; + +#lsx.txt vmaddwod.w.hu mask=0x70b68000 +#0x70b68000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.w.hu vrD, vrJ, vrK is op15_31=0xe16d & vrD & vrJ & vrK { + vrD = vmaddwod.w.hu(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.d.wu; + +#lsx.txt vmaddwod.d.wu mask=0x70b70000 +#0x70b70000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.d.wu vrD, vrJ, vrK is op15_31=0xe16e & vrD & vrJ & vrK { + vrD = vmaddwod.d.wu(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.q.du; + +#lsx.txt vmaddwod.q.du mask=0x70b78000 +#0x70b78000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.q.du vrD, vrJ, vrK is op15_31=0xe16f & vrD & vrJ & vrK { + vrD = vmaddwod.q.du(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.h.bu.b; + +#lsx.txt vmaddwev.h.bu.b mask=0x70bc0000 +#0x70bc0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.h.bu.b vrD, vrJ, vrK is op15_31=0xe178 & vrD & vrJ & vrK { + vrD = vmaddwev.h.bu.b(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.w.hu.h; + +#lsx.txt vmaddwev.w.hu.h mask=0x70bc8000 +#0x70bc8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.w.hu.h vrD, vrJ, vrK is op15_31=0xe179 & vrD & vrJ & vrK { + vrD = vmaddwev.w.hu.h(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.d.wu.w; + +#lsx.txt vmaddwev.d.wu.w mask=0x70bd0000 +#0x70bd0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.d.wu.w vrD, vrJ, vrK is op15_31=0xe17a & vrD & vrJ & vrK { + vrD = vmaddwev.d.wu.w(vrD, vrJ, vrK); +} + +define pcodeop vmaddwev.q.du.d; + +#lsx.txt vmaddwev.q.du.d mask=0x70bd8000 +#0x70bd8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwev.q.du.d vrD, vrJ, vrK is op15_31=0xe17b & vrD & vrJ & vrK { + vrD = vmaddwev.q.du.d(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.h.bu.b; + +#lsx.txt vmaddwod.h.bu.b mask=0x70be0000 +#0x70be0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.h.bu.b vrD, vrJ, vrK is op15_31=0xe17c & vrD & vrJ & vrK { + vrD = vmaddwod.h.bu.b(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.w.hu.h; + +#lsx.txt vmaddwod.w.hu.h mask=0x70be8000 +#0x70be8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.w.hu.h vrD, vrJ, vrK is op15_31=0xe17d & vrD & vrJ & vrK { + vrD = vmaddwod.w.hu.h(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.d.wu.w; + +#lsx.txt vmaddwod.d.wu.w mask=0x70bf0000 +#0x70bf0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.d.wu.w vrD, vrJ, vrK is op15_31=0xe17e & vrD & vrJ & vrK { + vrD = vmaddwod.d.wu.w(vrD, vrJ, vrK); +} + +define pcodeop vmaddwod.q.du.d; + +#lsx.txt vmaddwod.q.du.d mask=0x70bf8000 +#0x70bf8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmaddwod.q.du.d vrD, vrJ, vrK is op15_31=0xe17f & vrD & vrJ & vrK { + vrD = vmaddwod.q.du.d(vrD, vrJ, vrK); +} + +define pcodeop vdiv.b; + +#lsx.txt vdiv.b mask=0x70e00000 +#0x70e00000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vdiv.b vrD, vrJ, vrK is op15_31=0xe1c0 & vrD & vrJ & vrK { + vrD = vdiv.b(vrD, vrJ, vrK); +} + +define pcodeop vdiv.h; + +#lsx.txt vdiv.h mask=0x70e08000 +#0x70e08000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vdiv.h vrD, vrJ, vrK is op15_31=0xe1c1 & vrD & vrJ & vrK { + vrD = vdiv.h(vrD, vrJ, vrK); +} + +define pcodeop vdiv.w; + +#lsx.txt vdiv.w mask=0x70e10000 +#0x70e10000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vdiv.w vrD, vrJ, vrK is op15_31=0xe1c2 & vrD & vrJ & vrK { + vrD = vdiv.w(vrD, vrJ, vrK); +} + +define pcodeop vdiv.d; + +#lsx.txt vdiv.d mask=0x70e18000 +#0x70e18000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vdiv.d vrD, vrJ, vrK is op15_31=0xe1c3 & vrD & vrJ & vrK { + vrD = vdiv.d(vrD, vrJ, vrK); +} + +define pcodeop vmod.b; + +#lsx.txt vmod.b mask=0x70e20000 +#0x70e20000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmod.b vrD, vrJ, vrK is op15_31=0xe1c4 & vrD & vrJ & vrK { + vrD = vmod.b(vrD, vrJ, vrK); +} + +define pcodeop vmod.h; + +#lsx.txt vmod.h mask=0x70e28000 +#0x70e28000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmod.h vrD, vrJ, vrK is op15_31=0xe1c5 & vrD & vrJ & vrK { + vrD = vmod.h(vrD, vrJ, vrK); +} + +define pcodeop vmod.w; + +#lsx.txt vmod.w mask=0x70e30000 +#0x70e30000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmod.w vrD, vrJ, vrK is op15_31=0xe1c6 & vrD & vrJ & vrK { + vrD = vmod.w(vrD, vrJ, vrK); +} + +define pcodeop vmod.d; + +#lsx.txt vmod.d mask=0x70e38000 +#0x70e38000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmod.d vrD, vrJ, vrK is op15_31=0xe1c7 & vrD & vrJ & vrK { + vrD = vmod.d(vrD, vrJ, vrK); +} + +define pcodeop vdiv.bu; + +#lsx.txt vdiv.bu mask=0x70e40000 +#0x70e40000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vdiv.bu vrD, vrJ, vrK is op15_31=0xe1c8 & vrD & vrJ & vrK { + vrD = vdiv.bu(vrD, vrJ, vrK); +} + +define pcodeop vdiv.hu; + +#lsx.txt vdiv.hu mask=0x70e48000 +#0x70e48000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vdiv.hu vrD, vrJ, vrK is op15_31=0xe1c9 & vrD & vrJ & vrK { + vrD = vdiv.hu(vrD, vrJ, vrK); +} + +define pcodeop vdiv.wu; + +#lsx.txt vdiv.wu mask=0x70e50000 +#0x70e50000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vdiv.wu vrD, vrJ, vrK is op15_31=0xe1ca & vrD & vrJ & vrK { + vrD = vdiv.wu(vrD, vrJ, vrK); +} + +define pcodeop vdiv.du; + +#lsx.txt vdiv.du mask=0x70e58000 +#0x70e58000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vdiv.du vrD, vrJ, vrK is op15_31=0xe1cb & vrD & vrJ & vrK { + vrD = vdiv.du(vrD, vrJ, vrK); +} + +define pcodeop vmod.bu; + +#lsx.txt vmod.bu mask=0x70e60000 +#0x70e60000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmod.bu vrD, vrJ, vrK is op15_31=0xe1cc & vrD & vrJ & vrK { + vrD = vmod.bu(vrD, vrJ, vrK); +} + +define pcodeop vmod.hu; + +#lsx.txt vmod.hu mask=0x70e68000 +#0x70e68000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmod.hu vrD, vrJ, vrK is op15_31=0xe1cd & vrD & vrJ & vrK { + vrD = vmod.hu(vrD, vrJ, vrK); +} + +define pcodeop vmod.wu; + +#lsx.txt vmod.wu mask=0x70e70000 +#0x70e70000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmod.wu vrD, vrJ, vrK is op15_31=0xe1ce & vrD & vrJ & vrK { + vrD = vmod.wu(vrD, vrJ, vrK); +} + +define pcodeop vmod.du; + +#lsx.txt vmod.du mask=0x70e78000 +#0x70e78000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vmod.du vrD, vrJ, vrK is op15_31=0xe1cf & vrD & vrJ & vrK { + vrD = vmod.du(vrD, vrJ, vrK); +} + +define pcodeop vsll.b; + +#lsx.txt vsll.b mask=0x70e80000 +#0x70e80000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsll.b vrD, vrJ, vrK is op15_31=0xe1d0 & vrD & vrJ & vrK { + vrD = vsll.b(vrD, vrJ, vrK); +} + +define pcodeop vsll.h; + +#lsx.txt vsll.h mask=0x70e88000 +#0x70e88000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsll.h vrD, vrJ, vrK is op15_31=0xe1d1 & vrD & vrJ & vrK { + vrD = vsll.h(vrD, vrJ, vrK); +} + +define pcodeop vsll.w; + +#lsx.txt vsll.w mask=0x70e90000 +#0x70e90000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsll.w vrD, vrJ, vrK is op15_31=0xe1d2 & vrD & vrJ & vrK { + vrD = vsll.w(vrD, vrJ, vrK); +} + +define pcodeop vsll.d; + +#lsx.txt vsll.d mask=0x70e98000 +#0x70e98000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsll.d vrD, vrJ, vrK is op15_31=0xe1d3 & vrD & vrJ & vrK { + vrD = vsll.d(vrD, vrJ, vrK); +} + +define pcodeop vsrl.b; + +#lsx.txt vsrl.b mask=0x70ea0000 +#0x70ea0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrl.b vrD, vrJ, vrK is op15_31=0xe1d4 & vrD & vrJ & vrK { + vrD = vsrl.b(vrD, vrJ, vrK); +} + +define pcodeop vsrl.h; + +#lsx.txt vsrl.h mask=0x70ea8000 +#0x70ea8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrl.h vrD, vrJ, vrK is op15_31=0xe1d5 & vrD & vrJ & vrK { + vrD = vsrl.h(vrD, vrJ, vrK); +} + +define pcodeop vsrl.w; + +#lsx.txt vsrl.w mask=0x70eb0000 +#0x70eb0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrl.w vrD, vrJ, vrK is op15_31=0xe1d6 & vrD & vrJ & vrK { + vrD = vsrl.w(vrD, vrJ, vrK); +} + +define pcodeop vsrl.d; + +#lsx.txt vsrl.d mask=0x70eb8000 +#0x70eb8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrl.d vrD, vrJ, vrK is op15_31=0xe1d7 & vrD & vrJ & vrK { + vrD = vsrl.d(vrD, vrJ, vrK); +} + +define pcodeop vsra.b; + +#lsx.txt vsra.b mask=0x70ec0000 +#0x70ec0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsra.b vrD, vrJ, vrK is op15_31=0xe1d8 & vrD & vrJ & vrK { + vrD = vsra.b(vrD, vrJ, vrK); +} + +define pcodeop vsra.h; + +#lsx.txt vsra.h mask=0x70ec8000 +#0x70ec8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsra.h vrD, vrJ, vrK is op15_31=0xe1d9 & vrD & vrJ & vrK { + vrD = vsra.h(vrD, vrJ, vrK); +} + +define pcodeop vsra.w; + +#lsx.txt vsra.w mask=0x70ed0000 +#0x70ed0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsra.w vrD, vrJ, vrK is op15_31=0xe1da & vrD & vrJ & vrK { + vrD = vsra.w(vrD, vrJ, vrK); +} + +define pcodeop vsra.d; + +#lsx.txt vsra.d mask=0x70ed8000 +#0x70ed8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsra.d vrD, vrJ, vrK is op15_31=0xe1db & vrD & vrJ & vrK { + vrD = vsra.d(vrD, vrJ, vrK); +} + +define pcodeop vrotr.b; + +#lsx.txt vrotr.b mask=0x70ee0000 +#0x70ee0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vrotr.b vrD, vrJ, vrK is op15_31=0xe1dc & vrD & vrJ & vrK { + vrD = vrotr.b(vrD, vrJ, vrK); +} + +define pcodeop vrotr.h; + +#lsx.txt vrotr.h mask=0x70ee8000 +#0x70ee8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vrotr.h vrD, vrJ, vrK is op15_31=0xe1dd & vrD & vrJ & vrK { + vrD = vrotr.h(vrD, vrJ, vrK); +} + +define pcodeop vrotr.w; + +#lsx.txt vrotr.w mask=0x70ef0000 +#0x70ef0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vrotr.w vrD, vrJ, vrK is op15_31=0xe1de & vrD & vrJ & vrK { + vrD = vrotr.w(vrD, vrJ, vrK); +} + +define pcodeop vrotr.d; + +#lsx.txt vrotr.d mask=0x70ef8000 +#0x70ef8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vrotr.d vrD, vrJ, vrK is op15_31=0xe1df & vrD & vrJ & vrK { + vrD = vrotr.d(vrD, vrJ, vrK); +} + +define pcodeop vsrlr.b; + +#lsx.txt vsrlr.b mask=0x70f00000 +#0x70f00000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrlr.b vrD, vrJ, vrK is op15_31=0xe1e0 & vrD & vrJ & vrK { + vrD = vsrlr.b(vrD, vrJ, vrK); +} + +define pcodeop vsrlr.h; + +#lsx.txt vsrlr.h mask=0x70f08000 +#0x70f08000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrlr.h vrD, vrJ, vrK is op15_31=0xe1e1 & vrD & vrJ & vrK { + vrD = vsrlr.h(vrD, vrJ, vrK); +} + +define pcodeop vsrlr.w; + +#lsx.txt vsrlr.w mask=0x70f10000 +#0x70f10000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrlr.w vrD, vrJ, vrK is op15_31=0xe1e2 & vrD & vrJ & vrK { + vrD = vsrlr.w(vrD, vrJ, vrK); +} + +define pcodeop vsrlr.d; + +#lsx.txt vsrlr.d mask=0x70f18000 +#0x70f18000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrlr.d vrD, vrJ, vrK is op15_31=0xe1e3 & vrD & vrJ & vrK { + vrD = vsrlr.d(vrD, vrJ, vrK); +} + +define pcodeop vsrar.b; + +#lsx.txt vsrar.b mask=0x70f20000 +#0x70f20000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrar.b vrD, vrJ, vrK is op15_31=0xe1e4 & vrD & vrJ & vrK { + vrD = vsrar.b(vrD, vrJ, vrK); +} + +define pcodeop vsrar.h; + +#lsx.txt vsrar.h mask=0x70f28000 +#0x70f28000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrar.h vrD, vrJ, vrK is op15_31=0xe1e5 & vrD & vrJ & vrK { + vrD = vsrar.h(vrD, vrJ, vrK); +} + +define pcodeop vsrar.w; + +#lsx.txt vsrar.w mask=0x70f30000 +#0x70f30000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrar.w vrD, vrJ, vrK is op15_31=0xe1e6 & vrD & vrJ & vrK { + vrD = vsrar.w(vrD, vrJ, vrK); +} + +define pcodeop vsrar.d; + +#lsx.txt vsrar.d mask=0x70f38000 +#0x70f38000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrar.d vrD, vrJ, vrK is op15_31=0xe1e7 & vrD & vrJ & vrK { + vrD = vsrar.d(vrD, vrJ, vrK); +} + +define pcodeop vsrln.b.h; + +#lsx.txt vsrln.b.h mask=0x70f48000 +#0x70f48000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrln.b.h vrD, vrJ, vrK is op15_31=0xe1e9 & vrD & vrJ & vrK { + vrD = vsrln.b.h(vrD, vrJ, vrK); +} + +define pcodeop vsrln.h.w; + +#lsx.txt vsrln.h.w mask=0x70f50000 +#0x70f50000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrln.h.w vrD, vrJ, vrK is op15_31=0xe1ea & vrD & vrJ & vrK { + vrD = vsrln.h.w(vrD, vrJ, vrK); +} + +define pcodeop vsrln.w.d; + +#lsx.txt vsrln.w.d mask=0x70f58000 +#0x70f58000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrln.w.d vrD, vrJ, vrK is op15_31=0xe1eb & vrD & vrJ & vrK { + vrD = vsrln.w.d(vrD, vrJ, vrK); +} + +define pcodeop vsran.b.h; + +#lsx.txt vsran.b.h mask=0x70f68000 +#0x70f68000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsran.b.h vrD, vrJ, vrK is op15_31=0xe1ed & vrD & vrJ & vrK { + vrD = vsran.b.h(vrD, vrJ, vrK); +} + +define pcodeop vsran.h.w; + +#lsx.txt vsran.h.w mask=0x70f70000 +#0x70f70000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsran.h.w vrD, vrJ, vrK is op15_31=0xe1ee & vrD & vrJ & vrK { + vrD = vsran.h.w(vrD, vrJ, vrK); +} + +define pcodeop vsran.w.d; + +#lsx.txt vsran.w.d mask=0x70f78000 +#0x70f78000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsran.w.d vrD, vrJ, vrK is op15_31=0xe1ef & vrD & vrJ & vrK { + vrD = vsran.w.d(vrD, vrJ, vrK); +} + +define pcodeop vsrlrn.b.h; + +#lsx.txt vsrlrn.b.h mask=0x70f88000 +#0x70f88000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrlrn.b.h vrD, vrJ, vrK is op15_31=0xe1f1 & vrD & vrJ & vrK { + vrD = vsrlrn.b.h(vrD, vrJ, vrK); +} + +define pcodeop vsrlrn.h.w; + +#lsx.txt vsrlrn.h.w mask=0x70f90000 +#0x70f90000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrlrn.h.w vrD, vrJ, vrK is op15_31=0xe1f2 & vrD & vrJ & vrK { + vrD = vsrlrn.h.w(vrD, vrJ, vrK); +} + +define pcodeop vsrlrn.w.d; + +#lsx.txt vsrlrn.w.d mask=0x70f98000 +#0x70f98000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrlrn.w.d vrD, vrJ, vrK is op15_31=0xe1f3 & vrD & vrJ & vrK { + vrD = vsrlrn.w.d(vrD, vrJ, vrK); +} + +define pcodeop vsrarn.b.h; + +#lsx.txt vsrarn.b.h mask=0x70fa8000 +#0x70fa8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrarn.b.h vrD, vrJ, vrK is op15_31=0xe1f5 & vrD & vrJ & vrK { + vrD = vsrarn.b.h(vrD, vrJ, vrK); +} + +define pcodeop vsrarn.h.w; + +#lsx.txt vsrarn.h.w mask=0x70fb0000 +#0x70fb0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrarn.h.w vrD, vrJ, vrK is op15_31=0xe1f6 & vrD & vrJ & vrK { + vrD = vsrarn.h.w(vrD, vrJ, vrK); +} + +define pcodeop vsrarn.w.d; + +#lsx.txt vsrarn.w.d mask=0x70fb8000 +#0x70fb8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsrarn.w.d vrD, vrJ, vrK is op15_31=0xe1f7 & vrD & vrJ & vrK { + vrD = vsrarn.w.d(vrD, vrJ, vrK); +} + +define pcodeop vssrln.b.h; + +#lsx.txt vssrln.b.h mask=0x70fc8000 +#0x70fc8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrln.b.h vrD, vrJ, vrK is op15_31=0xe1f9 & vrD & vrJ & vrK { + vrD = vssrln.b.h(vrD, vrJ, vrK); +} + +define pcodeop vssrln.h.w; + +#lsx.txt vssrln.h.w mask=0x70fd0000 +#0x70fd0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrln.h.w vrD, vrJ, vrK is op15_31=0xe1fa & vrD & vrJ & vrK { + vrD = vssrln.h.w(vrD, vrJ, vrK); +} + +define pcodeop vssrln.w.d; + +#lsx.txt vssrln.w.d mask=0x70fd8000 +#0x70fd8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrln.w.d vrD, vrJ, vrK is op15_31=0xe1fb & vrD & vrJ & vrK { + vrD = vssrln.w.d(vrD, vrJ, vrK); +} + +define pcodeop vssran.b.h; + +#lsx.txt vssran.b.h mask=0x70fe8000 +#0x70fe8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssran.b.h vrD, vrJ, vrK is op15_31=0xe1fd & vrD & vrJ & vrK { + vrD = vssran.b.h(vrD, vrJ, vrK); +} + +define pcodeop vssran.h.w; + +#lsx.txt vssran.h.w mask=0x70ff0000 +#0x70ff0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssran.h.w vrD, vrJ, vrK is op15_31=0xe1fe & vrD & vrJ & vrK { + vrD = vssran.h.w(vrD, vrJ, vrK); +} + +define pcodeop vssran.w.d; + +#lsx.txt vssran.w.d mask=0x70ff8000 +#0x70ff8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssran.w.d vrD, vrJ, vrK is op15_31=0xe1ff & vrD & vrJ & vrK { + vrD = vssran.w.d(vrD, vrJ, vrK); +} + +define pcodeop vssrlrn.b.h; + +#lsx.txt vssrlrn.b.h mask=0x71008000 +#0x71008000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrlrn.b.h vrD, vrJ, vrK is op15_31=0xe201 & vrD & vrJ & vrK { + vrD = vssrlrn.b.h(vrD, vrJ, vrK); +} + +define pcodeop vssrlrn.h.w; + +#lsx.txt vssrlrn.h.w mask=0x71010000 +#0x71010000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrlrn.h.w vrD, vrJ, vrK is op15_31=0xe202 & vrD & vrJ & vrK { + vrD = vssrlrn.h.w(vrD, vrJ, vrK); +} + +define pcodeop vssrlrn.w.d; + +#lsx.txt vssrlrn.w.d mask=0x71018000 +#0x71018000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrlrn.w.d vrD, vrJ, vrK is op15_31=0xe203 & vrD & vrJ & vrK { + vrD = vssrlrn.w.d(vrD, vrJ, vrK); +} + +define pcodeop vssrarn.b.h; + +#lsx.txt vssrarn.b.h mask=0x71028000 +#0x71028000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrarn.b.h vrD, vrJ, vrK is op15_31=0xe205 & vrD & vrJ & vrK { + vrD = vssrarn.b.h(vrD, vrJ, vrK); +} + +define pcodeop vssrarn.h.w; + +#lsx.txt vssrarn.h.w mask=0x71030000 +#0x71030000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrarn.h.w vrD, vrJ, vrK is op15_31=0xe206 & vrD & vrJ & vrK { + vrD = vssrarn.h.w(vrD, vrJ, vrK); +} + +define pcodeop vssrarn.w.d; + +#lsx.txt vssrarn.w.d mask=0x71038000 +#0x71038000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrarn.w.d vrD, vrJ, vrK is op15_31=0xe207 & vrD & vrJ & vrK { + vrD = vssrarn.w.d(vrD, vrJ, vrK); +} + +define pcodeop vssrln.bu.h; + +#lsx.txt vssrln.bu.h mask=0x71048000 +#0x71048000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrln.bu.h vrD, vrJ, vrK is op15_31=0xe209 & vrD & vrJ & vrK { + vrD = vssrln.bu.h(vrD, vrJ, vrK); +} + +define pcodeop vssrln.hu.w; + +#lsx.txt vssrln.hu.w mask=0x71050000 +#0x71050000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrln.hu.w vrD, vrJ, vrK is op15_31=0xe20a & vrD & vrJ & vrK { + vrD = vssrln.hu.w(vrD, vrJ, vrK); +} + +define pcodeop vssrln.wu.d; + +#lsx.txt vssrln.wu.d mask=0x71058000 +#0x71058000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrln.wu.d vrD, vrJ, vrK is op15_31=0xe20b & vrD & vrJ & vrK { + vrD = vssrln.wu.d(vrD, vrJ, vrK); +} + +define pcodeop vssran.bu.h; + +#lsx.txt vssran.bu.h mask=0x71068000 +#0x71068000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssran.bu.h vrD, vrJ, vrK is op15_31=0xe20d & vrD & vrJ & vrK { + vrD = vssran.bu.h(vrD, vrJ, vrK); +} + +define pcodeop vssran.hu.w; + +#lsx.txt vssran.hu.w mask=0x71070000 +#0x71070000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssran.hu.w vrD, vrJ, vrK is op15_31=0xe20e & vrD & vrJ & vrK { + vrD = vssran.hu.w(vrD, vrJ, vrK); +} + +define pcodeop vssran.wu.d; + +#lsx.txt vssran.wu.d mask=0x71078000 +#0x71078000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssran.wu.d vrD, vrJ, vrK is op15_31=0xe20f & vrD & vrJ & vrK { + vrD = vssran.wu.d(vrD, vrJ, vrK); +} + +define pcodeop vssrlrn.bu.h; + +#lsx.txt vssrlrn.bu.h mask=0x71088000 +#0x71088000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrlrn.bu.h vrD, vrJ, vrK is op15_31=0xe211 & vrD & vrJ & vrK { + vrD = vssrlrn.bu.h(vrD, vrJ, vrK); +} + +define pcodeop vssrlrn.hu.w; + +#lsx.txt vssrlrn.hu.w mask=0x71090000 +#0x71090000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrlrn.hu.w vrD, vrJ, vrK is op15_31=0xe212 & vrD & vrJ & vrK { + vrD = vssrlrn.hu.w(vrD, vrJ, vrK); +} + +define pcodeop vssrlrn.wu.d; + +#lsx.txt vssrlrn.wu.d mask=0x71098000 +#0x71098000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrlrn.wu.d vrD, vrJ, vrK is op15_31=0xe213 & vrD & vrJ & vrK { + vrD = vssrlrn.wu.d(vrD, vrJ, vrK); +} + +define pcodeop vssrarn.bu.h; + +#lsx.txt vssrarn.bu.h mask=0x710a8000 +#0x710a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrarn.bu.h vrD, vrJ, vrK is op15_31=0xe215 & vrD & vrJ & vrK { + vrD = vssrarn.bu.h(vrD, vrJ, vrK); +} + +define pcodeop vssrarn.hu.w; + +#lsx.txt vssrarn.hu.w mask=0x710b0000 +#0x710b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrarn.hu.w vrD, vrJ, vrK is op15_31=0xe216 & vrD & vrJ & vrK { + vrD = vssrarn.hu.w(vrD, vrJ, vrK); +} + +define pcodeop vssrarn.wu.d; + +#lsx.txt vssrarn.wu.d mask=0x710b8000 +#0x710b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vssrarn.wu.d vrD, vrJ, vrK is op15_31=0xe217 & vrD & vrJ & vrK { + vrD = vssrarn.wu.d(vrD, vrJ, vrK); +} + +define pcodeop vbitclr.b; + +#lsx.txt vbitclr.b mask=0x710c0000 +#0x710c0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitclr.b vrD, vrJ, vrK is op15_31=0xe218 & vrD & vrJ & vrK { + vrD = vbitclr.b(vrD, vrJ, vrK); +} + +define pcodeop vbitclr.h; + +#lsx.txt vbitclr.h mask=0x710c8000 +#0x710c8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitclr.h vrD, vrJ, vrK is op15_31=0xe219 & vrD & vrJ & vrK { + vrD = vbitclr.h(vrD, vrJ, vrK); +} + +define pcodeop vbitclr.w; + +#lsx.txt vbitclr.w mask=0x710d0000 +#0x710d0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitclr.w vrD, vrJ, vrK is op15_31=0xe21a & vrD & vrJ & vrK { + vrD = vbitclr.w(vrD, vrJ, vrK); +} + +define pcodeop vbitclr.d; + +#lsx.txt vbitclr.d mask=0x710d8000 +#0x710d8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitclr.d vrD, vrJ, vrK is op15_31=0xe21b & vrD & vrJ & vrK { + vrD = vbitclr.d(vrD, vrJ, vrK); +} + +define pcodeop vbitset.b; + +#lsx.txt vbitset.b mask=0x710e0000 +#0x710e0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitset.b vrD, vrJ, vrK is op15_31=0xe21c & vrD & vrJ & vrK { + vrD = vbitset.b(vrD, vrJ, vrK); +} + +define pcodeop vbitset.h; + +#lsx.txt vbitset.h mask=0x710e8000 +#0x710e8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitset.h vrD, vrJ, vrK is op15_31=0xe21d & vrD & vrJ & vrK { + vrD = vbitset.h(vrD, vrJ, vrK); +} + +define pcodeop vbitset.w; + +#lsx.txt vbitset.w mask=0x710f0000 +#0x710f0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitset.w vrD, vrJ, vrK is op15_31=0xe21e & vrD & vrJ & vrK { + vrD = vbitset.w(vrD, vrJ, vrK); +} + +define pcodeop vbitset.d; + +#lsx.txt vbitset.d mask=0x710f8000 +#0x710f8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitset.d vrD, vrJ, vrK is op15_31=0xe21f & vrD & vrJ & vrK { + vrD = vbitset.d(vrD, vrJ, vrK); +} + +define pcodeop vbitrev.b; + +#lsx.txt vbitrev.b mask=0x71100000 +#0x71100000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitrev.b vrD, vrJ, vrK is op15_31=0xe220 & vrD & vrJ & vrK { + vrD = vbitrev.b(vrD, vrJ, vrK); +} + +define pcodeop vbitrev.h; + +#lsx.txt vbitrev.h mask=0x71108000 +#0x71108000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitrev.h vrD, vrJ, vrK is op15_31=0xe221 & vrD & vrJ & vrK { + vrD = vbitrev.h(vrD, vrJ, vrK); +} + +define pcodeop vbitrev.w; + +#lsx.txt vbitrev.w mask=0x71110000 +#0x71110000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitrev.w vrD, vrJ, vrK is op15_31=0xe222 & vrD & vrJ & vrK { + vrD = vbitrev.w(vrD, vrJ, vrK); +} + +define pcodeop vbitrev.d; + +#lsx.txt vbitrev.d mask=0x71118000 +#0x71118000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vbitrev.d vrD, vrJ, vrK is op15_31=0xe223 & vrD & vrJ & vrK { + vrD = vbitrev.d(vrD, vrJ, vrK); +} + +define pcodeop vpackev.b; + +#lsx.txt vpackev.b mask=0x71160000 +#0x71160000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpackev.b vrD, vrJ, vrK is op15_31=0xe22c & vrD & vrJ & vrK { + vrD = vpackev.b(vrD, vrJ, vrK); +} + +define pcodeop vpackev.h; + +#lsx.txt vpackev.h mask=0x71168000 +#0x71168000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpackev.h vrD, vrJ, vrK is op15_31=0xe22d & vrD & vrJ & vrK { + vrD = vpackev.h(vrD, vrJ, vrK); +} + +define pcodeop vpackev.w; + +#lsx.txt vpackev.w mask=0x71170000 +#0x71170000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpackev.w vrD, vrJ, vrK is op15_31=0xe22e & vrD & vrJ & vrK { + vrD = vpackev.w(vrD, vrJ, vrK); +} + +define pcodeop vpackev.d; + +#lsx.txt vpackev.d mask=0x71178000 +#0x71178000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpackev.d vrD, vrJ, vrK is op15_31=0xe22f & vrD & vrJ & vrK { + vrD = vpackev.d(vrD, vrJ, vrK); +} + +define pcodeop vpackod.b; + +#lsx.txt vpackod.b mask=0x71180000 +#0x71180000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpackod.b vrD, vrJ, vrK is op15_31=0xe230 & vrD & vrJ & vrK { + vrD = vpackod.b(vrD, vrJ, vrK); +} + +define pcodeop vpackod.h; + +#lsx.txt vpackod.h mask=0x71188000 +#0x71188000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpackod.h vrD, vrJ, vrK is op15_31=0xe231 & vrD & vrJ & vrK { + vrD = vpackod.h(vrD, vrJ, vrK); +} + +define pcodeop vpackod.w; + +#lsx.txt vpackod.w mask=0x71190000 +#0x71190000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpackod.w vrD, vrJ, vrK is op15_31=0xe232 & vrD & vrJ & vrK { + vrD = vpackod.w(vrD, vrJ, vrK); +} + +define pcodeop vpackod.d; + +#lsx.txt vpackod.d mask=0x71198000 +#0x71198000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpackod.d vrD, vrJ, vrK is op15_31=0xe233 & vrD & vrJ & vrK { + vrD = vpackod.d(vrD, vrJ, vrK); +} + +define pcodeop vilvl.b; + +#lsx.txt vilvl.b mask=0x711a0000 +#0x711a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vilvl.b vrD, vrJ, vrK is op15_31=0xe234 & vrD & vrJ & vrK { + vrD = vilvl.b(vrD, vrJ, vrK); +} + +define pcodeop vilvl.h; + +#lsx.txt vilvl.h mask=0x711a8000 +#0x711a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vilvl.h vrD, vrJ, vrK is op15_31=0xe235 & vrD & vrJ & vrK { + vrD = vilvl.h(vrD, vrJ, vrK); +} + +define pcodeop vilvl.w; + +#lsx.txt vilvl.w mask=0x711b0000 +#0x711b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vilvl.w vrD, vrJ, vrK is op15_31=0xe236 & vrD & vrJ & vrK { + vrD = vilvl.w(vrD, vrJ, vrK); +} + +define pcodeop vilvl.d; + +#lsx.txt vilvl.d mask=0x711b8000 +#0x711b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vilvl.d vrD, vrJ, vrK is op15_31=0xe237 & vrD & vrJ & vrK { + vrD = vilvl.d(vrD, vrJ, vrK); +} + +define pcodeop vilvh.b; + +#lsx.txt vilvh.b mask=0x711c0000 +#0x711c0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vilvh.b vrD, vrJ, vrK is op15_31=0xe238 & vrD & vrJ & vrK { + vrD = vilvh.b(vrD, vrJ, vrK); +} + +define pcodeop vilvh.h; + +#lsx.txt vilvh.h mask=0x711c8000 +#0x711c8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vilvh.h vrD, vrJ, vrK is op15_31=0xe239 & vrD & vrJ & vrK { + vrD = vilvh.h(vrD, vrJ, vrK); +} + +define pcodeop vilvh.w; + +#lsx.txt vilvh.w mask=0x711d0000 +#0x711d0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vilvh.w vrD, vrJ, vrK is op15_31=0xe23a & vrD & vrJ & vrK { + vrD = vilvh.w(vrD, vrJ, vrK); +} + +define pcodeop vilvh.d; + +#lsx.txt vilvh.d mask=0x711d8000 +#0x711d8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vilvh.d vrD, vrJ, vrK is op15_31=0xe23b & vrD & vrJ & vrK { + vrD = vilvh.d(vrD, vrJ, vrK); +} + +define pcodeop vpickev.b; + +#lsx.txt vpickev.b mask=0x711e0000 +#0x711e0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpickev.b vrD, vrJ, vrK is op15_31=0xe23c & vrD & vrJ & vrK { + vrD = vpickev.b(vrD, vrJ, vrK); +} + +define pcodeop vpickev.h; + +#lsx.txt vpickev.h mask=0x711e8000 +#0x711e8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpickev.h vrD, vrJ, vrK is op15_31=0xe23d & vrD & vrJ & vrK { + vrD = vpickev.h(vrD, vrJ, vrK); +} + +define pcodeop vpickev.w; + +#lsx.txt vpickev.w mask=0x711f0000 +#0x711f0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpickev.w vrD, vrJ, vrK is op15_31=0xe23e & vrD & vrJ & vrK { + vrD = vpickev.w(vrD, vrJ, vrK); +} + +define pcodeop vpickev.d; + +#lsx.txt vpickev.d mask=0x711f8000 +#0x711f8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpickev.d vrD, vrJ, vrK is op15_31=0xe23f & vrD & vrJ & vrK { + vrD = vpickev.d(vrD, vrJ, vrK); +} + +define pcodeop vpickod.b; + +#lsx.txt vpickod.b mask=0x71200000 +#0x71200000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpickod.b vrD, vrJ, vrK is op15_31=0xe240 & vrD & vrJ & vrK { + vrD = vpickod.b(vrD, vrJ, vrK); +} + +define pcodeop vpickod.h; + +#lsx.txt vpickod.h mask=0x71208000 +#0x71208000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpickod.h vrD, vrJ, vrK is op15_31=0xe241 & vrD & vrJ & vrK { + vrD = vpickod.h(vrD, vrJ, vrK); +} + +define pcodeop vpickod.w; + +#lsx.txt vpickod.w mask=0x71210000 +#0x71210000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpickod.w vrD, vrJ, vrK is op15_31=0xe242 & vrD & vrJ & vrK { + vrD = vpickod.w(vrD, vrJ, vrK); +} + +define pcodeop vpickod.d; + +#lsx.txt vpickod.d mask=0x71218000 +#0x71218000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vpickod.d vrD, vrJ, vrK is op15_31=0xe243 & vrD & vrJ & vrK { + vrD = vpickod.d(vrD, vrJ, vrK); +} + +define pcodeop vreplve.b; + +#lsx.txt vreplve.b mask=0x71220000 +#0x71220000 0xffff8000 v0:5,v5:5, r10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'reg10_5_s0'] +:vreplve.b vrD, vrJ, RKsrc is op15_31=0xe244 & vrD & vrJ & RKsrc { + vrD = vreplve.b(vrD, vrJ, RKsrc); +} + +define pcodeop vreplve.h; + +#lsx.txt vreplve.h mask=0x71228000 +#0x71228000 0xffff8000 v0:5,v5:5, r10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'reg10_5_s0'] +:vreplve.h vrD, vrJ, RKsrc is op15_31=0xe245 & vrD & vrJ & RKsrc { + vrD = vreplve.h(vrD, vrJ, RKsrc); +} + +define pcodeop vreplve.w; + +#lsx.txt vreplve.w mask=0x71230000 +#0x71230000 0xffff8000 v0:5,v5:5, r10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'reg10_5_s0'] +:vreplve.w vrD, vrJ, RKsrc is op15_31=0xe246 & vrD & vrJ & RKsrc { + vrD = vreplve.w(vrD, vrJ, RKsrc); +} + +define pcodeop vreplve.d; + +#lsx.txt vreplve.d mask=0x71238000 +#0x71238000 0xffff8000 v0:5,v5:5, r10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'reg10_5_s0'] +:vreplve.d vrD, vrJ, RKsrc is op15_31=0xe247 & vrD & vrJ & RKsrc { + vrD = vreplve.d(vrD, vrJ, RKsrc); +} + +define pcodeop vand.v; + +#lsx.txt vand.v mask=0x71260000 +#0x71260000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vand.v vrD, vrJ, vrK is op15_31=0xe24c & vrD & vrJ & vrK { + vrD = vand.v(vrD, vrJ, vrK); +} + +define pcodeop vor.v; + +#lsx.txt vor.v mask=0x71268000 +#0x71268000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vor.v vrD, vrJ, vrK is op15_31=0xe24d & vrD & vrJ & vrK { + vrD = vor.v(vrD, vrJ, vrK); +} + +define pcodeop vxor.v; + +#lsx.txt vxor.v mask=0x71270000 +#0x71270000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vxor.v vrD, vrJ, vrK is op15_31=0xe24e & vrD & vrJ & vrK { + vrD = vxor.v(vrD, vrJ, vrK); +} + +define pcodeop vnor.v; + +#lsx.txt vnor.v mask=0x71278000 +#0x71278000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vnor.v vrD, vrJ, vrK is op15_31=0xe24f & vrD & vrJ & vrK { + vrD = vnor.v(vrD, vrJ, vrK); +} + +define pcodeop vandn.v; + +#lsx.txt vandn.v mask=0x71280000 +#0x71280000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vandn.v vrD, vrJ, vrK is op15_31=0xe250 & vrD & vrJ & vrK { + vrD = vandn.v(vrD, vrJ, vrK); +} + +define pcodeop vorn.v; + +#lsx.txt vorn.v mask=0x71288000 +#0x71288000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vorn.v vrD, vrJ, vrK is op15_31=0xe251 & vrD & vrJ & vrK { + vrD = vorn.v(vrD, vrJ, vrK); +} + +define pcodeop vfrstp.b; + +#lsx.txt vfrstp.b mask=0x712b0000 +#0x712b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfrstp.b vrD, vrJ, vrK is op15_31=0xe256 & vrD & vrJ & vrK { + vrD = vfrstp.b(vrD, vrJ, vrK); +} + +define pcodeop vfrstp.h; + +#lsx.txt vfrstp.h mask=0x712b8000 +#0x712b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfrstp.h vrD, vrJ, vrK is op15_31=0xe257 & vrD & vrJ & vrK { + vrD = vfrstp.h(vrD, vrJ, vrK); +} + +define pcodeop vadd.q; + +#lsx.txt vadd.q mask=0x712d0000 +#0x712d0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vadd.q vrD, vrJ, vrK is op15_31=0xe25a & vrD & vrJ & vrK { + vrD = vadd.q(vrD, vrJ, vrK); +} + +define pcodeop vsub.q; + +#lsx.txt vsub.q mask=0x712d8000 +#0x712d8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsub.q vrD, vrJ, vrK is op15_31=0xe25b & vrD & vrJ & vrK { + vrD = vsub.q(vrD, vrJ, vrK); +} + +define pcodeop vsigncov.b; + +#lsx.txt vsigncov.b mask=0x712e0000 +#0x712e0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsigncov.b vrD, vrJ, vrK is op15_31=0xe25c & vrD & vrJ & vrK { + vrD = vsigncov.b(vrD, vrJ, vrK); +} + +define pcodeop vsigncov.h; + +#lsx.txt vsigncov.h mask=0x712e8000 +#0x712e8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsigncov.h vrD, vrJ, vrK is op15_31=0xe25d & vrD & vrJ & vrK { + vrD = vsigncov.h(vrD, vrJ, vrK); +} + +define pcodeop vsigncov.w; + +#lsx.txt vsigncov.w mask=0x712f0000 +#0x712f0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsigncov.w vrD, vrJ, vrK is op15_31=0xe25e & vrD & vrJ & vrK { + vrD = vsigncov.w(vrD, vrJ, vrK); +} + +define pcodeop vsigncov.d; + +#lsx.txt vsigncov.d mask=0x712f8000 +#0x712f8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vsigncov.d vrD, vrJ, vrK is op15_31=0xe25f & vrD & vrJ & vrK { + vrD = vsigncov.d(vrD, vrJ, vrK); +} + +define pcodeop vfadd.s; + +#lsx.txt vfadd.s mask=0x71308000 +#0x71308000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfadd.s vrD, vrJ, vrK is op15_31=0xe261 & vrD & vrJ & vrK { + vrD = vfadd.s(vrD, vrJ, vrK); +} + +define pcodeop vfadd.d; + +#lsx.txt vfadd.d mask=0x71310000 +#0x71310000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfadd.d vrD, vrJ, vrK is op15_31=0xe262 & vrD & vrJ & vrK { + vrD = vfadd.d(vrD, vrJ, vrK); +} + +define pcodeop vfsub.s; + +#lsx.txt vfsub.s mask=0x71328000 +#0x71328000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfsub.s vrD, vrJ, vrK is op15_31=0xe265 & vrD & vrJ & vrK { + vrD = vfsub.s(vrD, vrJ, vrK); +} + +define pcodeop vfsub.d; + +#lsx.txt vfsub.d mask=0x71330000 +#0x71330000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfsub.d vrD, vrJ, vrK is op15_31=0xe266 & vrD & vrJ & vrK { + vrD = vfsub.d(vrD, vrJ, vrK); +} + +define pcodeop vfmul.s; + +#lsx.txt vfmul.s mask=0x71388000 +#0x71388000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmul.s vrD, vrJ, vrK is op15_31=0xe271 & vrD & vrJ & vrK { + vrD = vfmul.s(vrD, vrJ, vrK); +} + +define pcodeop vfmul.d; + +#lsx.txt vfmul.d mask=0x71390000 +#0x71390000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmul.d vrD, vrJ, vrK is op15_31=0xe272 & vrD & vrJ & vrK { + vrD = vfmul.d(vrD, vrJ, vrK); +} + +define pcodeop vfdiv.s; + +#lsx.txt vfdiv.s mask=0x713a8000 +#0x713a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfdiv.s vrD, vrJ, vrK is op15_31=0xe275 & vrD & vrJ & vrK { + vrD = vfdiv.s(vrD, vrJ, vrK); +} + +define pcodeop vfdiv.d; + +#lsx.txt vfdiv.d mask=0x713b0000 +#0x713b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfdiv.d vrD, vrJ, vrK is op15_31=0xe276 & vrD & vrJ & vrK { + vrD = vfdiv.d(vrD, vrJ, vrK); +} + +define pcodeop vfmax.s; + +#lsx.txt vfmax.s mask=0x713c8000 +#0x713c8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmax.s vrD, vrJ, vrK is op15_31=0xe279 & vrD & vrJ & vrK { + vrD = vfmax.s(vrD, vrJ, vrK); +} + +define pcodeop vfmax.d; + +#lsx.txt vfmax.d mask=0x713d0000 +#0x713d0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmax.d vrD, vrJ, vrK is op15_31=0xe27a & vrD & vrJ & vrK { + vrD = vfmax.d(vrD, vrJ, vrK); +} + +define pcodeop vfmin.s; + +#lsx.txt vfmin.s mask=0x713e8000 +#0x713e8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmin.s vrD, vrJ, vrK is op15_31=0xe27d & vrD & vrJ & vrK { + vrD = vfmin.s(vrD, vrJ, vrK); +} + +define pcodeop vfmin.d; + +#lsx.txt vfmin.d mask=0x713f0000 +#0x713f0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmin.d vrD, vrJ, vrK is op15_31=0xe27e & vrD & vrJ & vrK { + vrD = vfmin.d(vrD, vrJ, vrK); +} + +define pcodeop vfmaxa.s; + +#lsx.txt vfmaxa.s mask=0x71408000 +#0x71408000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmaxa.s vrD, vrJ, vrK is op15_31=0xe281 & vrD & vrJ & vrK { + vrD = vfmaxa.s(vrD, vrJ, vrK); +} + +define pcodeop vfmaxa.d; + +#lsx.txt vfmaxa.d mask=0x71410000 +#0x71410000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmaxa.d vrD, vrJ, vrK is op15_31=0xe282 & vrD & vrJ & vrK { + vrD = vfmaxa.d(vrD, vrJ, vrK); +} + +define pcodeop vfmina.s; + +#lsx.txt vfmina.s mask=0x71428000 +#0x71428000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmina.s vrD, vrJ, vrK is op15_31=0xe285 & vrD & vrJ & vrK { + vrD = vfmina.s(vrD, vrJ, vrK); +} + +define pcodeop vfmina.d; + +#lsx.txt vfmina.d mask=0x71430000 +#0x71430000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfmina.d vrD, vrJ, vrK is op15_31=0xe286 & vrD & vrJ & vrK { + vrD = vfmina.d(vrD, vrJ, vrK); +} + +define pcodeop vfcvt.h.s; + +#lsx.txt vfcvt.h.s mask=0x71460000 +#0x71460000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcvt.h.s vrD, vrJ, vrK is op15_31=0xe28c & vrD & vrJ & vrK { + vrD = vfcvt.h.s(vrD, vrJ, vrK); +} + +define pcodeop vfcvt.s.d; + +#lsx.txt vfcvt.s.d mask=0x71468000 +#0x71468000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vfcvt.s.d vrD, vrJ, vrK is op15_31=0xe28d & vrD & vrJ & vrK { + vrD = vfcvt.s.d(vrD, vrJ, vrK); +} + +define pcodeop vffint.s.l; + +#lsx.txt vffint.s.l mask=0x71480000 +#0x71480000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vffint.s.l vrD, vrJ, vrK is op15_31=0xe290 & vrD & vrJ & vrK { + vrD = vffint.s.l(vrD, vrJ, vrK); +} + +define pcodeop vftint.w.d; + +#lsx.txt vftint.w.d mask=0x71498000 +#0x71498000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vftint.w.d vrD, vrJ, vrK is op15_31=0xe293 & vrD & vrJ & vrK { + vrD = vftint.w.d(vrD, vrJ, vrK); +} + +define pcodeop vftintrm.w.d; + +#lsx.txt vftintrm.w.d mask=0x714a0000 +#0x714a0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vftintrm.w.d vrD, vrJ, vrK is op15_31=0xe294 & vrD & vrJ & vrK { + vrD = vftintrm.w.d(vrD, vrJ, vrK); +} + +define pcodeop vftintrp.w.d; + +#lsx.txt vftintrp.w.d mask=0x714a8000 +#0x714a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vftintrp.w.d vrD, vrJ, vrK is op15_31=0xe295 & vrD & vrJ & vrK { + vrD = vftintrp.w.d(vrD, vrJ, vrK); +} + +define pcodeop vftintrz.w.d; + +#lsx.txt vftintrz.w.d mask=0x714b0000 +#0x714b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vftintrz.w.d vrD, vrJ, vrK is op15_31=0xe296 & vrD & vrJ & vrK { + vrD = vftintrz.w.d(vrD, vrJ, vrK); +} + +define pcodeop vftintrne.w.d; + +#lsx.txt vftintrne.w.d mask=0x714b8000 +#0x714b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vftintrne.w.d vrD, vrJ, vrK is op15_31=0xe297 & vrD & vrJ & vrK { + vrD = vftintrne.w.d(vrD, vrJ, vrK); +} + +define pcodeop vshuf.h; + +#lsx.txt vshuf.h mask=0x717a8000 +#0x717a8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vshuf.h vrD, vrJ, vrK is op15_31=0xe2f5 & vrD & vrJ & vrK { + vrD = vshuf.h(vrD, vrJ, vrK); +} + +define pcodeop vshuf.w; + +#lsx.txt vshuf.w mask=0x717b0000 +#0x717b0000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vshuf.w vrD, vrJ, vrK is op15_31=0xe2f6 & vrD & vrJ & vrK { + vrD = vshuf.w(vrD, vrJ, vrK); +} + +define pcodeop vshuf.d; + +#lsx.txt vshuf.d mask=0x717b8000 +#0x717b8000 0xffff8000 v0:5,v5:5,v10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'vreg10_5_s0'] +:vshuf.d vrD, vrJ, vrK is op15_31=0xe2f7 & vrD & vrJ & vrK { + vrD = vshuf.d(vrD, vrJ, vrK); +} + +define pcodeop vseqi.b; + +#lsx.txt vseqi.b mask=0x72800000 +#0x72800000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vseqi.b vrD, vrJ, simm10_5 is op15_31=0xe500 & vrD & vrJ & simm10_5 { + vrD = vseqi.b(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vseqi.h; + +#lsx.txt vseqi.h mask=0x72808000 +#0x72808000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vseqi.h vrD, vrJ, simm10_5 is op15_31=0xe501 & vrD & vrJ & simm10_5 { + vrD = vseqi.h(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vseqi.w; + +#lsx.txt vseqi.w mask=0x72810000 +#0x72810000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vseqi.w vrD, vrJ, simm10_5 is op15_31=0xe502 & vrD & vrJ & simm10_5 { + vrD = vseqi.w(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vseqi.d; + +#lsx.txt vseqi.d mask=0x72818000 +#0x72818000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vseqi.d vrD, vrJ, simm10_5 is op15_31=0xe503 & vrD & vrJ & simm10_5 { + vrD = vseqi.d(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslei.b; + +#lsx.txt vslei.b mask=0x72820000 +#0x72820000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vslei.b vrD, vrJ, simm10_5 is op15_31=0xe504 & vrD & vrJ & simm10_5 { + vrD = vslei.b(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslei.h; + +#lsx.txt vslei.h mask=0x72828000 +#0x72828000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vslei.h vrD, vrJ, simm10_5 is op15_31=0xe505 & vrD & vrJ & simm10_5 { + vrD = vslei.h(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslei.w; + +#lsx.txt vslei.w mask=0x72830000 +#0x72830000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vslei.w vrD, vrJ, simm10_5 is op15_31=0xe506 & vrD & vrJ & simm10_5 { + vrD = vslei.w(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslei.d; + +#lsx.txt vslei.d mask=0x72838000 +#0x72838000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vslei.d vrD, vrJ, simm10_5 is op15_31=0xe507 & vrD & vrJ & simm10_5 { + vrD = vslei.d(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslei.bu; + +#lsx.txt vslei.bu mask=0x72840000 +#0x72840000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslei.bu vrD, vrJ, imm10_5 is op15_31=0xe508 & vrD & vrJ & imm10_5 { + vrD = vslei.bu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vslei.hu; + +#lsx.txt vslei.hu mask=0x72848000 +#0x72848000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslei.hu vrD, vrJ, imm10_5 is op15_31=0xe509 & vrD & vrJ & imm10_5 { + vrD = vslei.hu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vslei.wu; + +#lsx.txt vslei.wu mask=0x72850000 +#0x72850000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslei.wu vrD, vrJ, imm10_5 is op15_31=0xe50a & vrD & vrJ & imm10_5 { + vrD = vslei.wu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vslei.du; + +#lsx.txt vslei.du mask=0x72858000 +#0x72858000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslei.du vrD, vrJ, imm10_5 is op15_31=0xe50b & vrD & vrJ & imm10_5 { + vrD = vslei.du(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vslti.b; + +#lsx.txt vslti.b mask=0x72860000 +#0x72860000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vslti.b vrD, vrJ, simm10_5 is op15_31=0xe50c & vrD & vrJ & simm10_5 { + vrD = vslti.b(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslti.h; + +#lsx.txt vslti.h mask=0x72868000 +#0x72868000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vslti.h vrD, vrJ, simm10_5 is op15_31=0xe50d & vrD & vrJ & simm10_5 { + vrD = vslti.h(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslti.w; + +#lsx.txt vslti.w mask=0x72870000 +#0x72870000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vslti.w vrD, vrJ, simm10_5 is op15_31=0xe50e & vrD & vrJ & simm10_5 { + vrD = vslti.w(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslti.d; + +#lsx.txt vslti.d mask=0x72878000 +#0x72878000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vslti.d vrD, vrJ, simm10_5 is op15_31=0xe50f & vrD & vrJ & simm10_5 { + vrD = vslti.d(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vslti.bu; + +#lsx.txt vslti.bu mask=0x72880000 +#0x72880000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslti.bu vrD, vrJ, imm10_5 is op15_31=0xe510 & vrD & vrJ & imm10_5 { + vrD = vslti.bu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vslti.hu; + +#lsx.txt vslti.hu mask=0x72888000 +#0x72888000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslti.hu vrD, vrJ, imm10_5 is op15_31=0xe511 & vrD & vrJ & imm10_5 { + vrD = vslti.hu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vslti.wu; + +#lsx.txt vslti.wu mask=0x72890000 +#0x72890000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslti.wu vrD, vrJ, imm10_5 is op15_31=0xe512 & vrD & vrJ & imm10_5 { + vrD = vslti.wu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vslti.du; + +#lsx.txt vslti.du mask=0x72898000 +#0x72898000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslti.du vrD, vrJ, imm10_5 is op15_31=0xe513 & vrD & vrJ & imm10_5 { + vrD = vslti.du(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vaddi.bu; + +#lsx.txt vaddi.bu mask=0x728a0000 +#0x728a0000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vaddi.bu vrD, vrJ, imm10_5 is op15_31=0xe514 & vrD & vrJ & imm10_5 { + vrD = vaddi.bu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vaddi.hu; + +#lsx.txt vaddi.hu mask=0x728a8000 +#0x728a8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vaddi.hu vrD, vrJ, imm10_5 is op15_31=0xe515 & vrD & vrJ & imm10_5 { + vrD = vaddi.hu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vaddi.wu; + +#lsx.txt vaddi.wu mask=0x728b0000 +#0x728b0000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vaddi.wu vrD, vrJ, imm10_5 is op15_31=0xe516 & vrD & vrJ & imm10_5 { + vrD = vaddi.wu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vaddi.du; + +#lsx.txt vaddi.du mask=0x728b8000 +#0x728b8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vaddi.du vrD, vrJ, imm10_5 is op15_31=0xe517 & vrD & vrJ & imm10_5 { + vrD = vaddi.du(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsubi.bu; + +#lsx.txt vsubi.bu mask=0x728c0000 +#0x728c0000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsubi.bu vrD, vrJ, imm10_5 is op15_31=0xe518 & vrD & vrJ & imm10_5 { + vrD = vsubi.bu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsubi.hu; + +#lsx.txt vsubi.hu mask=0x728c8000 +#0x728c8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsubi.hu vrD, vrJ, imm10_5 is op15_31=0xe519 & vrD & vrJ & imm10_5 { + vrD = vsubi.hu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsubi.wu; + +#lsx.txt vsubi.wu mask=0x728d0000 +#0x728d0000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsubi.wu vrD, vrJ, imm10_5 is op15_31=0xe51a & vrD & vrJ & imm10_5 { + vrD = vsubi.wu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsubi.du; + +#lsx.txt vsubi.du mask=0x728d8000 +#0x728d8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsubi.du vrD, vrJ, imm10_5 is op15_31=0xe51b & vrD & vrJ & imm10_5 { + vrD = vsubi.du(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vbsll.v; + +#lsx.txt vbsll.v mask=0x728e0000 +#0x728e0000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vbsll.v vrD, vrJ, imm10_5 is op15_31=0xe51c & vrD & vrJ & imm10_5 { + vrD = vbsll.v(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vbsrl.v; + +#lsx.txt vbsrl.v mask=0x728e8000 +#0x728e8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vbsrl.v vrD, vrJ, imm10_5 is op15_31=0xe51d & vrD & vrJ & imm10_5 { + vrD = vbsrl.v(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vmaxi.b; + +#lsx.txt vmaxi.b mask=0x72900000 +#0x72900000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vmaxi.b vrD, vrJ, simm10_5 is op15_31=0xe520 & vrD & vrJ & simm10_5 { + vrD = vmaxi.b(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vmaxi.h; + +#lsx.txt vmaxi.h mask=0x72908000 +#0x72908000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vmaxi.h vrD, vrJ, simm10_5 is op15_31=0xe521 & vrD & vrJ & simm10_5 { + vrD = vmaxi.h(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vmaxi.w; + +#lsx.txt vmaxi.w mask=0x72910000 +#0x72910000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vmaxi.w vrD, vrJ, simm10_5 is op15_31=0xe522 & vrD & vrJ & simm10_5 { + vrD = vmaxi.w(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vmaxi.d; + +#lsx.txt vmaxi.d mask=0x72918000 +#0x72918000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vmaxi.d vrD, vrJ, simm10_5 is op15_31=0xe523 & vrD & vrJ & simm10_5 { + vrD = vmaxi.d(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vmini.b; + +#lsx.txt vmini.b mask=0x72920000 +#0x72920000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vmini.b vrD, vrJ, simm10_5 is op15_31=0xe524 & vrD & vrJ & simm10_5 { + vrD = vmini.b(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vmini.h; + +#lsx.txt vmini.h mask=0x72928000 +#0x72928000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vmini.h vrD, vrJ, simm10_5 is op15_31=0xe525 & vrD & vrJ & simm10_5 { + vrD = vmini.h(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vmini.w; + +#lsx.txt vmini.w mask=0x72930000 +#0x72930000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vmini.w vrD, vrJ, simm10_5 is op15_31=0xe526 & vrD & vrJ & simm10_5 { + vrD = vmini.w(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vmini.d; + +#lsx.txt vmini.d mask=0x72938000 +#0x72938000 0xffff8000 v0:5,v5:5, s10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'simm10_5_s0'] +:vmini.d vrD, vrJ, simm10_5 is op15_31=0xe527 & vrD & vrJ & simm10_5 { + vrD = vmini.d(vrD, vrJ, simm10_5:$(REGSIZE)); +} + +define pcodeop vmaxi.bu; + +#lsx.txt vmaxi.bu mask=0x72940000 +#0x72940000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vmaxi.bu vrD, vrJ, imm10_5 is op15_31=0xe528 & vrD & vrJ & imm10_5 { + vrD = vmaxi.bu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vmaxi.hu; + +#lsx.txt vmaxi.hu mask=0x72948000 +#0x72948000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vmaxi.hu vrD, vrJ, imm10_5 is op15_31=0xe529 & vrD & vrJ & imm10_5 { + vrD = vmaxi.hu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vmaxi.wu; + +#lsx.txt vmaxi.wu mask=0x72950000 +#0x72950000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vmaxi.wu vrD, vrJ, imm10_5 is op15_31=0xe52a & vrD & vrJ & imm10_5 { + vrD = vmaxi.wu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vmaxi.du; + +#lsx.txt vmaxi.du mask=0x72958000 +#0x72958000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vmaxi.du vrD, vrJ, imm10_5 is op15_31=0xe52b & vrD & vrJ & imm10_5 { + vrD = vmaxi.du(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vmini.bu; + +#lsx.txt vmini.bu mask=0x72960000 +#0x72960000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vmini.bu vrD, vrJ, imm10_5 is op15_31=0xe52c & vrD & vrJ & imm10_5 { + vrD = vmini.bu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vmini.hu; + +#lsx.txt vmini.hu mask=0x72968000 +#0x72968000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vmini.hu vrD, vrJ, imm10_5 is op15_31=0xe52d & vrD & vrJ & imm10_5 { + vrD = vmini.hu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vmini.wu; + +#lsx.txt vmini.wu mask=0x72970000 +#0x72970000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vmini.wu vrD, vrJ, imm10_5 is op15_31=0xe52e & vrD & vrJ & imm10_5 { + vrD = vmini.wu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vmini.du; + +#lsx.txt vmini.du mask=0x72978000 +#0x72978000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vmini.du vrD, vrJ, imm10_5 is op15_31=0xe52f & vrD & vrJ & imm10_5 { + vrD = vmini.du(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vfrstpi.b; + +#lsx.txt vfrstpi.b mask=0x729a0000 +#0x729a0000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vfrstpi.b vrD, vrJ, imm10_5 is op15_31=0xe534 & vrD & vrJ & imm10_5 { + vrD = vfrstpi.b(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vfrstpi.h; + +#lsx.txt vfrstpi.h mask=0x729a8000 +#0x729a8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vfrstpi.h vrD, vrJ, imm10_5 is op15_31=0xe535 & vrD & vrJ & imm10_5 { + vrD = vfrstpi.h(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vclo.b; + +#lsx.txt vclo.b mask=0x729c0000 +#0x729c0000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vclo.b vrD, vrJ is op10_31=0x1ca700 & vrD & vrJ { + vrD = vclo.b(vrD, vrJ); +} + +define pcodeop vclo.h; + +#lsx.txt vclo.h mask=0x729c0400 +#0x729c0400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vclo.h vrD, vrJ is op10_31=0x1ca701 & vrD & vrJ { + vrD = vclo.h(vrD, vrJ); +} + +define pcodeop vclo.w; + +#lsx.txt vclo.w mask=0x729c0800 +#0x729c0800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vclo.w vrD, vrJ is op10_31=0x1ca702 & vrD & vrJ { + vrD = vclo.w(vrD, vrJ); +} + +define pcodeop vclo.d; + +#lsx.txt vclo.d mask=0x729c0c00 +#0x729c0c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vclo.d vrD, vrJ is op10_31=0x1ca703 & vrD & vrJ { + vrD = vclo.d(vrD, vrJ); +} + +define pcodeop vclz.b; + +#lsx.txt vclz.b mask=0x729c1000 +#0x729c1000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vclz.b vrD, vrJ is op10_31=0x1ca704 & vrD & vrJ { + vrD = vclz.b(vrD, vrJ); +} + +define pcodeop vclz.h; + +#lsx.txt vclz.h mask=0x729c1400 +#0x729c1400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vclz.h vrD, vrJ is op10_31=0x1ca705 & vrD & vrJ { + vrD = vclz.h(vrD, vrJ); +} + +define pcodeop vclz.w; + +#lsx.txt vclz.w mask=0x729c1800 +#0x729c1800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vclz.w vrD, vrJ is op10_31=0x1ca706 & vrD & vrJ { + vrD = vclz.w(vrD, vrJ); +} + +define pcodeop vclz.d; + +#lsx.txt vclz.d mask=0x729c1c00 +#0x729c1c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vclz.d vrD, vrJ is op10_31=0x1ca707 & vrD & vrJ { + vrD = vclz.d(vrD, vrJ); +} + +define pcodeop vpcnt.b; + +#lsx.txt vpcnt.b mask=0x729c2000 +#0x729c2000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vpcnt.b vrD, vrJ is op10_31=0x1ca708 & vrD & vrJ { + vrD = vpcnt.b(vrD, vrJ); +} + +define pcodeop vpcnt.h; + +#lsx.txt vpcnt.h mask=0x729c2400 +#0x729c2400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vpcnt.h vrD, vrJ is op10_31=0x1ca709 & vrD & vrJ { + vrD = vpcnt.h(vrD, vrJ); +} + +define pcodeop vpcnt.w; + +#lsx.txt vpcnt.w mask=0x729c2800 +#0x729c2800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vpcnt.w vrD, vrJ is op10_31=0x1ca70a & vrD & vrJ { + vrD = vpcnt.w(vrD, vrJ); +} + +define pcodeop vpcnt.d; + +#lsx.txt vpcnt.d mask=0x729c2c00 +#0x729c2c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vpcnt.d vrD, vrJ is op10_31=0x1ca70b & vrD & vrJ { + vrD = vpcnt.d(vrD, vrJ); +} + +define pcodeop vneg.b; + +#lsx.txt vneg.b mask=0x729c3000 +#0x729c3000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vneg.b vrD, vrJ is op10_31=0x1ca70c & vrD & vrJ { + vrD = vneg.b(vrD, vrJ); +} + +define pcodeop vneg.h; + +#lsx.txt vneg.h mask=0x729c3400 +#0x729c3400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vneg.h vrD, vrJ is op10_31=0x1ca70d & vrD & vrJ { + vrD = vneg.h(vrD, vrJ); +} + +define pcodeop vneg.w; + +#lsx.txt vneg.w mask=0x729c3800 +#0x729c3800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vneg.w vrD, vrJ is op10_31=0x1ca70e & vrD & vrJ { + vrD = vneg.w(vrD, vrJ); +} + +define pcodeop vneg.d; + +#lsx.txt vneg.d mask=0x729c3c00 +#0x729c3c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vneg.d vrD, vrJ is op10_31=0x1ca70f & vrD & vrJ { + vrD = vneg.d(vrD, vrJ); +} + +define pcodeop vmskltz.b; + +#lsx.txt vmskltz.b mask=0x729c4000 +#0x729c4000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vmskltz.b vrD, vrJ is op10_31=0x1ca710 & vrD & vrJ { + vrD = vmskltz.b(vrD, vrJ); +} + +define pcodeop vmskltz.h; + +#lsx.txt vmskltz.h mask=0x729c4400 +#0x729c4400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vmskltz.h vrD, vrJ is op10_31=0x1ca711 & vrD & vrJ { + vrD = vmskltz.h(vrD, vrJ); +} + +define pcodeop vmskltz.w; + +#lsx.txt vmskltz.w mask=0x729c4800 +#0x729c4800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vmskltz.w vrD, vrJ is op10_31=0x1ca712 & vrD & vrJ { + vrD = vmskltz.w(vrD, vrJ); +} + +define pcodeop vmskltz.d; + +#lsx.txt vmskltz.d mask=0x729c4c00 +#0x729c4c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vmskltz.d vrD, vrJ is op10_31=0x1ca713 & vrD & vrJ { + vrD = vmskltz.d(vrD, vrJ); +} + +define pcodeop vmskgez.b; + +#lsx.txt vmskgez.b mask=0x729c5000 +#0x729c5000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vmskgez.b vrD, vrJ is op10_31=0x1ca714 & vrD & vrJ { + vrD = vmskgez.b(vrD, vrJ); +} + +define pcodeop vmsknz.b; + +#lsx.txt vmsknz.b mask=0x729c6000 +#0x729c6000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vmsknz.b vrD, vrJ is op10_31=0x1ca718 & vrD & vrJ { + vrD = vmsknz.b(vrD, vrJ); +} + +define pcodeop vseteqz.v; + +#lsx.txt vseteqz.v mask=0x729c9800 +#0x729c9800 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vseteqz.v fccD, vrJ is op10_31=0x1ca726 & fccD & vrJ { + fccD = vseteqz.v(fccD, vrJ); +} + +define pcodeop vsetnez.v; + +#lsx.txt vsetnez.v mask=0x729c9c00 +#0x729c9c00 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetnez.v fccD, vrJ is op10_31=0x1ca727 & fccD & vrJ { + fccD = vsetnez.v(fccD, vrJ); +} + +define pcodeop vsetanyeqz.b; + +#lsx.txt vsetanyeqz.b mask=0x729ca000 +#0x729ca000 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetanyeqz.b fccD, vrJ is op10_31=0x1ca728 & fccD & vrJ { + fccD = vsetanyeqz.b(fccD, vrJ); +} + +define pcodeop vsetanyeqz.h; + +#lsx.txt vsetanyeqz.h mask=0x729ca400 +#0x729ca400 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetanyeqz.h fccD, vrJ is op10_31=0x1ca729 & fccD & vrJ { + fccD = vsetanyeqz.h(fccD, vrJ); +} + +define pcodeop vsetanyeqz.w; + +#lsx.txt vsetanyeqz.w mask=0x729ca800 +#0x729ca800 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetanyeqz.w fccD, vrJ is op10_31=0x1ca72a & fccD & vrJ { + fccD = vsetanyeqz.w(fccD, vrJ); +} + +define pcodeop vsetanyeqz.d; + +#lsx.txt vsetanyeqz.d mask=0x729cac00 +#0x729cac00 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetanyeqz.d fccD, vrJ is op10_31=0x1ca72b & fccD & vrJ { + fccD = vsetanyeqz.d(fccD, vrJ); +} + +define pcodeop vsetallnez.b; + +#lsx.txt vsetallnez.b mask=0x729cb000 +#0x729cb000 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetallnez.b fccD, vrJ is op10_31=0x1ca72c & fccD & vrJ { + fccD = vsetallnez.b(fccD, vrJ); +} + +define pcodeop vsetallnez.h; + +#lsx.txt vsetallnez.h mask=0x729cb400 +#0x729cb400 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetallnez.h fccD, vrJ is op10_31=0x1ca72d & fccD & vrJ { + fccD = vsetallnez.h(fccD, vrJ); +} + +define pcodeop vsetallnez.w; + +#lsx.txt vsetallnez.w mask=0x729cb800 +#0x729cb800 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetallnez.w fccD, vrJ is op10_31=0x1ca72e & fccD & vrJ { + fccD = vsetallnez.w(fccD, vrJ); +} + +define pcodeop vsetallnez.d; + +#lsx.txt vsetallnez.d mask=0x729cbc00 +#0x729cbc00 0xfffffc18 c0:3,v5:5 ['fcc0_3_s0', 'vreg5_5_s0'] +:vsetallnez.d fccD, vrJ is op10_31=0x1ca72f & fccD & vrJ { + fccD = vsetallnez.d(fccD, vrJ); +} + +define pcodeop vflogb.s; + +#lsx.txt vflogb.s mask=0x729cc400 +#0x729cc400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vflogb.s vrD, vrJ is op10_31=0x1ca731 & vrD & vrJ { + vrD = vflogb.s(vrD, vrJ); +} + +define pcodeop vflogb.d; + +#lsx.txt vflogb.d mask=0x729cc800 +#0x729cc800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vflogb.d vrD, vrJ is op10_31=0x1ca732 & vrD & vrJ { + vrD = vflogb.d(vrD, vrJ); +} + +define pcodeop vfclass.s; + +#lsx.txt vfclass.s mask=0x729cd400 +#0x729cd400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfclass.s vrD, vrJ is op10_31=0x1ca735 & vrD & vrJ { + vrD = vfclass.s(vrD, vrJ); +} + +define pcodeop vfclass.d; + +#lsx.txt vfclass.d mask=0x729cd800 +#0x729cd800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfclass.d vrD, vrJ is op10_31=0x1ca736 & vrD & vrJ { + vrD = vfclass.d(vrD, vrJ); +} + +define pcodeop vfsqrt.s; + +#lsx.txt vfsqrt.s mask=0x729ce400 +#0x729ce400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfsqrt.s vrD, vrJ is op10_31=0x1ca739 & vrD & vrJ { + vrD = vfsqrt.s(vrD, vrJ); +} + +define pcodeop vfsqrt.d; + +#lsx.txt vfsqrt.d mask=0x729ce800 +#0x729ce800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfsqrt.d vrD, vrJ is op10_31=0x1ca73a & vrD & vrJ { + vrD = vfsqrt.d(vrD, vrJ); +} + +define pcodeop vfrecip.s; + +#lsx.txt vfrecip.s mask=0x729cf400 +#0x729cf400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrecip.s vrD, vrJ is op10_31=0x1ca73d & vrD & vrJ { + vrD = vfrecip.s(vrD, vrJ); +} + +define pcodeop vfrecip.d; + +#lsx.txt vfrecip.d mask=0x729cf800 +#0x729cf800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrecip.d vrD, vrJ is op10_31=0x1ca73e & vrD & vrJ { + vrD = vfrecip.d(vrD, vrJ); +} + +define pcodeop vfrsqrt.s; + +#lsx.txt vfrsqrt.s mask=0x729d0400 +#0x729d0400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrsqrt.s vrD, vrJ is op10_31=0x1ca741 & vrD & vrJ { + vrD = vfrsqrt.s(vrD, vrJ); +} + +define pcodeop vfrsqrt.d; + +#lsx.txt vfrsqrt.d mask=0x729d0800 +#0x729d0800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrsqrt.d vrD, vrJ is op10_31=0x1ca742 & vrD & vrJ { + vrD = vfrsqrt.d(vrD, vrJ); +} + +define pcodeop vfrint.s; + +#lsx.txt vfrint.s mask=0x729d3400 +#0x729d3400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrint.s vrD, vrJ is op10_31=0x1ca74d & vrD & vrJ { + vrD = vfrint.s(vrD, vrJ); +} + +define pcodeop vfrint.d; + +#lsx.txt vfrint.d mask=0x729d3800 +#0x729d3800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrint.d vrD, vrJ is op10_31=0x1ca74e & vrD & vrJ { + vrD = vfrint.d(vrD, vrJ); +} + +define pcodeop vfrintrm.s; + +#lsx.txt vfrintrm.s mask=0x729d4400 +#0x729d4400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrintrm.s vrD, vrJ is op10_31=0x1ca751 & vrD & vrJ { + vrD = vfrintrm.s(vrD, vrJ); +} + +define pcodeop vfrintrm.d; + +#lsx.txt vfrintrm.d mask=0x729d4800 +#0x729d4800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrintrm.d vrD, vrJ is op10_31=0x1ca752 & vrD & vrJ { + vrD = vfrintrm.d(vrD, vrJ); +} + +define pcodeop vfrintrp.s; + +#lsx.txt vfrintrp.s mask=0x729d5400 +#0x729d5400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrintrp.s vrD, vrJ is op10_31=0x1ca755 & vrD & vrJ { + vrD = vfrintrp.s(vrD, vrJ); +} + +define pcodeop vfrintrp.d; + +#lsx.txt vfrintrp.d mask=0x729d5800 +#0x729d5800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrintrp.d vrD, vrJ is op10_31=0x1ca756 & vrD & vrJ { + vrD = vfrintrp.d(vrD, vrJ); +} + +define pcodeop vfrintrz.s; + +#lsx.txt vfrintrz.s mask=0x729d6400 +#0x729d6400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrintrz.s vrD, vrJ is op10_31=0x1ca759 & vrD & vrJ { + vrD = vfrintrz.s(vrD, vrJ); +} + +define pcodeop vfrintrz.d; + +#lsx.txt vfrintrz.d mask=0x729d6800 +#0x729d6800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrintrz.d vrD, vrJ is op10_31=0x1ca75a & vrD & vrJ { + vrD = vfrintrz.d(vrD, vrJ); +} + +define pcodeop vfrintrne.s; + +#lsx.txt vfrintrne.s mask=0x729d7400 +#0x729d7400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrintrne.s vrD, vrJ is op10_31=0x1ca75d & vrD & vrJ { + vrD = vfrintrne.s(vrD, vrJ); +} + +define pcodeop vfrintrne.d; + +#lsx.txt vfrintrne.d mask=0x729d7800 +#0x729d7800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfrintrne.d vrD, vrJ is op10_31=0x1ca75e & vrD & vrJ { + vrD = vfrintrne.d(vrD, vrJ); +} + +define pcodeop vfcvtl.s.h; + +#lsx.txt vfcvtl.s.h mask=0x729de800 +#0x729de800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfcvtl.s.h vrD, vrJ is op10_31=0x1ca77a & vrD & vrJ { + vrD = vfcvtl.s.h(vrD, vrJ); +} + +define pcodeop vfcvth.s.h; + +#lsx.txt vfcvth.s.h mask=0x729dec00 +#0x729dec00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfcvth.s.h vrD, vrJ is op10_31=0x1ca77b & vrD & vrJ { + vrD = vfcvth.s.h(vrD, vrJ); +} + +define pcodeop vfcvtl.d.s; + +#lsx.txt vfcvtl.d.s mask=0x729df000 +#0x729df000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfcvtl.d.s vrD, vrJ is op10_31=0x1ca77c & vrD & vrJ { + vrD = vfcvtl.d.s(vrD, vrJ); +} + +define pcodeop vfcvth.d.s; + +#lsx.txt vfcvth.d.s mask=0x729df400 +#0x729df400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vfcvth.d.s vrD, vrJ is op10_31=0x1ca77d & vrD & vrJ { + vrD = vfcvth.d.s(vrD, vrJ); +} + +define pcodeop vffint.s.w; + +#lsx.txt vffint.s.w mask=0x729e0000 +#0x729e0000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vffint.s.w vrD, vrJ is op10_31=0x1ca780 & vrD & vrJ { + vrD = vffint.s.w(vrD, vrJ); +} + +define pcodeop vffint.s.wu; + +#lsx.txt vffint.s.wu mask=0x729e0400 +#0x729e0400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vffint.s.wu vrD, vrJ is op10_31=0x1ca781 & vrD & vrJ { + vrD = vffint.s.wu(vrD, vrJ); +} + +define pcodeop vffint.d.l; + +#lsx.txt vffint.d.l mask=0x729e0800 +#0x729e0800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vffint.d.l vrD, vrJ is op10_31=0x1ca782 & vrD & vrJ { + vrD = vffint.d.l(vrD, vrJ); +} + +define pcodeop vffint.d.lu; + +#lsx.txt vffint.d.lu mask=0x729e0c00 +#0x729e0c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vffint.d.lu vrD, vrJ is op10_31=0x1ca783 & vrD & vrJ { + vrD = vffint.d.lu(vrD, vrJ); +} + +define pcodeop vffintl.d.w; + +#lsx.txt vffintl.d.w mask=0x729e1000 +#0x729e1000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vffintl.d.w vrD, vrJ is op10_31=0x1ca784 & vrD & vrJ { + vrD = vffintl.d.w(vrD, vrJ); +} + +define pcodeop vffinth.d.w; + +#lsx.txt vffinth.d.w mask=0x729e1400 +#0x729e1400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vffinth.d.w vrD, vrJ is op10_31=0x1ca785 & vrD & vrJ { + vrD = vffinth.d.w(vrD, vrJ); +} + +define pcodeop vftint.w.s; + +#lsx.txt vftint.w.s mask=0x729e3000 +#0x729e3000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftint.w.s vrD, vrJ is op10_31=0x1ca78c & vrD & vrJ { + vrD = vftint.w.s(vrD, vrJ); +} + +define pcodeop vftint.l.d; + +#lsx.txt vftint.l.d mask=0x729e3400 +#0x729e3400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftint.l.d vrD, vrJ is op10_31=0x1ca78d & vrD & vrJ { + vrD = vftint.l.d(vrD, vrJ); +} + +define pcodeop vftintrm.w.s; + +#lsx.txt vftintrm.w.s mask=0x729e3800 +#0x729e3800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrm.w.s vrD, vrJ is op10_31=0x1ca78e & vrD & vrJ { + vrD = vftintrm.w.s(vrD, vrJ); +} + +define pcodeop vftintrm.l.d; + +#lsx.txt vftintrm.l.d mask=0x729e3c00 +#0x729e3c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrm.l.d vrD, vrJ is op10_31=0x1ca78f & vrD & vrJ { + vrD = vftintrm.l.d(vrD, vrJ); +} + +define pcodeop vftintrp.w.s; + +#lsx.txt vftintrp.w.s mask=0x729e4000 +#0x729e4000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrp.w.s vrD, vrJ is op10_31=0x1ca790 & vrD & vrJ { + vrD = vftintrp.w.s(vrD, vrJ); +} + +define pcodeop vftintrp.l.d; + +#lsx.txt vftintrp.l.d mask=0x729e4400 +#0x729e4400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrp.l.d vrD, vrJ is op10_31=0x1ca791 & vrD & vrJ { + vrD = vftintrp.l.d(vrD, vrJ); +} + +define pcodeop vftintrz.w.s; + +#lsx.txt vftintrz.w.s mask=0x729e4800 +#0x729e4800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrz.w.s vrD, vrJ is op10_31=0x1ca792 & vrD & vrJ { + vrD = vftintrz.w.s(vrD, vrJ); +} + +define pcodeop vftintrz.l.d; + +#lsx.txt vftintrz.l.d mask=0x729e4c00 +#0x729e4c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrz.l.d vrD, vrJ is op10_31=0x1ca793 & vrD & vrJ { + vrD = vftintrz.l.d(vrD, vrJ); +} + +define pcodeop vftintrne.w.s; + +#lsx.txt vftintrne.w.s mask=0x729e5000 +#0x729e5000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrne.w.s vrD, vrJ is op10_31=0x1ca794 & vrD & vrJ { + vrD = vftintrne.w.s(vrD, vrJ); +} + +define pcodeop vftintrne.l.d; + +#lsx.txt vftintrne.l.d mask=0x729e5400 +#0x729e5400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrne.l.d vrD, vrJ is op10_31=0x1ca795 & vrD & vrJ { + vrD = vftintrne.l.d(vrD, vrJ); +} + +define pcodeop vftint.wu.s; + +#lsx.txt vftint.wu.s mask=0x729e5800 +#0x729e5800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftint.wu.s vrD, vrJ is op10_31=0x1ca796 & vrD & vrJ { + vrD = vftint.wu.s(vrD, vrJ); +} + +define pcodeop vftint.lu.d; + +#lsx.txt vftint.lu.d mask=0x729e5c00 +#0x729e5c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftint.lu.d vrD, vrJ is op10_31=0x1ca797 & vrD & vrJ { + vrD = vftint.lu.d(vrD, vrJ); +} + +define pcodeop vftintrz.wu.s; + +#lsx.txt vftintrz.wu.s mask=0x729e7000 +#0x729e7000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrz.wu.s vrD, vrJ is op10_31=0x1ca79c & vrD & vrJ { + vrD = vftintrz.wu.s(vrD, vrJ); +} + +define pcodeop vftintrz.lu.d; + +#lsx.txt vftintrz.lu.d mask=0x729e7400 +#0x729e7400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrz.lu.d vrD, vrJ is op10_31=0x1ca79d & vrD & vrJ { + vrD = vftintrz.lu.d(vrD, vrJ); +} + +define pcodeop vftintl.l.s; + +#lsx.txt vftintl.l.s mask=0x729e8000 +#0x729e8000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintl.l.s vrD, vrJ is op10_31=0x1ca7a0 & vrD & vrJ { + vrD = vftintl.l.s(vrD, vrJ); +} + +define pcodeop vftinth.l.s; + +#lsx.txt vftinth.l.s mask=0x729e8400 +#0x729e8400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftinth.l.s vrD, vrJ is op10_31=0x1ca7a1 & vrD & vrJ { + vrD = vftinth.l.s(vrD, vrJ); +} + +define pcodeop vftintrml.l.s; + +#lsx.txt vftintrml.l.s mask=0x729e8800 +#0x729e8800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrml.l.s vrD, vrJ is op10_31=0x1ca7a2 & vrD & vrJ { + vrD = vftintrml.l.s(vrD, vrJ); +} + +define pcodeop vftintrmh.l.s; + +#lsx.txt vftintrmh.l.s mask=0x729e8c00 +#0x729e8c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrmh.l.s vrD, vrJ is op10_31=0x1ca7a3 & vrD & vrJ { + vrD = vftintrmh.l.s(vrD, vrJ); +} + +define pcodeop vftintrpl.l.s; + +#lsx.txt vftintrpl.l.s mask=0x729e9000 +#0x729e9000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrpl.l.s vrD, vrJ is op10_31=0x1ca7a4 & vrD & vrJ { + vrD = vftintrpl.l.s(vrD, vrJ); +} + +define pcodeop vftintrph.l.s; + +#lsx.txt vftintrph.l.s mask=0x729e9400 +#0x729e9400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrph.l.s vrD, vrJ is op10_31=0x1ca7a5 & vrD & vrJ { + vrD = vftintrph.l.s(vrD, vrJ); +} + +define pcodeop vftintrzl.l.s; + +#lsx.txt vftintrzl.l.s mask=0x729e9800 +#0x729e9800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrzl.l.s vrD, vrJ is op10_31=0x1ca7a6 & vrD & vrJ { + vrD = vftintrzl.l.s(vrD, vrJ); +} + +define pcodeop vftintrzh.l.s; + +#lsx.txt vftintrzh.l.s mask=0x729e9c00 +#0x729e9c00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrzh.l.s vrD, vrJ is op10_31=0x1ca7a7 & vrD & vrJ { + vrD = vftintrzh.l.s(vrD, vrJ); +} + +define pcodeop vftintrnel.l.s; + +#lsx.txt vftintrnel.l.s mask=0x729ea000 +#0x729ea000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrnel.l.s vrD, vrJ is op10_31=0x1ca7a8 & vrD & vrJ { + vrD = vftintrnel.l.s(vrD, vrJ); +} + +define pcodeop vftintrneh.l.s; + +#lsx.txt vftintrneh.l.s mask=0x729ea400 +#0x729ea400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vftintrneh.l.s vrD, vrJ is op10_31=0x1ca7a9 & vrD & vrJ { + vrD = vftintrneh.l.s(vrD, vrJ); +} + +define pcodeop vexth.h.b; + +#lsx.txt vexth.h.b mask=0x729ee000 +#0x729ee000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vexth.h.b vrD, vrJ is op10_31=0x1ca7b8 & vrD & vrJ { + vrD = vexth.h.b(vrD, vrJ); +} + +define pcodeop vexth.w.h; + +#lsx.txt vexth.w.h mask=0x729ee400 +#0x729ee400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vexth.w.h vrD, vrJ is op10_31=0x1ca7b9 & vrD & vrJ { + vrD = vexth.w.h(vrD, vrJ); +} + +define pcodeop vexth.d.w; + +#lsx.txt vexth.d.w mask=0x729ee800 +#0x729ee800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vexth.d.w vrD, vrJ is op10_31=0x1ca7ba & vrD & vrJ { + vrD = vexth.d.w(vrD, vrJ); +} + +define pcodeop vexth.q.d; + +#lsx.txt vexth.q.d mask=0x729eec00 +#0x729eec00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vexth.q.d vrD, vrJ is op10_31=0x1ca7bb & vrD & vrJ { + vrD = vexth.q.d(vrD, vrJ); +} + +define pcodeop vexth.hu.bu; + +#lsx.txt vexth.hu.bu mask=0x729ef000 +#0x729ef000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vexth.hu.bu vrD, vrJ is op10_31=0x1ca7bc & vrD & vrJ { + vrD = vexth.hu.bu(vrD, vrJ); +} + +define pcodeop vexth.wu.hu; + +#lsx.txt vexth.wu.hu mask=0x729ef400 +#0x729ef400 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vexth.wu.hu vrD, vrJ is op10_31=0x1ca7bd & vrD & vrJ { + vrD = vexth.wu.hu(vrD, vrJ); +} + +define pcodeop vexth.du.wu; + +#lsx.txt vexth.du.wu mask=0x729ef800 +#0x729ef800 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vexth.du.wu vrD, vrJ is op10_31=0x1ca7be & vrD & vrJ { + vrD = vexth.du.wu(vrD, vrJ); +} + +define pcodeop vexth.qu.du; + +#lsx.txt vexth.qu.du mask=0x729efc00 +#0x729efc00 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vexth.qu.du vrD, vrJ is op10_31=0x1ca7bf & vrD & vrJ { + vrD = vexth.qu.du(vrD, vrJ); +} + +define pcodeop vreplgr2vr.b; + +#lsx.txt vreplgr2vr.b mask=0x729f0000 +#0x729f0000 0xfffffc00 v0:5, r5:5 ['vreg0_5_s0', 'reg5_5_s0'] +:vreplgr2vr.b vrD, RJsrc is op10_31=0x1ca7c0 & vrD & RJsrc { + vrD = vreplgr2vr.b(vrD, RJsrc); +} + +define pcodeop vreplgr2vr.h; + +#lsx.txt vreplgr2vr.h mask=0x729f0400 +#0x729f0400 0xfffffc00 v0:5, r5:5 ['vreg0_5_s0', 'reg5_5_s0'] +:vreplgr2vr.h vrD, RJsrc is op10_31=0x1ca7c1 & vrD & RJsrc { + vrD = vreplgr2vr.h(vrD, RJsrc); +} + +define pcodeop vreplgr2vr.w; + +#lsx.txt vreplgr2vr.w mask=0x729f0800 +#0x729f0800 0xfffffc00 v0:5, r5:5 ['vreg0_5_s0', 'reg5_5_s0'] +:vreplgr2vr.w vrD, RJsrc is op10_31=0x1ca7c2 & vrD & RJsrc { + vrD = vreplgr2vr.w(vrD, RJsrc); +} + +define pcodeop vreplgr2vr.d; + +#lsx.txt vreplgr2vr.d mask=0x729f0c00 +#0x729f0c00 0xfffffc00 v0:5, r5:5 ['vreg0_5_s0', 'reg5_5_s0'] +:vreplgr2vr.d vrD, RJsrc is op10_31=0x1ca7c3 & vrD & RJsrc { + vrD = vreplgr2vr.d(vrD, RJsrc); +} + +define pcodeop vrotri.b; + +#lsx.txt vrotri.b mask=0x72a02000 +#0x72a02000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vrotri.b vrD, vrJ, imm10_3 is op13_31=0x39501 & vrD & vrJ & imm10_3 { + vrD = vrotri.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vrotri.h; + +#lsx.txt vrotri.h mask=0x72a04000 +#0x72a04000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vrotri.h vrD, vrJ, imm10_4 is op14_31=0x1ca81 & vrD & vrJ & imm10_4 { + vrD = vrotri.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vrotri.w; + +#lsx.txt vrotri.w mask=0x72a08000 +#0x72a08000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vrotri.w vrD, vrJ, imm10_5 is op15_31=0xe541 & vrD & vrJ & imm10_5 { + vrD = vrotri.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vrotri.d; + +#lsx.txt vrotri.d mask=0x72a10000 +#0x72a10000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vrotri.d vrD, vrJ, imm10_6 is op16_31=0x72a1 & vrD & vrJ & imm10_6 { + vrD = vrotri.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrlri.b; + +#lsx.txt vsrlri.b mask=0x72a42000 +#0x72a42000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vsrlri.b vrD, vrJ, imm10_3 is op13_31=0x39521 & vrD & vrJ & imm10_3 { + vrD = vsrlri.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vsrlri.h; + +#lsx.txt vsrlri.h mask=0x72a44000 +#0x72a44000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsrlri.h vrD, vrJ, imm10_4 is op14_31=0x1ca91 & vrD & vrJ & imm10_4 { + vrD = vsrlri.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsrlri.w; + +#lsx.txt vsrlri.w mask=0x72a48000 +#0x72a48000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsrlri.w vrD, vrJ, imm10_5 is op15_31=0xe549 & vrD & vrJ & imm10_5 { + vrD = vsrlri.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsrlri.d; + +#lsx.txt vsrlri.d mask=0x72a50000 +#0x72a50000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsrlri.d vrD, vrJ, imm10_6 is op16_31=0x72a5 & vrD & vrJ & imm10_6 { + vrD = vsrlri.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrari.b; + +#lsx.txt vsrari.b mask=0x72a82000 +#0x72a82000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vsrari.b vrD, vrJ, imm10_3 is op13_31=0x39541 & vrD & vrJ & imm10_3 { + vrD = vsrari.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vsrari.h; + +#lsx.txt vsrari.h mask=0x72a84000 +#0x72a84000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsrari.h vrD, vrJ, imm10_4 is op14_31=0x1caa1 & vrD & vrJ & imm10_4 { + vrD = vsrari.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsrari.w; + +#lsx.txt vsrari.w mask=0x72a88000 +#0x72a88000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsrari.w vrD, vrJ, imm10_5 is op15_31=0xe551 & vrD & vrJ & imm10_5 { + vrD = vsrari.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsrari.d; + +#lsx.txt vsrari.d mask=0x72a90000 +#0x72a90000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsrari.d vrD, vrJ, imm10_6 is op16_31=0x72a9 & vrD & vrJ & imm10_6 { + vrD = vsrari.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vinsgr2vr.b; + +#lsx.txt vinsgr2vr.b mask=0x72eb8000 +#0x72eb8000 0xffffc000 v0:5, r5:5,u10:4 ['vreg0_5_s0', 'reg5_5_s0', 'imm10_4_s0'] +:vinsgr2vr.b vrD, RJsrc, imm10_4 is op14_31=0x1cbae & vrD & RJsrc & imm10_4 { + vrD = vinsgr2vr.b(vrD, RJsrc, imm10_4:$(REGSIZE)); +} + +define pcodeop vinsgr2vr.h; + +#lsx.txt vinsgr2vr.h mask=0x72ebc000 +#0x72ebc000 0xffffe000 v0:5, r5:5,u10:3 ['vreg0_5_s0', 'reg5_5_s0', 'imm10_3_s0'] +:vinsgr2vr.h vrD, RJsrc, imm10_3 is op13_31=0x3975e & vrD & RJsrc & imm10_3 { + vrD = vinsgr2vr.h(vrD, RJsrc, imm10_3:$(REGSIZE)); +} + +define pcodeop vinsgr2vr.w; + +#lsx.txt vinsgr2vr.w mask=0x72ebe000 +#0x72ebe000 0xfffff000 v0:5, r5:5,u10:2 ['vreg0_5_s0', 'reg5_5_s0', 'imm10_2_s0'] +:vinsgr2vr.w vrD, RJsrc, imm10_2 is op12_31=0x72ebe & vrD & RJsrc & imm10_2 { + vrD = vinsgr2vr.w(vrD, RJsrc, imm10_2:$(REGSIZE)); +} + +define pcodeop vinsgr2vr.d; + +#lsx.txt vinsgr2vr.d mask=0x72ebf000 +#0x72ebf000 0xfffff800 v0:5, r5:5,u10:1 ['vreg0_5_s0', 'reg5_5_s0', 'imm10_1_s0'] +:vinsgr2vr.d vrD, RJsrc, imm10_1 is op11_31=0xe5d7e & vrD & RJsrc & imm10_1 { + vrD = vinsgr2vr.d(vrD, RJsrc, imm10_1:$(REGSIZE)); +} + +define pcodeop vpickve2gr.b; + +#lsx.txt vpickve2gr.b mask=0x72ef8000 +#0x72ef8000 0xffffc000 r0:5,v5:5,u10:4 ['reg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vpickve2gr.b RD, vrJ, imm10_4 is op14_31=0x1cbbe & RD & vrJ & imm10_4 { + RD = vpickve2gr.b(RD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vpickve2gr.h; + +#lsx.txt vpickve2gr.h mask=0x72efc000 +#0x72efc000 0xffffe000 r0:5,v5:5,u10:3 ['reg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vpickve2gr.h RD, vrJ, imm10_3 is op13_31=0x3977e & RD & vrJ & imm10_3 { + RD = vpickve2gr.h(RD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vpickve2gr.w; + +#lsx.txt vpickve2gr.w mask=0x72efe000 +#0x72efe000 0xfffff000 r0:5,v5:5,u10:2 ['reg0_5_s0', 'vreg5_5_s0', 'imm10_2_s0'] +:vpickve2gr.w RD, vrJ, imm10_2 is op12_31=0x72efe & RD & vrJ & imm10_2 { + RD = vpickve2gr.w(RD, vrJ, imm10_2:$(REGSIZE)); +} + +define pcodeop vpickve2gr.d; + +#lsx.txt vpickve2gr.d mask=0x72eff000 +#0x72eff000 0xfffff800 r0:5,v5:5,u10:1 ['reg0_5_s0', 'vreg5_5_s0', 'imm10_1_s0'] +:vpickve2gr.d RD, vrJ, imm10_1 is op11_31=0xe5dfe & RD & vrJ & imm10_1 { + RD = vpickve2gr.d(RD, vrJ, imm10_1:$(REGSIZE)); +} + +define pcodeop vpickve2gr.bu; + +#lsx.txt vpickve2gr.bu mask=0x72f38000 +#0x72f38000 0xffffc000 r0:5,v5:5,u10:4 ['reg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vpickve2gr.bu RD, vrJ, imm10_4 is op14_31=0x1cbce & RD & vrJ & imm10_4 { + RD = vpickve2gr.bu(RD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vpickve2gr.hu; + +#lsx.txt vpickve2gr.hu mask=0x72f3c000 +#0x72f3c000 0xffffe000 r0:5,v5:5,u10:3 ['reg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vpickve2gr.hu RD, vrJ, imm10_3 is op13_31=0x3979e & RD & vrJ & imm10_3 { + RD = vpickve2gr.hu(RD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vpickve2gr.wu; + +#lsx.txt vpickve2gr.wu mask=0x72f3e000 +#0x72f3e000 0xfffff000 r0:5,v5:5,u10:2 ['reg0_5_s0', 'vreg5_5_s0', 'imm10_2_s0'] +:vpickve2gr.wu RD, vrJ, imm10_2 is op12_31=0x72f3e & RD & vrJ & imm10_2 { + RD = vpickve2gr.wu(RD, vrJ, imm10_2:$(REGSIZE)); +} + +define pcodeop vpickve2gr.du; + +#lsx.txt vpickve2gr.du mask=0x72f3f000 +#0x72f3f000 0xfffff800 r0:5,v5:5,u10:1 ['reg0_5_s0', 'vreg5_5_s0', 'imm10_1_s0'] +:vpickve2gr.du RD, vrJ, imm10_1 is op11_31=0xe5e7e & RD & vrJ & imm10_1 { + RD = vpickve2gr.du(RD, vrJ, imm10_1:$(REGSIZE)); +} + +define pcodeop vreplvei.b; + +#lsx.txt vreplvei.b mask=0x72f78000 +#0x72f78000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vreplvei.b vrD, vrJ, imm10_4 is op14_31=0x1cbde & vrD & vrJ & imm10_4 { + vrD = vreplvei.b(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vreplvei.h; + +#lsx.txt vreplvei.h mask=0x72f7c000 +#0x72f7c000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vreplvei.h vrD, vrJ, imm10_3 is op13_31=0x397be & vrD & vrJ & imm10_3 { + vrD = vreplvei.h(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vreplvei.w; + +#lsx.txt vreplvei.w mask=0x72f7e000 +#0x72f7e000 0xfffff000 v0:5,v5:5,u10:2 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_2_s0'] +:vreplvei.w vrD, vrJ, imm10_2 is op12_31=0x72f7e & vrD & vrJ & imm10_2 { + vrD = vreplvei.w(vrD, vrJ, imm10_2:$(REGSIZE)); +} + +define pcodeop vreplvei.d; + +#lsx.txt vreplvei.d mask=0x72f7f000 +#0x72f7f000 0xfffff800 v0:5,v5:5,u10:1 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_1_s0'] +:vreplvei.d vrD, vrJ, imm10_1 is op11_31=0xe5efe & vrD & vrJ & imm10_1 { + vrD = vreplvei.d(vrD, vrJ, imm10_1:$(REGSIZE)); +} + +define pcodeop vsllwil.h.b; + +#lsx.txt vsllwil.h.b mask=0x73082000 +#0x73082000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vsllwil.h.b vrD, vrJ, imm10_3 is op13_31=0x39841 & vrD & vrJ & imm10_3 { + vrD = vsllwil.h.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vsllwil.w.h; + +#lsx.txt vsllwil.w.h mask=0x73084000 +#0x73084000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsllwil.w.h vrD, vrJ, imm10_4 is op14_31=0x1cc21 & vrD & vrJ & imm10_4 { + vrD = vsllwil.w.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsllwil.d.w; + +#lsx.txt vsllwil.d.w mask=0x73088000 +#0x73088000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsllwil.d.w vrD, vrJ, imm10_5 is op15_31=0xe611 & vrD & vrJ & imm10_5 { + vrD = vsllwil.d.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vextl.q.d; + +#lsx.txt vextl.q.d mask=0x73090000 +#0x73090000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vextl.q.d vrD, vrJ is op10_31=0x1cc240 & vrD & vrJ { + vrD = vextl.q.d(vrD, vrJ); +} + +define pcodeop vsllwil.hu.bu; + +#lsx.txt vsllwil.hu.bu mask=0x730c2000 +#0x730c2000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vsllwil.hu.bu vrD, vrJ, imm10_3 is op13_31=0x39861 & vrD & vrJ & imm10_3 { + vrD = vsllwil.hu.bu(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vsllwil.wu.hu; + +#lsx.txt vsllwil.wu.hu mask=0x730c4000 +#0x730c4000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsllwil.wu.hu vrD, vrJ, imm10_4 is op14_31=0x1cc31 & vrD & vrJ & imm10_4 { + vrD = vsllwil.wu.hu(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsllwil.du.wu; + +#lsx.txt vsllwil.du.wu mask=0x730c8000 +#0x730c8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsllwil.du.wu vrD, vrJ, imm10_5 is op15_31=0xe619 & vrD & vrJ & imm10_5 { + vrD = vsllwil.du.wu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vextl.qu.du; + +#lsx.txt vextl.qu.du mask=0x730d0000 +#0x730d0000 0xfffffc00 v0:5,v5:5 ['vreg0_5_s0', 'vreg5_5_s0'] +:vextl.qu.du vrD, vrJ is op10_31=0x1cc340 & vrD & vrJ { + vrD = vextl.qu.du(vrD, vrJ); +} + +define pcodeop vbitclri.b; + +#lsx.txt vbitclri.b mask=0x73102000 +#0x73102000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vbitclri.b vrD, vrJ, imm10_3 is op13_31=0x39881 & vrD & vrJ & imm10_3 { + vrD = vbitclri.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vbitclri.h; + +#lsx.txt vbitclri.h mask=0x73104000 +#0x73104000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vbitclri.h vrD, vrJ, imm10_4 is op14_31=0x1cc41 & vrD & vrJ & imm10_4 { + vrD = vbitclri.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vbitclri.w; + +#lsx.txt vbitclri.w mask=0x73108000 +#0x73108000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vbitclri.w vrD, vrJ, imm10_5 is op15_31=0xe621 & vrD & vrJ & imm10_5 { + vrD = vbitclri.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vbitclri.d; + +#lsx.txt vbitclri.d mask=0x73110000 +#0x73110000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vbitclri.d vrD, vrJ, imm10_6 is op16_31=0x7311 & vrD & vrJ & imm10_6 { + vrD = vbitclri.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vbitseti.b; + +#lsx.txt vbitseti.b mask=0x73142000 +#0x73142000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vbitseti.b vrD, vrJ, imm10_3 is op13_31=0x398a1 & vrD & vrJ & imm10_3 { + vrD = vbitseti.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vbitseti.h; + +#lsx.txt vbitseti.h mask=0x73144000 +#0x73144000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vbitseti.h vrD, vrJ, imm10_4 is op14_31=0x1cc51 & vrD & vrJ & imm10_4 { + vrD = vbitseti.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vbitseti.w; + +#lsx.txt vbitseti.w mask=0x73148000 +#0x73148000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vbitseti.w vrD, vrJ, imm10_5 is op15_31=0xe629 & vrD & vrJ & imm10_5 { + vrD = vbitseti.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vbitseti.d; + +#lsx.txt vbitseti.d mask=0x73150000 +#0x73150000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vbitseti.d vrD, vrJ, imm10_6 is op16_31=0x7315 & vrD & vrJ & imm10_6 { + vrD = vbitseti.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vbitrevi.b; + +#lsx.txt vbitrevi.b mask=0x73182000 +#0x73182000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vbitrevi.b vrD, vrJ, imm10_3 is op13_31=0x398c1 & vrD & vrJ & imm10_3 { + vrD = vbitrevi.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vbitrevi.h; + +#lsx.txt vbitrevi.h mask=0x73184000 +#0x73184000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vbitrevi.h vrD, vrJ, imm10_4 is op14_31=0x1cc61 & vrD & vrJ & imm10_4 { + vrD = vbitrevi.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vbitrevi.w; + +#lsx.txt vbitrevi.w mask=0x73188000 +#0x73188000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vbitrevi.w vrD, vrJ, imm10_5 is op15_31=0xe631 & vrD & vrJ & imm10_5 { + vrD = vbitrevi.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vbitrevi.d; + +#lsx.txt vbitrevi.d mask=0x73190000 +#0x73190000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vbitrevi.d vrD, vrJ, imm10_6 is op16_31=0x7319 & vrD & vrJ & imm10_6 { + vrD = vbitrevi.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsat.b; + +#lsx.txt vsat.b mask=0x73242000 +#0x73242000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vsat.b vrD, vrJ, imm10_3 is op13_31=0x39921 & vrD & vrJ & imm10_3 { + vrD = vsat.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vsat.h; + +#lsx.txt vsat.h mask=0x73244000 +#0x73244000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsat.h vrD, vrJ, imm10_4 is op14_31=0x1cc91 & vrD & vrJ & imm10_4 { + vrD = vsat.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsat.w; + +#lsx.txt vsat.w mask=0x73248000 +#0x73248000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsat.w vrD, vrJ, imm10_5 is op15_31=0xe649 & vrD & vrJ & imm10_5 { + vrD = vsat.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsat.d; + +#lsx.txt vsat.d mask=0x73250000 +#0x73250000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsat.d vrD, vrJ, imm10_6 is op16_31=0x7325 & vrD & vrJ & imm10_6 { + vrD = vsat.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsat.bu; + +#lsx.txt vsat.bu mask=0x73282000 +#0x73282000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vsat.bu vrD, vrJ, imm10_3 is op13_31=0x39941 & vrD & vrJ & imm10_3 { + vrD = vsat.bu(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vsat.hu; + +#lsx.txt vsat.hu mask=0x73284000 +#0x73284000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsat.hu vrD, vrJ, imm10_4 is op14_31=0x1cca1 & vrD & vrJ & imm10_4 { + vrD = vsat.hu(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsat.wu; + +#lsx.txt vsat.wu mask=0x73288000 +#0x73288000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsat.wu vrD, vrJ, imm10_5 is op15_31=0xe651 & vrD & vrJ & imm10_5 { + vrD = vsat.wu(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsat.du; + +#lsx.txt vsat.du mask=0x73290000 +#0x73290000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsat.du vrD, vrJ, imm10_6 is op16_31=0x7329 & vrD & vrJ & imm10_6 { + vrD = vsat.du(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vslli.b; + +#lsx.txt vslli.b mask=0x732c2000 +#0x732c2000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vslli.b vrD, vrJ, imm10_3 is op13_31=0x39961 & vrD & vrJ & imm10_3 { + vrD = vslli.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vslli.h; + +#lsx.txt vslli.h mask=0x732c4000 +#0x732c4000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vslli.h vrD, vrJ, imm10_4 is op14_31=0x1ccb1 & vrD & vrJ & imm10_4 { + vrD = vslli.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vslli.w; + +#lsx.txt vslli.w mask=0x732c8000 +#0x732c8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vslli.w vrD, vrJ, imm10_5 is op15_31=0xe659 & vrD & vrJ & imm10_5 { + vrD = vslli.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vslli.d; + +#lsx.txt vslli.d mask=0x732d0000 +#0x732d0000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vslli.d vrD, vrJ, imm10_6 is op16_31=0x732d & vrD & vrJ & imm10_6 { + vrD = vslli.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrli.b; + +#lsx.txt vsrli.b mask=0x73302000 +#0x73302000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vsrli.b vrD, vrJ, imm10_3 is op13_31=0x39981 & vrD & vrJ & imm10_3 { + vrD = vsrli.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vsrli.h; + +#lsx.txt vsrli.h mask=0x73304000 +#0x73304000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsrli.h vrD, vrJ, imm10_4 is op14_31=0x1ccc1 & vrD & vrJ & imm10_4 { + vrD = vsrli.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsrli.w; + +#lsx.txt vsrli.w mask=0x73308000 +#0x73308000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsrli.w vrD, vrJ, imm10_5 is op15_31=0xe661 & vrD & vrJ & imm10_5 { + vrD = vsrli.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsrli.d; + +#lsx.txt vsrli.d mask=0x73310000 +#0x73310000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsrli.d vrD, vrJ, imm10_6 is op16_31=0x7331 & vrD & vrJ & imm10_6 { + vrD = vsrli.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrai.b; + +#lsx.txt vsrai.b mask=0x73342000 +#0x73342000 0xffffe000 v0:5,v5:5,u10:3 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_3_s0'] +:vsrai.b vrD, vrJ, imm10_3 is op13_31=0x399a1 & vrD & vrJ & imm10_3 { + vrD = vsrai.b(vrD, vrJ, imm10_3:$(REGSIZE)); +} + +define pcodeop vsrai.h; + +#lsx.txt vsrai.h mask=0x73344000 +#0x73344000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsrai.h vrD, vrJ, imm10_4 is op14_31=0x1ccd1 & vrD & vrJ & imm10_4 { + vrD = vsrai.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsrai.w; + +#lsx.txt vsrai.w mask=0x73348000 +#0x73348000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsrai.w vrD, vrJ, imm10_5 is op15_31=0xe669 & vrD & vrJ & imm10_5 { + vrD = vsrai.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsrai.d; + +#lsx.txt vsrai.d mask=0x73350000 +#0x73350000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsrai.d vrD, vrJ, imm10_6 is op16_31=0x7335 & vrD & vrJ & imm10_6 { + vrD = vsrai.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrlni.b.h; + +#lsx.txt vsrlni.b.h mask=0x73404000 +#0x73404000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsrlni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd01 & vrD & vrJ & imm10_4 { + vrD = vsrlni.b.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsrlni.h.w; + +#lsx.txt vsrlni.h.w mask=0x73408000 +#0x73408000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsrlni.h.w vrD, vrJ, imm10_5 is op15_31=0xe681 & vrD & vrJ & imm10_5 { + vrD = vsrlni.h.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsrlni.w.d; + +#lsx.txt vsrlni.w.d mask=0x73410000 +#0x73410000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsrlni.w.d vrD, vrJ, imm10_6 is op16_31=0x7341 & vrD & vrJ & imm10_6 { + vrD = vsrlni.w.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrlni.d.q; + +#lsx.txt vsrlni.d.q mask=0x73420000 +#0x73420000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vsrlni.d.q vrD, vrJ, imm10_7 is op17_31=0x39a1 & vrD & vrJ & imm10_7 { + vrD = vsrlni.d.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vsrlrni.b.h; + +#lsx.txt vsrlrni.b.h mask=0x73444000 +#0x73444000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsrlrni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd11 & vrD & vrJ & imm10_4 { + vrD = vsrlrni.b.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsrlrni.h.w; + +#lsx.txt vsrlrni.h.w mask=0x73448000 +#0x73448000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsrlrni.h.w vrD, vrJ, imm10_5 is op15_31=0xe689 & vrD & vrJ & imm10_5 { + vrD = vsrlrni.h.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsrlrni.w.d; + +#lsx.txt vsrlrni.w.d mask=0x73450000 +#0x73450000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsrlrni.w.d vrD, vrJ, imm10_6 is op16_31=0x7345 & vrD & vrJ & imm10_6 { + vrD = vsrlrni.w.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrlrni.d.q; + +#lsx.txt vsrlrni.d.q mask=0x73460000 +#0x73460000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vsrlrni.d.q vrD, vrJ, imm10_7 is op17_31=0x39a3 & vrD & vrJ & imm10_7 { + vrD = vsrlrni.d.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vssrlni.b.h; + +#lsx.txt vssrlni.b.h mask=0x73484000 +#0x73484000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vssrlni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd21 & vrD & vrJ & imm10_4 { + vrD = vssrlni.b.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vssrlni.h.w; + +#lsx.txt vssrlni.h.w mask=0x73488000 +#0x73488000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vssrlni.h.w vrD, vrJ, imm10_5 is op15_31=0xe691 & vrD & vrJ & imm10_5 { + vrD = vssrlni.h.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vssrlni.w.d; + +#lsx.txt vssrlni.w.d mask=0x73490000 +#0x73490000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vssrlni.w.d vrD, vrJ, imm10_6 is op16_31=0x7349 & vrD & vrJ & imm10_6 { + vrD = vssrlni.w.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vssrlni.d.q; + +#lsx.txt vssrlni.d.q mask=0x734a0000 +#0x734a0000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vssrlni.d.q vrD, vrJ, imm10_7 is op17_31=0x39a5 & vrD & vrJ & imm10_7 { + vrD = vssrlni.d.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vssrlni.bu.h; + +#lsx.txt vssrlni.bu.h mask=0x734c4000 +#0x734c4000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vssrlni.bu.h vrD, vrJ, imm10_4 is op14_31=0x1cd31 & vrD & vrJ & imm10_4 { + vrD = vssrlni.bu.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vssrlni.hu.w; + +#lsx.txt vssrlni.hu.w mask=0x734c8000 +#0x734c8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vssrlni.hu.w vrD, vrJ, imm10_5 is op15_31=0xe699 & vrD & vrJ & imm10_5 { + vrD = vssrlni.hu.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vssrlni.wu.d; + +#lsx.txt vssrlni.wu.d mask=0x734d0000 +#0x734d0000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vssrlni.wu.d vrD, vrJ, imm10_6 is op16_31=0x734d & vrD & vrJ & imm10_6 { + vrD = vssrlni.wu.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vssrlni.du.q; + +#lsx.txt vssrlni.du.q mask=0x734e0000 +#0x734e0000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vssrlni.du.q vrD, vrJ, imm10_7 is op17_31=0x39a7 & vrD & vrJ & imm10_7 { + vrD = vssrlni.du.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vssrlrni.b.h; + +#lsx.txt vssrlrni.b.h mask=0x73504000 +#0x73504000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vssrlrni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd41 & vrD & vrJ & imm10_4 { + vrD = vssrlrni.b.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vssrlrni.h.w; + +#lsx.txt vssrlrni.h.w mask=0x73508000 +#0x73508000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vssrlrni.h.w vrD, vrJ, imm10_5 is op15_31=0xe6a1 & vrD & vrJ & imm10_5 { + vrD = vssrlrni.h.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vssrlrni.w.d; + +#lsx.txt vssrlrni.w.d mask=0x73510000 +#0x73510000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vssrlrni.w.d vrD, vrJ, imm10_6 is op16_31=0x7351 & vrD & vrJ & imm10_6 { + vrD = vssrlrni.w.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vssrlrni.d.q; + +#lsx.txt vssrlrni.d.q mask=0x73520000 +#0x73520000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vssrlrni.d.q vrD, vrJ, imm10_7 is op17_31=0x39a9 & vrD & vrJ & imm10_7 { + vrD = vssrlrni.d.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vssrlrni.bu.h; + +#lsx.txt vssrlrni.bu.h mask=0x73544000 +#0x73544000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vssrlrni.bu.h vrD, vrJ, imm10_4 is op14_31=0x1cd51 & vrD & vrJ & imm10_4 { + vrD = vssrlrni.bu.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vssrlrni.hu.w; + +#lsx.txt vssrlrni.hu.w mask=0x73548000 +#0x73548000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vssrlrni.hu.w vrD, vrJ, imm10_5 is op15_31=0xe6a9 & vrD & vrJ & imm10_5 { + vrD = vssrlrni.hu.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vssrlrni.wu.d; + +#lsx.txt vssrlrni.wu.d mask=0x73550000 +#0x73550000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vssrlrni.wu.d vrD, vrJ, imm10_6 is op16_31=0x7355 & vrD & vrJ & imm10_6 { + vrD = vssrlrni.wu.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vssrlrni.du.q; + +#lsx.txt vssrlrni.du.q mask=0x73560000 +#0x73560000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vssrlrni.du.q vrD, vrJ, imm10_7 is op17_31=0x39ab & vrD & vrJ & imm10_7 { + vrD = vssrlrni.du.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vsrani.b.h; + +#lsx.txt vsrani.b.h mask=0x73584000 +#0x73584000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsrani.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd61 & vrD & vrJ & imm10_4 { + vrD = vsrani.b.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsrani.h.w; + +#lsx.txt vsrani.h.w mask=0x73588000 +#0x73588000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsrani.h.w vrD, vrJ, imm10_5 is op15_31=0xe6b1 & vrD & vrJ & imm10_5 { + vrD = vsrani.h.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsrani.w.d; + +#lsx.txt vsrani.w.d mask=0x73590000 +#0x73590000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsrani.w.d vrD, vrJ, imm10_6 is op16_31=0x7359 & vrD & vrJ & imm10_6 { + vrD = vsrani.w.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrani.d.q; + +#lsx.txt vsrani.d.q mask=0x735a0000 +#0x735a0000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vsrani.d.q vrD, vrJ, imm10_7 is op17_31=0x39ad & vrD & vrJ & imm10_7 { + vrD = vsrani.d.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vsrarni.b.h; + +#lsx.txt vsrarni.b.h mask=0x735c4000 +#0x735c4000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vsrarni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd71 & vrD & vrJ & imm10_4 { + vrD = vsrarni.b.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vsrarni.h.w; + +#lsx.txt vsrarni.h.w mask=0x735c8000 +#0x735c8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vsrarni.h.w vrD, vrJ, imm10_5 is op15_31=0xe6b9 & vrD & vrJ & imm10_5 { + vrD = vsrarni.h.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vsrarni.w.d; + +#lsx.txt vsrarni.w.d mask=0x735d0000 +#0x735d0000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vsrarni.w.d vrD, vrJ, imm10_6 is op16_31=0x735d & vrD & vrJ & imm10_6 { + vrD = vsrarni.w.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vsrarni.d.q; + +#lsx.txt vsrarni.d.q mask=0x735e0000 +#0x735e0000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vsrarni.d.q vrD, vrJ, imm10_7 is op17_31=0x39af & vrD & vrJ & imm10_7 { + vrD = vsrarni.d.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vssrani.b.h; + +#lsx.txt vssrani.b.h mask=0x73604000 +#0x73604000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vssrani.b.h vrD, vrJ, imm10_4 is op14_31=0x1cd81 & vrD & vrJ & imm10_4 { + vrD = vssrani.b.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vssrani.h.w; + +#lsx.txt vssrani.h.w mask=0x73608000 +#0x73608000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vssrani.h.w vrD, vrJ, imm10_5 is op15_31=0xe6c1 & vrD & vrJ & imm10_5 { + vrD = vssrani.h.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vssrani.w.d; + +#lsx.txt vssrani.w.d mask=0x73610000 +#0x73610000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vssrani.w.d vrD, vrJ, imm10_6 is op16_31=0x7361 & vrD & vrJ & imm10_6 { + vrD = vssrani.w.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vssrani.d.q; + +#lsx.txt vssrani.d.q mask=0x73620000 +#0x73620000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vssrani.d.q vrD, vrJ, imm10_7 is op17_31=0x39b1 & vrD & vrJ & imm10_7 { + vrD = vssrani.d.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vssrani.bu.h; + +#lsx.txt vssrani.bu.h mask=0x73644000 +#0x73644000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vssrani.bu.h vrD, vrJ, imm10_4 is op14_31=0x1cd91 & vrD & vrJ & imm10_4 { + vrD = vssrani.bu.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vssrani.hu.w; + +#lsx.txt vssrani.hu.w mask=0x73648000 +#0x73648000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vssrani.hu.w vrD, vrJ, imm10_5 is op15_31=0xe6c9 & vrD & vrJ & imm10_5 { + vrD = vssrani.hu.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vssrani.wu.d; + +#lsx.txt vssrani.wu.d mask=0x73650000 +#0x73650000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vssrani.wu.d vrD, vrJ, imm10_6 is op16_31=0x7365 & vrD & vrJ & imm10_6 { + vrD = vssrani.wu.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vssrani.du.q; + +#lsx.txt vssrani.du.q mask=0x73660000 +#0x73660000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vssrani.du.q vrD, vrJ, imm10_7 is op17_31=0x39b3 & vrD & vrJ & imm10_7 { + vrD = vssrani.du.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vssrarni.b.h; + +#lsx.txt vssrarni.b.h mask=0x73684000 +#0x73684000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vssrarni.b.h vrD, vrJ, imm10_4 is op14_31=0x1cda1 & vrD & vrJ & imm10_4 { + vrD = vssrarni.b.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vssrarni.h.w; + +#lsx.txt vssrarni.h.w mask=0x73688000 +#0x73688000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vssrarni.h.w vrD, vrJ, imm10_5 is op15_31=0xe6d1 & vrD & vrJ & imm10_5 { + vrD = vssrarni.h.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vssrarni.w.d; + +#lsx.txt vssrarni.w.d mask=0x73690000 +#0x73690000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vssrarni.w.d vrD, vrJ, imm10_6 is op16_31=0x7369 & vrD & vrJ & imm10_6 { + vrD = vssrarni.w.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vssrarni.d.q; + +#lsx.txt vssrarni.d.q mask=0x736a0000 +#0x736a0000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vssrarni.d.q vrD, vrJ, imm10_7 is op17_31=0x39b5 & vrD & vrJ & imm10_7 { + vrD = vssrarni.d.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vssrarni.bu.h; + +#lsx.txt vssrarni.bu.h mask=0x736c4000 +#0x736c4000 0xffffc000 v0:5,v5:5,u10:4 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_4_s0'] +:vssrarni.bu.h vrD, vrJ, imm10_4 is op14_31=0x1cdb1 & vrD & vrJ & imm10_4 { + vrD = vssrarni.bu.h(vrD, vrJ, imm10_4:$(REGSIZE)); +} + +define pcodeop vssrarni.hu.w; + +#lsx.txt vssrarni.hu.w mask=0x736c8000 +#0x736c8000 0xffff8000 v0:5,v5:5,u10:5 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_5_s0'] +:vssrarni.hu.w vrD, vrJ, imm10_5 is op15_31=0xe6d9 & vrD & vrJ & imm10_5 { + vrD = vssrarni.hu.w(vrD, vrJ, imm10_5:$(REGSIZE)); +} + +define pcodeop vssrarni.wu.d; + +#lsx.txt vssrarni.wu.d mask=0x736d0000 +#0x736d0000 0xffff0000 v0:5,v5:5,u10:6 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_6_s0'] +:vssrarni.wu.d vrD, vrJ, imm10_6 is op16_31=0x736d & vrD & vrJ & imm10_6 { + vrD = vssrarni.wu.d(vrD, vrJ, imm10_6:$(REGSIZE)); +} + +define pcodeop vssrarni.du.q; + +#lsx.txt vssrarni.du.q mask=0x736e0000 +#0x736e0000 0xfffe0000 v0:5,v5:5,u10:7 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_7_s0'] +:vssrarni.du.q vrD, vrJ, imm10_7 is op17_31=0x39b7 & vrD & vrJ & imm10_7 { + vrD = vssrarni.du.q(vrD, vrJ, imm10_7:$(REGSIZE)); +} + +define pcodeop vextrins.d; + +#lsx.txt vextrins.d mask=0x73800000 +#0x73800000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vextrins.d vrD, vrJ, imm10_8 is op18_31=0x1ce0 & vrD & vrJ & imm10_8 { + vrD = vextrins.d(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vextrins.w; + +#lsx.txt vextrins.w mask=0x73840000 +#0x73840000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vextrins.w vrD, vrJ, imm10_8 is op18_31=0x1ce1 & vrD & vrJ & imm10_8 { + vrD = vextrins.w(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vextrins.h; + +#lsx.txt vextrins.h mask=0x73880000 +#0x73880000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vextrins.h vrD, vrJ, imm10_8 is op18_31=0x1ce2 & vrD & vrJ & imm10_8 { + vrD = vextrins.h(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vextrins.b; + +#lsx.txt vextrins.b mask=0x738c0000 +#0x738c0000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vextrins.b vrD, vrJ, imm10_8 is op18_31=0x1ce3 & vrD & vrJ & imm10_8 { + vrD = vextrins.b(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vshuf4i.b; + +#lsx.txt vshuf4i.b mask=0x73900000 +#0x73900000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vshuf4i.b vrD, vrJ, imm10_8 is op18_31=0x1ce4 & vrD & vrJ & imm10_8 { + vrD = vshuf4i.b(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vshuf4i.h; + +#lsx.txt vshuf4i.h mask=0x73940000 +#0x73940000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vshuf4i.h vrD, vrJ, imm10_8 is op18_31=0x1ce5 & vrD & vrJ & imm10_8 { + vrD = vshuf4i.h(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vshuf4i.w; + +#lsx.txt vshuf4i.w mask=0x73980000 +#0x73980000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vshuf4i.w vrD, vrJ, imm10_8 is op18_31=0x1ce6 & vrD & vrJ & imm10_8 { + vrD = vshuf4i.w(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vshuf4i.d; + +#lsx.txt vshuf4i.d mask=0x739c0000 +#0x739c0000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vshuf4i.d vrD, vrJ, imm10_8 is op18_31=0x1ce7 & vrD & vrJ & imm10_8 { + vrD = vshuf4i.d(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vbitseli.b; + +#lsx.txt vbitseli.b mask=0x73c40000 +#0x73c40000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vbitseli.b vrD, vrJ, imm10_8 is op18_31=0x1cf1 & vrD & vrJ & imm10_8 { + vrD = vbitseli.b(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vandi.b; + +#lsx.txt vandi.b mask=0x73d00000 +#0x73d00000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vandi.b vrD, vrJ, imm10_8 is op18_31=0x1cf4 & vrD & vrJ & imm10_8 { + vrD = vandi.b(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vori.b; + +#lsx.txt vori.b mask=0x73d40000 +#0x73d40000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vori.b vrD, vrJ, imm10_8 is op18_31=0x1cf5 & vrD & vrJ & imm10_8 { + vrD = vori.b(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vxori.b; + +#lsx.txt vxori.b mask=0x73d80000 +#0x73d80000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vxori.b vrD, vrJ, imm10_8 is op18_31=0x1cf6 & vrD & vrJ & imm10_8 { + vrD = vxori.b(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vnori.b; + +#lsx.txt vnori.b mask=0x73dc0000 +#0x73dc0000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vnori.b vrD, vrJ, imm10_8 is op18_31=0x1cf7 & vrD & vrJ & imm10_8 { + vrD = vnori.b(vrD, vrJ, imm10_8:$(REGSIZE)); +} + +define pcodeop vldi; + +#lsx.txt vldi mask=0x73e00000 +#0x73e00000 0xfffc0000 v0:5, s5:13 ['vreg0_5_s0', 'simm5_13_s0'] +:vldi vrD, simm5_13 is op18_31=0x1cf8 & vrD & simm5_13 { + vrD = vldi(vrD, simm5_13:$(REGSIZE)); +} + +define pcodeop vpermi.w; + +#lsx.txt vpermi.w mask=0x73e40000 +#0x73e40000 0xfffc0000 v0:5,v5:5,u10:8 ['vreg0_5_s0', 'vreg5_5_s0', 'imm10_8_s0'] +:vpermi.w vrD, vrJ, imm10_8 is op18_31=0x1cf9 & vrD & vrJ & imm10_8 { + vrD = vpermi.w(vrD, vrJ, imm10_8:$(REGSIZE)); +} + diff --git a/Ghidra/Processors/Loongarch/data/languages/lvz.sinc b/Ghidra/Processors/Loongarch/data/languages/lvz.sinc new file mode 100644 index 0000000000..5062508c11 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/lvz.sinc @@ -0,0 +1,59 @@ +define pcodeop gcsrxchg; + +#lvz.txt gcsrxchg mask=0x05000000 [@lvz] +#0x05000000 0xff000000 r0:5, r5:5,u10:14 ['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0'] +:gcsrxchg RD, RJsrc,imm10_14 is op24_31=0x5 & RD & RJsrc & imm10_14 { + RD = gcsrxchg(RD, RJsrc, imm10_14:$(REGSIZE)); +} + +define pcodeop gtlbclr; + +#lvz.txt gtlbclr mask=0x06482001 [@lvz] +:gtlbclr is instword=0x06482001 { + gtlbclr(); +} + +define pcodeop gtlbflush; + +#lvz.txt gtlbflush mask=0x06482401 [@lvz] +#0x06482401 0xffffffff [''] +:gtlbflush is instword=0x06482401 { + gtlbflush(); +} + +define pcodeop gtlbsrch; + +#lvz.txt gtlbsrch mask=0x06482801 [@lvz] +:gtlbsrch is instword=0x06482801 { + gtlbsrch(); +} + +define pcodeop gtlbrd; + +#lvz.txt gtlbrd mask=0x06482c01 [@lvz] +:gtlbrd is instword=0x06482c01 { + gtlbrd(); +} + +define pcodeop gtlbwr; + +#lvz.txt gtlbwr mask=0x06483001 [@lvz] +:gtlbwr is instword=0x06483001 { + gtlbwr(); +} + +define pcodeop gtlbfill; + +#lvz.txt gtlbfill mask=0x06483401 [@lvz] +:gtlbfill is instword=0x06483401 { + gtlbfill(); +} + +define pcodeop hvcl; + +#lvz.txt hypcall mask=0x002b8000 [@lvz, @orig_name=hvcl] +#0x002b8000 0xffff8000 u0:15 ['imm0_15_s0'] +:hvcl imm0_15 is op15_31=0x57 & imm0_15 { + hvcl(imm0_15:$(REGSIZE)); +} + diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc new file mode 100644 index 0000000000..463f177c92 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc @@ -0,0 +1,172 @@ +#la-privileged-32.txt csrxchg mask=0x04000000 [@primary] +#0x04000000 0xff000000 r0:5,r5:5,u10:14 ['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0'] +csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] {local tmp:$(REGSIZE) = csr; export *[register]:$(REGSIZE) tmp; } + +:csrxchg RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr { + local csrval:$(REGSIZE) = csr; + local mask = RJsrc; + csr = RD & mask; + RD = csrval & mask; +} + +:cssrd RD, csr is op24_31=0x4 & RD & op5_9=0 & csr { + RD = csr; +} + +:cssrw RD, csr is op24_31=0x4 & RD & op5_9=1 & csr { + local csrval:$(REGSIZE) = csr; + csr = RD; + RD = csrval; +} + +define pcodeop cacop; +#la-privileged-32.txt cacop mask=0x06000000 [@orig_fmt=Ud5JSk12, @primary] +#0x06000000 0xffc00000 u0:5,r5:5,s10:12 ['imm0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] +cache_obj: op0_2 is op0_2 { local tmp:1 = op0_2; export *[const]:1 tmp; } +op_type: "initialization" is op3_4=0 { export 0:1; } +op_type: "consistency" is op3_4=1 { export 1:1; } +op_type: "coherency" is op3_4=2 { export 2:1; } +op_type: "Custom" is op3_4=3 { export 3:1; } + +:cacop op_type^"("^cache_obj^")", ldst_addr is op22_31=0x18 & cache_obj & op_type & ldst_addr { + cacop(op_type, cache_obj, ldst_addr); +} + + +define pcodeop lddir; +level: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } +#la-privileged-32.txt lddir mask=0x06400000 +#0x06400000 0xfffc0000 r0:5,r5:5,u10:8 ['reg0_5_s0', 'reg5_5_s0', 'imm10_8_s0'] +:lddir RD, RJsrc, level is op18_31=0x190 & RD & RJsrc & level { + RD = lddir(RJsrc, level); +} + + +define pcodeop ldpte; +seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } +#la-privileged-32.txt ldpte mask=0x06440000 +#0x06440000 0xfffc001f r5:5,u10:8 ['reg5_5_s0', 'imm10_8_s0'] +:ldpte RJsrc, seq is op18_31=0x191 & op0_4=0x0 & RJsrc & seq { + ldpte(RJsrc, seq); +} + + + +#la-privileged-32.txt iocsrrd.b mask=0x06480000 +#0x06480000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrrd.b RD, RJsrc is op10_31=0x19200 & RD & RJsrc { + local val:1 = iocsrrd(RJsrc, 1:1); + RD = sext(val); +} + + +#la-privileged-32.txt iocsrrd.h mask=0x06480400 +#0x06480400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrrd.h RD, RJsrc is op10_31=0x19201 & RD & RJsrc { + local val:2 = iocsrrd(RJsrc, 2:1); + RD = sext(val); +} + + +#la-privileged-32.txt iocsrrd.w mask=0x06480800 +#0x06480800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrrd.w RD, RJsrc is op10_31=0x19202 & RD & RJsrc { + local val:4 = iocsrrd(RJsrc, 4:1); + RD = sext(val); +} + + + +#la-privileged-32.txt iocsrwr.b mask=0x06481000 +#0x06481000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrwr.b RD, RJsrc is op10_31=0x19204 & RD & RJsrc { + iocsrwr(RD, RJsrc, 1:1); +} + + +#la-privileged-32.txt iocsrwr.h mask=0x06481400 +#0x06481400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrwr.h RD, RJsrc is op10_31=0x19205 & RD & RJsrc { + iocsrwr(RD, RJsrc, 2:1); +} + + +#la-privileged-32.txt iocsrwr.w mask=0x06481800 +#0x06481800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrwr.w RD, RJsrc is op10_31=0x19206 & RD & RJsrc { + iocsrwr(RD, RJsrc, 4:1); +} + + +define pcodeop tlbclr; +#la-privileged-32.txt tlbclr mask=0x06482000 +#0x06482000 0xffffffff +:tlbclr is instword=0x06482000 { + tlbclr(); +} + + +define pcodeop tlbflush; +#la-privileged-32.txt tlbflush mask=0x06482400 +#0x06482400 0xffffffff +:tlbflush is instword=0x06482400 { + tlbflush(); +} + + +define pcodeop tlbsrch; +#la-privileged-32.txt tlbsrch mask=0x06482800 [@primary] +#0x06482800 0xffffffff +:tlbsrch is instword=0x06482800 { + tlbsrch(); +} + + +define pcodeop tlbrd; +#la-privileged-32.txt tlbrd mask=0x06482c00 [@primary] +#0x06482c00 0xffffffff +:tlbrd is instword=0x06482c00 { + tlbrd(); +} + + +define pcodeop tlbwr; +#la-privileged-32.txt tlbwr mask=0x06483000 [@primary] +#0x06483000 0xffffffff +:tlbwr is instword=0x06483000 { + tlbwr(); +} + + +define pcodeop tlbfill; +#la-privileged-32.txt tlbfill mask=0x06483400 [@primary] +#0x06483400 0xffffffff +:tlbfill is instword=0x06483400 { + tlbfill(); +} + + +define pcodeop ertn; +#la-privileged-32.txt eret mask=0x06483800 [@orig_name=ertn, @primary] +#0x06483800 0xffffffff +:ertn is instword=0x06483800 { + ertn(); +} + + +define pcodeop idle; +#la-privileged-32.txt idle mask=0x06488000 [@primary] +#0x06488000 0xffff8000 u0:15 ['imm0_15_s0'] +:idle imm0_15 is op15_31=0xc91 & imm0_15 { + idle(imm0_15:2); +} + + +define pcodeop invtlb; +#la-privileged-32.txt tlbinv mask=0x06498000 [@orig_name=invtlb, @orig_fmt=Ud5JK, @primary] +#0x06498000 0xffff8000 u0:5,r5:5,r10:5 ['imm0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:invtlb RJsrc, RKsrc, imm0_5 is op15_31=0xc93 & RJsrc & RKsrc & imm0_5 { + invtlb(RJsrc, RKsrc, imm0_5:1); +} + + diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc new file mode 100644 index 0000000000..e76db485ac --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc @@ -0,0 +1,14 @@ +#la-privileged-64.txt iocsrrd.d mask=0x06480c00 +#0x06480c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrrd.d RD, RJsrc is op10_31=0x19203 & RD & RJsrc { + RD = iocsrrd(RJsrc, 8:1); +} + + +#la-privileged-64.txt iocsrwr.d mask=0x06481c00 +#0x06481c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrwr.d RD, RJsrc is op10_31=0x19207 & RD & RJsrc { + iocsrwr(RD, RJsrc, 64:1); +} + + diff --git a/Ghidra/Processors/Loongarch/data/manuals/loongarch.idx b/Ghidra/Processors/Loongarch/data/manuals/loongarch.idx new file mode 100644 index 0000000000..be43b7a53a --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/manuals/loongarch.idx @@ -0,0 +1,181 @@ +@LoongArch-Vol1-EN.pdf[LoongArch Reference Manual - Volume 1: Basic Architecture] +add, 23 +sub, 23 +addi, 24 +addu16id, 24 +alsl, 25 +lu12i.w, 26 +lu32i.d, 26 +lu52i.d, 26 +slt, 26 +sltu, 26 +slti, 27 +sltui, 27 +pcaddi, 28 +pcaddu12i, 28 +pcaddu18i, 28 +pcalau12i, 28 +and, 29 +or, 29 +nor, 29 +xor, 29 +andn, 29 +orn, 29 +andi, 30 +ori, 30 +xori, 30 +mul, 31 +mulh, 31 +mulw, 32 +div, 32 +mod, 32 +sll.w, 34 +srl.w, 34 +sra.w, 34 +rotr.w, 34 +slli.w, 35 +srli.w, 35 +srai.w, 35 +rotri.w, 35 +sll.d, 36 +srl.d, 36 +sra.d, 36 +rotr.d, 36 +slli.d, 37 +srli.d, 37 +srai.d, 37 +rotri.d, 37 +ext.w.b, 38 +ext.w.h, 38 +clo, 38 +clz, 38 +cto, 38 +ctz, 38 +bytepick, 40 +revb, 40 +revh, 41 +bitrev.4b, 42 +bitrev.8b, 42 +bitrev.w, 43 +bitrev.d, 43 +bstrins, 43 +bstrpick, 44 +maskeqz, 44 +masknez, 44 +beq, 45 +bne, 45 +blt, 45 +bge, 45 +bltu, 45 +bgeu, 45 +beqz, 46 +bnez, 46 +b, 47 +bl, 47 +jirl, 48 +ld, 49 +st, 49 +ldx, 51 +stx, 51 +ldptr, 53 +stptr, 53 +preld, 54 +preldx, 55 +lgdt, 56 +ldle, 56 +stgt, 56 +stle, 56 +amswap, 60 +amadd, 60 +amand, 60 +amor, 60 +amxor, 60 +ammax, 60 +ammin, 60 +ll, 62 +sc, 62 +dbar, 62 +ibar, 63 +crc, 63 +crcc, 63 +syscall, 64 +break, 64 +asrtle, 65 +asrtgt, 65 +rdtime, 65 +rdtimel, 65 +rdtimeh, 65 +cpucfg, 65 +fadd, 78 +fsub, 78 +fmul, 78 +fmadd, 80 +fmsub, 80 +fnmadd, 80 +fnmsub, 80 +fmax, 81 +fmin, 81 +fmaxa, 82 +fmina, 82 +fabs, 83 +fneg, 83 +fsqrt, 83 +frecip, 83 +frsqrt, 83 +fscaleb, 85 +flogb, 85 +fcopysign, 85 +fclass, 86 +fcmp, 86 +fcvt, 88 +ffint, 88 +ftint, 88 +ftintrm, 90 +ftintrp, 90 +ftintrz, 90 +ftintrne, 90 +frint, 92 +fmov, 93 +fsel, 94 +movgr2fr, 94 +movgr2frh, 94 +movfr2gr, 95 +movfrh2gr, 95 +movgr2fcsr, 95 +movfcsr2gr, 95 +movfr2cf, 96 +movcf2fr, 96 +movgr2cf, 96 +movcf2gr, 96 +bceqz, 97 +bcnez, 97 +fld, 97 +fst, 97 +fldx, 98 +fstx, 98 +fldgt, 100 +fldle, 100 +fstgt, 100 +fstle, 100 +csrrd, 103 +csrwr, 103 +csrxchg, 103 +iocsrrd, 104 +iocsrwr, 104 +cacop, 104 +tlbsrch, 105 +tlbrd, 106 +tlbwr, 106 +tlbfill, 106 +tlbclr, 107 +tlbflush, 107 +invtlb, 107 +lddir, 108 +ldpte, 108 +ertn, 109 +dbcl, 110 +idle, 110 + + + + diff --git a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java new file mode 100644 index 0000000000..f4049951e6 --- /dev/null +++ b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class Loongarch64_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "Loongarch:LE:64:default"; + private static final String COMPILER_SPEC_ID = "default"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public Loongarch64_O0_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "Loongarch64_GCC_O0"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(Loongarch64_O0_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java new file mode 100644 index 0000000000..81cbaab6b1 --- /dev/null +++ b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class Loongarch64_O3_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "Loongarch:LE:64:default"; + private static final String COMPILER_SPEC_ID = "default"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public Loongarch64_O3_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "Loongarch64_GCC_O3"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(Loongarch64_O3_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64f_O0_EmulatorTest.java b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64f_O0_EmulatorTest.java new file mode 100644 index 0000000000..07b6701fba --- /dev/null +++ b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64f_O0_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class Loongarch64f_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "Loongarch:LE:64:lp64f"; + private static final String COMPILER_SPEC_ID = "default"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public Loongarch64f_O0_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "Loongarch64f_GCC_O0"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(Loongarch64f_O0_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64f_O3_EmulatorTest.java b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64f_O3_EmulatorTest.java new file mode 100644 index 0000000000..edee05f26f --- /dev/null +++ b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64f_O3_EmulatorTest.java @@ -0,0 +1,40 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class Loongarch64f_O3_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "Loongarch:LE:64:lp64f"; + private static final String COMPILER_SPEC_ID = "default"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public Loongarch64f_O3_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + } + + @Override + protected String getProcessorDesignator() { + return "Loongarch64f_GCC_O3"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(Loongarch64f_O3_EmulatorTest.class); + } +} From 8004108681ee75c784db5c35ad76df0ba92e0cf6 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Tue, 15 Aug 2023 15:53:42 +0000 Subject: [PATCH 02/15] GP-3211: Refactored pcodetest scripts --- .../Extensions/SleighDevTools/pcodetest/build | 61 ++++++++++++++----- .../pcodetest/c_src/BIOPS_DOUBLE_BODY.c | 13 ++++ .../pcodetest/c_src/BIOPS_FLOAT_BODY.c | 13 ---- .../SleighDevTools/pcodetest/c_src/types.h | 6 +- .../SleighDevTools/pcodetest/defaults.py | 6 +- .../SleighDevTools/pcodetest/pcode_defs.py | 26 ++++++++ .../SleighDevTools/pcodetest/pcodetest.py | 5 +- 7 files changed, 95 insertions(+), 35 deletions(-) diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/build b/Ghidra/Extensions/SleighDevTools/pcodetest/build index 90070c2114..0e3b899ea6 100755 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/build +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/build @@ -13,14 +13,39 @@ from pcodetest import * # set default properties first, then update values from the command # line before they are instantiated. + +def test_action(action_class, deprecate=False): + class pcodeTestAction(action_class): + def __call__(self, parser, namespace, values, option_string=None): + c = getattr(namespace, 'command_count', 0) + setattr(namespace, 'command_count', c+1) + + if deprecate: + print('Deprecated pcodetest command\n\tuse --%s' % (self.dest)) + action_class.__call__(self, parser, namespace, values, option_string) + return pcodeTestAction + exec(compile(open('defaults.py', "rb").read(), 'defaults.py', 'exec')) parser = argparse.ArgumentParser(description='''Build pcodetests. One and only one of the following options must be given: -[--pcodetest, --pcodetest-all, --pcodetest-list]''', +[--test, --all, --list]''', epilog='(*) default properties for pcodetest instances', formatter_class=argparse.ArgumentDefaultsHelpFormatter) +# required alternates +required_group = parser.add_argument_group('Pcodetest Commands') + +required_group.add_argument('-t', '--test', dest='test', action=test_action(argparse._StoreAction), help='the pcode test to build') +required_group.add_argument('-a', '--all', dest='all', action=test_action(argparse._StoreTrueAction), help='build all pcode tests') +required_group.add_argument('-l', '--list', dest='list', action=test_action(argparse._StoreTrueAction), help='list available pcode tests') + +#Deprecated +required_group.add_argument('--pcodetest', dest='test', action=test_action(argparse._StoreAction, True), help=argparse.SUPPRESS) +required_group.add_argument('--pcodetest-all',dest='all', action=test_action(argparse._StoreTrueAction, True), help=argparse.SUPPRESS) +required_group.add_argument('--pcodetest-list', dest='list', action=test_action(argparse._StoreTrueAction, True), help=argparse.SUPPRESS) + + # all-applicable arguments parser.add_argument('-f', '--force', action='store_true', help='force a build') @@ -29,16 +54,10 @@ parser.add_argument('--toolchain-root', default=PCodeTest.defaults.toolchain_roo parser.add_argument('--build-root', default=PCodeTest.defaults.build_root, help='temporary directory to hold build files (*)') parser.add_argument('--gcc-version', default=PCodeTest.defaults.gcc_version, help='default version of gcc (*)') -# required alternates - -required_group = parser.add_mutually_exclusive_group(required=True) -required_group.add_argument('--pcodetest', help='the pcode test to build') -required_group.add_argument('--pcodetest-all', action='store_true', help='build all pcode tests') -required_group.add_argument('--pcodetest-list', action='store_true', help='list available pcode tests') # pcodetest arguments -pcodetest_group = parser.add_argument_group('pcodetest', 'pcodetest options') +pcodetest_group = parser.add_argument_group('Pcodetest Options') pcodetest_group.add_argument('--no-publish', action='store_true', help='do not publish pcode test binaries to pcode test root') pcodetest_group.add_argument('--pcodetest-root', default=PCodeTest.defaults.pcodetest_root, help='location to publish pcode tests binaries (*)') pcodetest_group.add_argument('--pcodetest-src', default=PCodeTest.defaults.pcodetest_src, help='location of pcode test .c and .h source files (*)') @@ -49,6 +68,7 @@ pcodetest_group.add_argument('--add-info', action='store_true', help='add data t pcodetest_group.add_argument('--build-exe', action='store_true', help='build a guest executable binary (exe)') pcodetest_group.add_argument('--variants', default=json.dumps(PCodeTest.defaults.variants, sort_keys=True, separators=(',',':')), type=json.loads, help='build the (optimization) variants, encoded as a json dict') + sys.argv.pop(0) args = parser.parse_args(sys.argv) @@ -73,9 +93,21 @@ exec(compile(open('pcode_defs.py', "rb").read(), 'pcode_defs.py', 'exec')) cwd = os.getcwd() -if args.pcodetest_list: +if not hasattr(args, 'command_count'): + print('ERROR: One of [--test, --all, --list] must be given\n') + parser.print_help() + exit() + +if args.command_count > 1: + print('ERROR: Two many commands given. Only one of [--test, --all, --list] must be given\n') + parser.print_help() + exit() + + +if args.list: PCodeTest.print_all() -elif args.pcodetest_all: + +elif args.all: for n,pct in sorted(PCodeTest.list.items(), key=lambda x: x[0].lower()): if pct.config.build_all: try: PCodeTestBuild.factory(pct).main() @@ -83,12 +115,13 @@ elif args.pcodetest_all: print('unhandled exception while building %s' % n) traceback.print_exc(file=sys.stdout) os.chdir(cwd) -elif args.pcodetest: - if args.pcodetest in PCodeTest.list: - PCodeTest = PCodeTest.list[args.pcodetest] + +elif args.test: + if args.test in PCodeTest.list: + PCodeTest = PCodeTest.list[args.test] PCodeTestBuild.factory(PCodeTest).main() else: - print('the pcode test %s is not in the list' % args.pcodetest) + print('the pcode test %s is not in the list' % args.test) else: parser.print_help() diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE_BODY.c b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE_BODY.c index cf6839ac21..98c88c2a25 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE_BODY.c +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE_BODY.c @@ -16,6 +16,19 @@ #include "pcode_test.h" #ifdef HAS_DOUBLE +f8 f8_compareLogic(f8 lhs, f8 rhs) +{ + if (lhs < 0) + lhs += 2; + if (lhs > 0) + lhs += 4; + if (lhs == 0) + lhs += 8; + if (lhs != rhs) + lhs += 16; + return lhs; +} + /* Comparison operators */ f8 f8_greaterThan(f8 lhs, f8 rhs) { diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT_BODY.c b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT_BODY.c index e4bb5dac78..c27d73f790 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT_BODY.c +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT_BODY.c @@ -29,19 +29,6 @@ f4 f4_compareLogic(f4 lhs, f4 rhs) return lhs; } -f8 f8_compareLogic(f8 lhs, f8 rhs) -{ - if (lhs < 0) - lhs += 2; - if (lhs > 0) - lhs += 4; - if (lhs == 0) - lhs += 8; - if (lhs != rhs) - lhs += 16; - return lhs; -} - /* Comparison operators */ f4 f4_greaterThan(f4 lhs, f4 rhs) { diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/types.h b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/types.h index 6f918a5b60..d02681a4ee 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/types.h +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/types.h @@ -107,6 +107,8 @@ typedef unsigned int u4; typedef signed int i4; #ifdef HAS_LONGLONG typedef long long i8; +#endif +#if defined(HAS_LONGLONG) || defined(HAS__DOUBLE) typedef unsigned long long u8; #endif #ifdef HAS_FLOAT @@ -132,6 +134,8 @@ typedef signed int i4; #endif #ifdef HAS_LONGLONG typedef long long i8; +#endif +#if defined(HAS_LONGLONG) || defined(HAS__DOUBLE) typedef unsigned long long u8; #endif #ifdef HAS_FLOAT @@ -197,10 +201,8 @@ typedef __UINT8_TYPE__ u1; typedef __UINT16_TYPE__ u2; typedef __UINT32_TYPE__ u4; #if defined(__UINT64_TYPE__) -#ifdef HAS_LONGLONG typedef __UINT64_TYPE__ u8; #endif -#endif #ifdef __SIZEOF_FLOAT__ #ifdef HAS_FLOAT diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/defaults.py b/Ghidra/Extensions/SleighDevTools/pcodetest/defaults.py index 8bc78ab34e..e397992c1f 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/defaults.py +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/defaults.py @@ -20,19 +20,17 @@ PCodeTest.defaults.toolchain_root = '/local/ToolChains' PCodeTest.defaults.build_root = '/local/build-pcodetest' -PCodeTest.defaults.gcc_version = '7.3.0' +PCodeTest.defaults.gcc_version = '9.2.0' PCodeTest.defaults.skip_files = [] PCodeTest.defaults.export_root = os.getcwd() + '/../../../../../ghidra.bin/Ghidra/Test/TestResources/data/pcodetests/' PCodeTest.defaults.pcodetest_src = os.getcwd() + '/c_src' # PCodeTest.defaults that cannot be overridden on the command line - +# These are set by processor test definitions in the pcode_defs.py file PCodeTest.defaults.build_all = 0 PCodeTest.defaults.ccflags = '' PCodeTest.defaults.has_decimal128 = 0 PCodeTest.defaults.has_decimal32 = 0 - - PCodeTest.defaults.has_decimal64 = 0 PCodeTest.defaults.has_double = 1 PCodeTest.defaults.has_float = 1 diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/pcode_defs.py b/Ghidra/Extensions/SleighDevTools/pcodetest/pcode_defs.py index ca300da20c..827aae690e 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/pcode_defs.py +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/pcode_defs.py @@ -219,6 +219,32 @@ PCodeTest({ 'architecture_test': 'PARISC', }) +PCodeTest({ + 'name': 'Loongarch64', + 'build_all': 1, + 'build_exe': 0, + 'gcc_version': '12.3.0', + 'qemu_command': 'qemu-loongarch64', + 'target': 'loongson-linux', + 'toolchain': '%(name)s/%(target)s', #%(toolchain_dir)s/lib/gcc/loongarch64-linux/%(gcc_version)s + 'ccflags': '-march=loongarch64 -mabi=lp64d -L /local/cross/lib/gcc/loongarch64-linux/12.3.0/ -lgcc', + 'language_id': 'Loongarch:LE:64:default', + #'has_longlong': 0, +}) + +PCodeTest({ + 'name': 'Loongarch64f', + 'build_all': 1, + 'build_exe': 0, + 'gcc_version': '12.3.0', + 'qemu_command': 'qemu-loongarch64', + 'target': 'loongson-linux', + 'toolchain': 'Loongarch64/%(target)s', #%(toolchain_dir)s/lib/gcc/loongarch64-linux/%(gcc_version)s + 'ccflags': '-march=loongarch64 -mabi=lp64f -mfpu=32 -L /local/cross/lib/gcc/loongarch64-linux/12.3.0/ -lgcc', + 'language_id': 'Loongarch:LE:64:lp64f', + 'has_double': 0, +}) + # Note that libgcc.a was built for m68020 which has a different function calling convention from pre-68020 diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/pcodetest.py b/Ghidra/Extensions/SleighDevTools/pcodetest/pcodetest.py index d670fc522c..3580e40a20 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/pcodetest.py +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/pcodetest.py @@ -400,9 +400,10 @@ class PCodeBuildGCC(PCodeTestBuild): # can pass this if weak symbols aren't defined # f += ['-Xlinker', '--unresolved-symbols=ignore-all'] - f += self.config.ccflags.split() - f += self.config.add_ccflags.split() + f +=[self.config.format(g) for g in self.config.ccflags.split()] + f += [self.config.format(g) for g in self.config.add_ccflags.split()] + self.log_info('Compiler flags: %s' % f) return f def compile(self, input_files, opt_cflag, output_base): From 2853f487a86364ef2b24ee012fa8d82584b3adfe Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 21 Aug 2023 15:25:15 +0000 Subject: [PATCH 03/15] GP-3211: Code review fixes --- .../pcodetest/c_src/BIOPS_DOUBLE.test | 13 ++ .../pcodetest/c_src/BIOPS_FLOAT.test | 13 -- .../languages/Loongarch32_Instructions.sinc | 193 ++++-------------- .../languages/Loongarch64_Instructions.sinc | 123 ++++++----- .../data/languages/double_Instructions.sinc | 50 ++--- .../data/languages/float_Instructions.sinc | 56 +++-- .../Loongarch/data/languages/ilp32f.cspec | 24 +-- .../Loongarch/data/languages/lasx.sinc | 10 - .../Loongarch/data/languages/lbt.sinc | 10 +- .../Loongarch/data/languages/loongarch.ldefs | 9 +- .../data/languages/loongarch_main.sinc | 25 +-- .../Loongarch/data/languages/lp64f.cspec | 15 ++ .../Loongarch/data/languages/lsx.sinc | 10 - .../data/languages/privileged-32.sinc | 5 +- .../Loongarch64_O0_EmulatorTest.java | 2 +- .../Loongarch64_O3_EmulatorTest.java | 2 +- 16 files changed, 230 insertions(+), 330 deletions(-) diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE.test b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE.test index 5738519d20..34bba39353 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE.test +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_DOUBLE.test @@ -1,5 +1,18 @@ #include "pcode_test.h" +#ifdef HAS_DOUBLE +TEST f8_compareLogic_Main() +{ + extern f8 f8_compareLogic(f8 lhs, f8 rhs); + ASSERTF8(f8_compareLogic(0x1, 0x1), 21); + ASSERTF8(f8_compareLogic(0x1, 0x2), 21); + ASSERTF8(f8_compareLogic(0x2, 0x1), 22); + ASSERTF8(f8_compareLogic(-0x1, -0x1), 21); + ASSERTF8(f8_compareLogic(-0x1, -0x2), 21); + ASSERTF8(f8_compareLogic(-0x2, -0x1), 24); +} +#endif + /* Comparison operators */ #ifdef HAS_DOUBLE TEST f8_greaterThan_Main() diff --git a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT.test b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT.test index 20f2e7a4a9..6f638105ce 100644 --- a/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT.test +++ b/Ghidra/Extensions/SleighDevTools/pcodetest/c_src/BIOPS_FLOAT.test @@ -13,19 +13,6 @@ TEST f4_compareLogic_Main() } #endif -#ifdef HAS_DOUBLE -TEST f8_compareLogic_Main() -{ - extern f8 f8_compareLogic(f8 lhs, f8 rhs); - ASSERTF8(f8_compareLogic(0x1, 0x1), 21); - ASSERTF8(f8_compareLogic(0x1, 0x2), 21); - ASSERTF8(f8_compareLogic(0x2, 0x1), 22); - ASSERTF8(f8_compareLogic(-0x1, -0x1), 21); - ASSERTF8(f8_compareLogic(-0x1, -0x2), 21); - ASSERTF8(f8_compareLogic(-0x2, -0x1), 24); -} -#endif - /* Comparison operators */ #ifdef HAS_FLOAT TEST f4_greaterThan_Main() diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc index 946ef94cc1..be0d205bc2 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc @@ -10,11 +10,7 @@ local add1:4 = RJ32src; local add2:4 = RK32src; local result = add1 + add2; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } #la-base-32.txt addi.w mask=0x02800000 [@la32, @primary, @qemu] @@ -23,11 +19,7 @@ local add1:4 = RJ32src; local add2:4 = simm10_12; local result = add1 + add2; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -35,11 +27,7 @@ #0x00040000 0xfffe0000 r0:5,r5:5,r10:5,u15:2+1 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0'] :alsl.w RD, RJ32src, RK32src, alsl_shift is op17_31=0x2 & RD & RJ32src & RK32src & alsl_shift { local result:4 = (RJ32src << alsl_shift) + RK32src; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -122,25 +110,23 @@ #la-base-32.txt lu12i.w mask=0x14000000 [@la32, @primary, @qemu] #0x14000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] :lu12i.w RD, simm12i is op25_31=0xa & RD & simm12i { -@ifdef LA64 RD = sext(simm12i); -@else - RD = simm12i; -@endif } #la-base-32.txt maskeqz mask=0x00130000 [@la32, @qemu] #0x00130000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] :maskeqz RD, RJsrc, RKsrc is op15_31=0x26 & RD & RJsrc & RKsrc { - RD = (zext(RKsrc == 0) * 0) + (zext(RKsrc != 0) * RJsrc); + local test = (RKsrc == 0); + RD = (zext(test) * 0) + (zext(!test) * RJsrc); } #la-base-32.txt masknez mask=0x00138000 [@la32, @qemu] #0x00138000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] :masknez RD, RJsrc, RKsrc is op15_31=0x27 & RD & RJsrc & RKsrc { - RD = (zext(RKsrc != 0) * 0) + (zext(RKsrc == 0) * RJsrc); + local test = (RKsrc != 0); + RD = (zext(test) * 0) + (zext(!test) * RJsrc); } @@ -275,11 +261,9 @@ local tmp1:4 = RJ32src s>> shift; local tmp2:4 = RJ32src << (32 - shift); local result = tmp1 + tmp2; -@ifdef LA64 + RD = sext(result); -@else - RD = result; -@endif + } #la-base-32.txt rotri.w mask=0x004c8000 [@la32, @qemu] @@ -289,11 +273,9 @@ local tmp1:4 = RJ32src s>> shift; local tmp2:4 = RJ32src << (32 - shift); local result = tmp1 + tmp2; -@ifdef LA64 + RD = sext(result); -@else - RD = result; -@endif + } @@ -302,11 +284,7 @@ :sll.w RD, RJ32src, RK32src is op15_31=0x2e & RD & RJ32src & RK32src { local shift:1 = RK32src(0) & 0x1f; local result:4 = RJ32src << shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } #la-base-32.txt slli.w mask=0x00408000 [@la32, @primary, @qemu] @@ -314,11 +292,7 @@ :slli.w RD, RJ32src, imm10_5 is op15_31=0x81 & RD & RJ32src& imm10_5 { local shift:1 = imm10_5 & 0x1f; local result:4 = RJ32src << shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -352,11 +326,7 @@ :srl.w RD, RJ32src, RK32src is op15_31=0x2f & RD & RJ32src & RK32src { local shift:1 = RK32src(0) & 0x1f; local result:4 = RJ32src >> shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } #la-base-32.txt srli.w mask=0x00448000 [@la32, @primary, @qemu] @@ -364,11 +334,7 @@ :srli.w RD, RJ32src, imm10_5 is op15_31=0x89 & RD & RJ32src & imm10_5 { local shift:1 = imm10_5 & 0x1f; local result:4 = RJ32src >> shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -377,11 +343,7 @@ :sra.w RD, RJ32src, RK32src is op15_31=0x30 & RD & RJ32src & RK32src { local shift:1 = RK32src(0) & 0x1f; local result:4 = RJ32src s>> shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } #la-base-32.txt srai.w mask=0x00488000 [@la32, @primary, @qemu] @@ -389,11 +351,7 @@ :srai.w RD, RJ32src, imm10_5 is op15_31=0x91 & RD & RJ32src & imm10_5 { local shift:1 = imm10_5 & 0x1f; local result:4 = RJ32src s>> shift; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -403,11 +361,7 @@ local sub1:4 = RJ32src; local sub2:4 = RK32src; local result = sub1 - sub2; -@ifdef LA64 RD = sext(result); -@else - RD = result; -@endif } @@ -440,11 +394,7 @@ #0x24000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] :ldptr.w RD, ldstptr_addr is op24_31=0x24 & RD & RJsrc & ldstptr_addr { local data:4 = *[ram]:4 ldstptr_addr; -@ifdef LA64 RD = sext(data); -@else - RD = data; -@endif } @@ -473,11 +423,7 @@ #0x28800000 0xffc00000 r0:5,r5:5,so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] :ld.w RD, ldst_addr is op22_31=0xa2 & RD & RJsrc & ldst_addr { local data:4 = *[ram]:4 ldst_addr; -@ifdef LA64 RD = sext(data); -@else - RD = data; -@endif } @@ -560,11 +506,7 @@ #0x38080000 0xffff8000 r0:5,r5:5,r10:5 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] :ldx.w RD, ldstx_addr is op15_31=0x7010 & RD & ldstx_addr { local data:4 = *[ram]:4 ldstx_addr; -@ifdef LA64 RD = sext(data); -@else - RD = data; -@endif } @@ -707,20 +649,19 @@ #la-base-32.txt jirl mask=0x4c000000 [@orig_fmt=DJSk16ps2, @la32, @primary, @qemu] #0x4c000000 0xfc000000 r0:5,r5:5,so10:16<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_16_s0'] -:jirl RD, RelJ16 is op26_31=0x13 & RD & RJsrc & offs16 & RelJ16 { +:jirl RD, RelJ16 is op26_31=0x13 & RD & RJsrc & RelJ16 { RD = inst_next; - local addr:$(ADDRSIZE) = RJsrc + (offs16 << 2); call [RelJ16]; } # alias of jirl zero, ra, 0 -:ret is op26_31=0x13 & rD=0x0 & rJ=0x1 & RJsrc & offs16=0 { +:ret is op26_31=0x13 & rD=0x0 & rJ=0x1 & RJsrc & simm10_16=0 { local retAddr = RJsrc; return [retAddr]; } # alias of jirl zer, rj, 0 -:jr RJsrc is op26_31=0x13 & rD=0x0 & RJsrc & offs16=0 { +:jr RJsrc is op26_31=0x13 & rD=0x0 & RJsrc & simm10_16=0 { local retAddr = RJsrc; return [retAddr]; } @@ -733,20 +674,14 @@ #la-atomics-32.txt ll.w mask=0x20000000 [@orig_fmt=DJSk14ps2, @la32, @primary] #0x20000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] -#TODO: FIX RELATIVE OFFSET :ll.w RD, ldstptr_addr is op24_31=0x20 & RD & ldstptr_addr { local data:4 = *[ram]:4 ldstptr_addr; -@ifdef LA64 RD = sext(data); -@else - RD = data; -@endif } #la-atomics-32.txt sc.w mask=0x21000000 [@orig_fmt=DJSk14ps2, @la32, @primary] #0x21000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] -#TODO: FIX RELATIVE OFFSET :sc.w RD, ldstptr_addr is op24_31=0x21 & RD & ldstptr_addr { *[ram]:4 ldstptr_addr = RD:4; } @@ -800,18 +735,22 @@ #la-atomics-32.txt ammax.w mask=0x38650000 [@orig_fmt=DKJ] #0x38650000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax.w RD, RJsrc, RK32src is op15_31=0x70ca & RD & RJsrc & RK32src { - local val:4 = *[ram]:4 RJsrc; - RD = sext(val); - *[ram]:4 RJsrc = (zext(RK32src s>= val) * RK32src) + (zext(RK32src s< val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 s>= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-32.txt ammin.w mask=0x38660000 [@orig_fmt=DKJ] #0x38660000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin.w RD, RJsrc, RK32src is op15_31=0x70cc & RD & RJsrc & RK32src { - local val:4 = *[ram]:4 RJsrc; - RD = sext(val); - *[ram]:4 RJsrc = (zext(RK32src s<= val) * RK32src) + (zext(RK32src s> val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 s<= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -869,9 +808,11 @@ #0x386e0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax_db.w RD, RJsrc, RK32src is op15_31=0x70dc & RD & RJsrc & RK32src { dbar(0:1); - local val:4 = *[ram]:4 RJsrc; - RD = sext(val); - *[ram]:4 RJsrc = (zext(RK32src s>= val) * RK32src) + (zext(RK32src s< val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 s>= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -879,9 +820,11 @@ #0x386f0000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin_db.w RD, RJsrc, RK32src is op15_31=0x70de & RD & RJsrc & RK32src { dbar(0:1); - local val:4 = *[ram]:4 RJsrc; - RD = sext(val); - *[ram]:4 RJsrc = (zext(RK32src s<= val) * RK32src) + (zext(RK32src s> val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 s<= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -911,11 +854,7 @@ :cto.w RD, RJ32src is op10_31=0x6 & RD & RJ32src { local tmp:4 = 0; tzcount32(~RJ32src, tmp); -@ifdef LA64 RD = zext(tmp); -@else - RD = tmp; -@endif } #la-bitops-32.txt ctz.w mask=0x00001c00 [@la32, @qemu] @@ -923,11 +862,7 @@ :ctz.w RD, RJ32src is op10_31=0x7 & RD & RJ32src { local tmp:4 = 0; tzcount32(RJ32src, tmp); -@ifdef LA64 RD = zext(tmp); -@else - RD = tmp; -@endif } @@ -936,11 +871,7 @@ :revb.2h RD, RJ32src is op10_31=0xc & RD & RJ32src { tmp0:4 = (zext(RJ32src[0,8]) << 8) + zext(RJ32src[8,8]); tmp1:4 = (zext(RJ32src[16,8]) << 8) + zext(RJ32src[24,8]); -@ifdef LA64 RD = sext((tmp1 << 16) + tmp0); -@else - RD = (tmp1 << 16) + tmp0; -@endif } @@ -949,11 +880,7 @@ :bitrev.4b RD, RJ32src is op10_31=0x12 & RD & RJ32src { local v:4 = 0; byterev32(RJ32src, v); -@ifdef LA64 RD = sext(v); -@else - RD = v; -@endif } @@ -962,11 +889,7 @@ :bitrev.w RD, RJ32src is op10_31=0x14 & RD & RJ32src { local v:4 = 0; bitrev32(RJ32src, v); -@ifdef LA64 RD = sext(v); -@else - RD = v; -@endif } @@ -977,11 +900,7 @@ local mask:4 = (1 << bitstop) - 1; local tmp_hi:4 = RK32src & ~mask; local tmp_lo:4 = (RJ32src & (mask << (32-bitstop)) >> (32-bitstop)); -@ifdef LA64 RD = sext(tmp_hi + tmp_lo); -@else - RD = tmp_hi + tmp_lo; -@endif } define pcodeop crc.w.b.w; @@ -1046,11 +965,7 @@ define pcodeop bstrins.w; local len:1 = msb + 1 - lsb; local mask:4 = (1 << len) - 1; local repl:4 = (RJ32src & (mask << lsb)) >> lsb; -@ifdef LA64 RD = sext((RD32 & (~mask)) | repl); -@else - RD = (RD & (~mask)) | repl; -@endif } @@ -1062,11 +977,7 @@ define pcodeop bstrins.w; local len:1 = msb + 1 - lsb; local mask:4 = (1 << len) - 1; local repl:4 = (RJ32src & (mask << lsb)) >> lsb; -@ifdef LA64 RD = sext(repl); -@else - RD = repl; -@endif } @@ -1078,17 +989,15 @@ define pcodeop bstrins.w; #la-bound.txt asrtle mask=0x00010000 [@orig_name=asrtle.d] #0x00010000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] :asrtle.d RJsrc, RKsrc is op15_31=0x2 & op0_4=0x0 & RJsrc & RKsrc { - if (RJsrc <= RKsrc) goto ; + if (RJsrc <= RKsrc) goto inst_next; addr_bound_exception(RJsrc, RKsrc); - } #la-bound.txt asrtgt mask=0x00018000 [@orig_name=asrtgt.d] #0x00018000 0xffff801f r5:5, r10:5 ['reg5_5_s0', 'reg10_5_s0'] :asrtgt.d RJsrc, RKsrc is op15_31=0x3 & op0_4=0x0 & RJsrc & RKsrc { - if (RJsrc > RKsrc) goto ; + if (RJsrc > RKsrc) goto inst_next; addr_bound_exception(RJsrc, RKsrc); - } @@ -1098,10 +1007,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:1 vaddr); - } #la-bound.txt ldgt.h mask=0x38788000 @@ -1110,10 +1018,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:2 vaddr); - } #la-bound.txt ldgt.w mask=0x38790000 @@ -1122,10 +1029,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:4 vaddr); - } @@ -1135,10 +1041,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:1 vaddr); - } #la-bound.txt ldle.h mask=0x387a8000 @@ -1147,10 +1052,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:2 vaddr); - } #la-bound.txt ldle.w mask=0x387b0000 @@ -1159,10 +1063,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:4 vaddr); - } @@ -1172,10 +1075,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(vaddr, RKsrc); - goto ; + goto inst_next; *[ram]:1 RJsrc = RDsrc:1; - } #la-bound.txt stgt.h mask=0x387c8000 @@ -1184,10 +1086,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(vaddr, RKsrc); - goto ; + goto inst_next; *[ram]:2 vaddr = RDsrc:2; - } #la-bound.txt stgt.w mask=0x387d0000 @@ -1196,10 +1097,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:4 vaddr = RDsrc:4; - } #la-bound.txt stle.b mask=0x387e0000 @@ -1208,10 +1108,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:1 vaddr = RDsrc:1; - } #la-bound.txt stle.h mask=0x387e8000 @@ -1220,10 +1119,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:2 vaddr = RDsrc:2; - } #la-bound.txt stle.w mask=0x387f0000 @@ -1232,10 +1130,9 @@ define pcodeop bstrins.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:4 vaddr = RDsrc:4; - } diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc index 15859141ed..b3f142e728 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc @@ -31,11 +31,7 @@ #0x00060000 0xfffe0000 r0:5,r5:5,r10:5,u15:2+1 ['reg0_5_s0', 'reg5_5_s0', 'reg10_5_s0', 'imm15_2+1_s0'] :alsl.wu RD, RJ32src, RK32src, alsl_shift is op17_31=0x3 & RD & RJ32src & RK32src & alsl_shift { local result:4 = (RJ32src << alsl_shift) + RK32src; -@ifdef LA64 RD = zext(result); -@else - RD = result; -@endif } @@ -204,16 +200,15 @@ #la-base-64.txt cu52i.d mask=0x03000000 [@orig_name=lu52i.d, @qemu] #0x03000000 0xffc00000 r0:5,r5:5,s10:12 ['reg0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] -:lu52i.d RD, RJsrc, simm10_12 is op22_31=0xc & RD & RJsrc & simm10_12 { - local simm52i:$(REGSIZE) = (simm10_12 << 52) + (RJsrc & 0xfffffffffffff); - RD = simm52i; +:lu52i.d RD, RJsrc, simm52i is op22_31=0xc & RD & RJsrc & simm52i { + RD = simm52i + (RJsrc & 0xfffffffffffff); } #la-base-64.txt cu32i.d mask=0x16000000 [@orig_name=lu32i.d, @qemu] #0x16000000 0xfe000000 r0:5,s5:20 ['reg0_5_s0', 'simm5_20_s0'] -:lu32i.d RD, simm5_20 is op25_31=0xb & RD & RD32 & simm5_20 { - RD = (simm5_20 << 32) + zext(RD32); +:lu32i.d RD, simm32i is op25_31=0xb & RD & RD32 & simm32i { + RD = simm32i + zext(RD32); } @@ -280,7 +275,6 @@ #la-atomics-64.txt ll.d mask=0x22000000 [@orig_fmt=DJSk14ps2] #0x22000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] -#TODO: FIX RELATIVE OFFSET :ll.d RD, ldstptr_addr is op24_31=0x22 & RD & ldstptr_addr { RD = *[ram]:8 ldstptr_addr; } @@ -288,7 +282,6 @@ #la-atomics-64.txt sc.d mask=0x23000000 [@orig_fmt=DJSk14ps2] #0x23000000 0xff000000 r0:5,r5:5,so10:14<<2 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_14_s0'] -#TODO: FIX RELATIVE OFFSET :sc.d RD, ldstptr_addr is op24_31=0x23 & RD & ldstptr_addr { *[ram]:8 ldstptr_addr = RD; } @@ -342,54 +335,66 @@ #la-atomics-64.txt ammax.d mask=0x38658000 [@orig_fmt=DKJ] #0x38658000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax.d RD, RJsrc, RKsrc is op15_31=0x70cb & RD & RJsrc & RKsrc { - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc s>= val) * RKsrc) + (zext(RKsrc s< val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 s>= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammin.d mask=0x38668000 [@orig_fmt=DKJ] #0x38668000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin.d RD, RJsrc, RKsrc is op15_31=0x70cd & RD & RJsrc & RKsrc { - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc s<= val) * RKsrc) + (zext(RKsrc s> val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 s<= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammax.wu mask=0x38670000 [@orig_fmt=DKJ] #0x38670000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax.wu RD, RJsrc, RK32src is op15_31=0x70ce & RD & RJsrc & RK32src { - local val:4 = *[ram]:4 RJsrc; - RD = zext(val); - *[ram]:4 RJsrc = (zext(RK32src >= val) * RK32src) + (zext(RK32src < val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 >= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammax.du mask=0x38678000 [@orig_fmt=DKJ] #0x38678000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax.du RD, RJsrc, RKsrc is op15_31=0x70cf & RD & RJsrc & RKsrc { - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc >= val) * RKsrc) + (zext(RKsrc < val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 >= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammin.wu mask=0x38680000 [@orig_fmt=DKJ] #0x38680000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin.wu RD, RJsrc, RK32src is op15_31=0x70d0 & RD & RJsrc & RK32src { - local val:4 = *[ram]:4 RJsrc; - RD = zext(val); - *[ram]:4 RJsrc = (zext(RK32src <= val) * RK32src) + (zext(RK32src > val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 <= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } #la-atomics-64.txt ammin.du mask=0x38688000 [@orig_fmt=DKJ] #0x38688000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin.du RD, RJsrc, RKsrc is op15_31=0x70d1 & RD & RJsrc & RKsrc { - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc <= val) * RKsrc) + (zext(RKsrc > val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 <= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -447,9 +452,11 @@ #0x386e8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax_db.d RD, RJsrc, RKsrc is op15_31=0x70dd & RD & RJsrc & RKsrc { dbar(0:1); - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc s>= val) * RKsrc) + (zext(RKsrc s< val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 s>= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -457,9 +464,11 @@ #0x386f8000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin_db.d RD, RJsrc, RKsrc is op15_31=0x70df & RD & RJsrc & RKsrc { dbar(0:1); - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc s<= val) * RKsrc) + (zext(RKsrc s> val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 s<= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -467,9 +476,11 @@ #0x38700000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax_db.wu RD, RJsrc, RK32src is op15_31=0x70e0 & RD & RJsrc & RK32src { dbar(0:1); - local val:4 = *[ram]:4 RJsrc; - RD = zext(val); - *[ram]:4 RJsrc = (zext(RK32src >= val) * RK32src) + (zext(RK32src < val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 >= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -477,9 +488,11 @@ #0x38708000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammax_db.du RD, RJsrc, RKsrc is op15_31=0x70e1 & RD & RJsrc & RKsrc { dbar(0:1); - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc >= val) * RKsrc) + (zext(RKsrc < val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 >= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -487,9 +500,11 @@ #0x38710000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin_db.wu RD, RJsrc, RK32src is op15_31=0x70e2 & RD & RJsrc & RK32src { dbar(0:1); - local val:4 = *[ram]:4 RJsrc; - RD = zext(val); - *[ram]:4 RJsrc = (zext(RK32src <= val) * RK32src) + (zext(RK32src > val) * val); + local val1:4 = *[ram]:4 RJsrc; + local val2:4 = RK32src; + local test = (val1 <= val2); + RD = sext(val1); + *[ram]:4 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -497,9 +512,11 @@ #0x38718000 0xffff8000 r0:5,r10:5,r5:5 ['reg0_5_s0', 'reg10_5_s0', 'reg5_5_s0'] :ammin_db.du RD, RJsrc, RKsrc is op15_31=0x70e3 & RD & RJsrc & RKsrc { dbar(0:1); - local val:8 = *[ram]:8 RJsrc; - RD = val; - *[ram]:8 RJsrc = (zext(RKsrc <= val) * RKsrc) + (zext(RKsrc > val) * val); + local val1:8 = *[ram]:8 RJsrc; + local val2:8 = RKsrc; + local test = (val1 <= val2); + RD = sext(val1); + *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -683,10 +700,9 @@ define pcodeop crcc.w.d.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:8 vaddr); - } #la-bound-64.txt ldle.d mask=0x387b8000 @@ -695,10 +711,9 @@ define pcodeop crcc.w.d.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; RD = sext(*[ram]:1 vaddr); - } @@ -708,10 +723,9 @@ define pcodeop crcc.w.d.w; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:8 vaddr = RDsrc:8; - } #la-bound-64.txt stle.d mask=0x387f8000 @@ -720,10 +734,9 @@ define pcodeop crcc.w.d.w; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:8 vaddr = RDsrc:8; - } diff --git a/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc index adc639eb1e..019c425c73 100644 --- a/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc @@ -34,7 +34,8 @@ :fmax.d drD, drJ, drK is op15_31=0x212 & drD & drJ & drK { local jval = drJ; local kval = drK; - drD = (zext(jval f>= kval) * jval) + (zext(jval f< kval) * jval); + local test = jval f>= kval; + drD = (zext(test) * jval) + (zext(!test) * kval); } @@ -43,7 +44,8 @@ :fmin.d drD, drJ, drK is op15_31=0x216 & drD & drJ & drK { local jval = drJ; local kval = drK; - drD = (zext(jval f<= kval) * jval) + (zext(jval f> kval) * jval); + local test = jval f<= kval; + drD = (zext(test) * jval) + (zext(!test) * kval); } @@ -52,7 +54,8 @@ :fmaxa.d drD, drJ, drK is op15_31=0x21a & drD & drJ & drK { local jval = drJ; local kval = drK; - drD = (zext(abs(jval) f>= abs(kval)) * jval) + (zext(abs(jval) f< abs(kval)) * jval); + local test = (abs(jval) f>= abs(kval)); + drD = (zext(test) * jval) + (zext(!test) * kval); } @@ -61,7 +64,8 @@ :fmina.d drD, drJ, drK is op15_31=0x21e & drD & drJ & drK { local jval = drJ; local kval = drK; - drD = (zext(abs(jval) f<= abs(kval)) * jval) + (zext(abs(jval) f> abs(kval)) * jval); + local test = (abs(jval) f<= abs(kval)); + drD = (zext(test) * jval) + (zext(!test) * kval); } @@ -279,20 +283,20 @@ drD = f- ((drJ f* drK) f- drA); } -dSNaN: "c" is cond_s = 0 { } -dSNaN: "s" is cond_s = 1 { } +dSNaN: "c" is ccf_s = 0 { } +dSNaN: "s" is ccf_s = 1 { } -dcond: dSNaN^"af" is cond=0x0 & dSNaN { DCMPR = 0; } -dcond: dSNaN^"lt" is cond=0x1 & dSNaN { DCMPR = DCMP1 f< DCMP2; } -dcond: dSNaN^"eq" is cond=0x2 & dSNaN { DCMPR = DCMP1 f== DCMP2; } -dcond: dSNaN^"le" is cond=0x3 & dSNaN { DCMPR = DCMP1 f<= DCMP2; } -dcond: dSNaN^"un" is cond=0x4 & dSNaN { DCMPR = nan(DCMP1) || nan(DCMP2); } -dcond: dSNaN^"ult" is cond=0x5 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f< DCMP2); } -dcond: dSNaN^"ueq" is cond=0x6 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f== DCMP2); } -dcond: dSNaN^"ule" is cond=0x7 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f<= DCMP2); } -dcond: dSNaN^"ne" is cond=0x8 & dSNaN { DCMPR = DCMP1 f!= DCMP2; } -dcond: dSNaN^"or" is cond=0xa & dSNaN { DCMPR = !(nan(DCMP1) || nan(DCMP2)); } -dcond: dSNaN^"une" is cond=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f!= DCMP2); } +dcond: dSNaN^"af" is ccf=0x0 & dSNaN { DCMPR = 0; } +dcond: dSNaN^"lt" is ccf=0x1 & dSNaN { DCMPR = DCMP1 f< DCMP2; } +dcond: dSNaN^"eq" is ccf=0x2 & dSNaN { DCMPR = DCMP1 f== DCMP2; } +dcond: dSNaN^"le" is ccf=0x3 & dSNaN { DCMPR = DCMP1 f<= DCMP2; } +dcond: dSNaN^"un" is ccf=0x4 & dSNaN { DCMPR = nan(DCMP1) || nan(DCMP2); } +dcond: dSNaN^"ult" is ccf=0x5 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f< DCMP2); } +dcond: dSNaN^"ueq" is ccf=0x6 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f== DCMP2); } +dcond: dSNaN^"ule" is ccf=0x7 & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f<= DCMP2); } +dcond: dSNaN^"ne" is ccf=0x8 & dSNaN { DCMPR = DCMP1 f!= DCMP2; } +dcond: dSNaN^"or" is ccf=0xa & dSNaN { DCMPR = !(nan(DCMP1) || nan(DCMP2)); } +dcond: dSNaN^"une" is ccf=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || (DCMP1 f!= DCMP2); } #la-fp-d.txt fcmp.caf.d mask=0x0c200000 #0x0c200000 0xffff8018 c0:3, f5:5, f10:5 ['fcc0_3_s0', 'freg5_5_s0', 'freg10_5_s0'] @@ -337,10 +341,9 @@ dcond: dSNaN^"une" is cond=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; drD = sext(*[ram]:8 vaddr); - } @@ -350,10 +353,9 @@ dcond: dSNaN^"une" is cond=0xc & dSNaN { DCMPR = (nan(DCMP1) || nan(DCMP2)) || local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; drD = sext(*[ram]:8 vaddr); - } define pcodeop fstgt.d; @@ -364,10 +366,9 @@ define pcodeop fstgt.d; local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:8 vaddr = drD; - } define pcodeop fstle.d; @@ -378,10 +379,9 @@ define pcodeop fstle.d; local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:8 vaddr = drD; - } diff --git a/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc index 72662a462a..c187c65257 100644 --- a/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc @@ -102,7 +102,6 @@ define pcodeop uncertain_fcsr; #la-fp.txt bcnez mask=0x48000100 [@orig_fmt=CjSd5k16ps2] #0x48000100 0xfc000300 c5:3,sb0:5|10:16<<2 ['fcc5_3_s0', 'sbranch0_0_s2'] -#TODO: FIX RELATIVE OFFSET :bcnez fccJ, Rel21 is op26_31=0x12 & fccJ & op8_9=1 & Rel21 { if(fccJ != 0) goto Rel21; } @@ -168,7 +167,8 @@ define pcodeop uncertain_fcsr; :fmax.s frD, frJ, frK is op15_31=0x211 & frD & frJ & frK { local jval = frJ; local kval = frK; - frD = (zext(jval f>= kval) * jval) + (zext(jval f< kval) * jval); + local test = (jval f>= kval); + frD = (zext(test) * jval) + (zext(!test) * kval); } #la-fp-s.txt fmin.s mask=0x010a8000 @@ -176,7 +176,8 @@ define pcodeop uncertain_fcsr; :fmin.s frD, frJ, frK is op15_31=0x215 & frD & frJ & frK { local jval = frJ; local kval = frK; - frD = (zext(jval f<= kval) * jval) + (zext(jval f> kval) * jval); + local test = (jval f<= kval); + frD = (zext(test) * jval) + (zext(!test) * kval); } @@ -185,7 +186,8 @@ define pcodeop uncertain_fcsr; :fmaxa.s frD, frJ, frK is op15_31=0x219 & frD & frJ & frK { local jval = frJ; local kval = frK; - frD = (zext(abs(jval) f>= abs(kval)) * jval) + (zext(abs(jval) f< abs(kval)) * jval); + local test = (abs(jval) f>= abs(kval)); + frD = (zext(test) * jval) + (zext(!test) * kval); } #la-fp-s.txt fmina.s mask=0x010e8000 @@ -193,7 +195,8 @@ define pcodeop uncertain_fcsr; :fmina.s frD, frJ, frK is op15_31=0x21d & frD & frJ & frK { local jval = frJ; local kval = frK; - frD = (zext(abs(jval) f<= abs(kval)) * jval) + (zext(abs(jval) f> abs(kval)) * jval); + local test = (abs(jval) f<= abs(kval)); + frD = (zext(test) * jval) + (zext(!test) * kval); } @@ -371,9 +374,8 @@ define pcodeop uncertain_fcsr; #la-fp-s.txt ffint.s.l mask=0x011d1800 #0x011d1800 0xfffffc00 f0:5,f5:5 ['freg0_5_s0', 'freg5_5_s0'] -:ffint.s.l frD,frJ is op10_31=0x4746 & frD & frJ { - local val:8 = int2float(frJ); - frD = frJ(0); +:ffint.s.l frD, drD is op10_31=0x4746 & frD & drD { + frD = int2float(drD); } @@ -411,20 +413,20 @@ define pcodeop uncertain_fcsr; *[ram]:4 ldstx_addr = frD; } -SNaN: "c" is cond_s = 0 { } -SNaN: "s" is cond_s = 1 { } +SNaN: "c" is ccf_s = 0 { } +SNaN: "s" is ccf_s = 1 { } -fcond: SNaN^"af" is cond=0x0 & SNaN { FCMPR = 0; } -fcond: SNaN^"lt" is cond=0x1 & SNaN { FCMPR = FCMP1 f< FCMP2; } -fcond: SNaN^"eq" is cond=0x2 & SNaN { FCMPR = FCMP1 f== FCMP2; } -fcond: SNaN^"le" is cond=0x3 & SNaN { FCMPR = FCMP1 f<= FCMP2; } -fcond: SNaN^"un" is cond=0x4 & SNaN { FCMPR = nan(FCMP1) || nan(FCMP2); } -fcond: SNaN^"ult" is cond=0x5 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f< FCMP2); } -fcond: SNaN^"ueq" is cond=0x6 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f== FCMP2); } -fcond: SNaN^"ule" is cond=0x7 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f<= FCMP2); } -fcond: SNaN^"ne" is cond=0x8 & SNaN { FCMPR = FCMP1 f!= FCMP2; } -fcond: SNaN^"or" is cond=0xa & SNaN { FCMPR = !(nan(FCMP1) || nan(FCMP2)); } -fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f!= FCMP2); } +fcond: SNaN^"af" is ccf=0x0 & SNaN { FCMPR = 0; } +fcond: SNaN^"lt" is ccf=0x1 & SNaN { FCMPR = FCMP1 f< FCMP2; } +fcond: SNaN^"eq" is ccf=0x2 & SNaN { FCMPR = FCMP1 f== FCMP2; } +fcond: SNaN^"le" is ccf=0x3 & SNaN { FCMPR = FCMP1 f<= FCMP2; } +fcond: SNaN^"un" is ccf=0x4 & SNaN { FCMPR = nan(FCMP1) || nan(FCMP2); } +fcond: SNaN^"ult" is ccf=0x5 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f< FCMP2); } +fcond: SNaN^"ueq" is ccf=0x6 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f== FCMP2); } +fcond: SNaN^"ule" is ccf=0x7 & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f<= FCMP2); } +fcond: SNaN^"ne" is ccf=0x8 & SNaN { FCMPR = FCMP1 f!= FCMP2; } +fcond: SNaN^"or" is ccf=0xa & SNaN { FCMPR = !(nan(FCMP1) || nan(FCMP2)); } +fcond: SNaN^"une" is ccf=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (FCMP1 f!= FCMP2); } #la-fp-s.txt fcmp.caf.s mask=0x0c100000 #0x0c100000 0xffff8018 c0:3, f5:5, f10:5 ['fcc0_3_s0', 'freg5_5_s0', 'freg10_5_s0'] @@ -442,10 +444,9 @@ fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (F local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; frD = sext(*[ram]:4 vaddr); - } @@ -455,10 +456,9 @@ fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (F local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; frD = sext(*[ram]:4 vaddr); - } @@ -468,10 +468,9 @@ fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (F local vaddr = RJsrc; if (vaddr > RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:4 vaddr = frD; - } @@ -481,9 +480,8 @@ fcond: SNaN^"une" is cond=0xc & SNaN { FCMPR = (nan(FCMP1) || nan(FCMP2)) || (F local vaddr = RJsrc; if (vaddr <= RKsrc) goto ; bound_check_exception(RJsrc, RKsrc); - goto ; + goto inst_next; *[ram]:4 vaddr = frD; - } diff --git a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec index fba9d74aba..a643556d93 100644 --- a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec @@ -29,18 +29,6 @@ - - - - - - - - - - - - @@ -65,6 +53,18 @@ + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lasx.sinc b/Ghidra/Processors/Loongarch/data/languages/lasx.sinc index 0ae4624457..9e79e3316c 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lasx.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/lasx.sinc @@ -434,7 +434,6 @@ define pcodeop xvld; #lasx.txt xvld mask=0x2c800000 #0x2c800000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :xvld xrD, RJsrc,simm10_12 is op22_31=0xb2 & xrD & RJsrc & simm10_12 { xrD = xvld(xrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -443,7 +442,6 @@ define pcodeop xvst; #lasx.txt xvst mask=0x2cc00000 #0x2cc00000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :xvst xrD, RJsrc,simm10_12 is op22_31=0xb3 & xrD & RJsrc & simm10_12 { xrD = xvst(xrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -452,7 +450,6 @@ define pcodeop xvldrepl.d; #lasx.txt xvldrepl.d mask=0x32100000 [@orig_fmt=XdJSk9ps3] #0x32100000 0xfff80000 x0:5, r5:5,so10:9<<3 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_9_s0'] -#TODO: FIX RELATIVE OFFSET :xvldrepl.d xrD, RJsrc,simm10_9 is op19_31=0x642 & xrD & RJsrc & simm10_9 { xrD = xvldrepl.d(xrD, RJsrc, simm10_9:$(REGSIZE)); } @@ -461,7 +458,6 @@ define pcodeop xvldrepl.w; #lasx.txt xvldrepl.w mask=0x32200000 [@orig_fmt=XdJSk10ps2] #0x32200000 0xfff00000 x0:5, r5:5,so10:10<<2 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_10_s0'] -#TODO: FIX RELATIVE OFFSET :xvldrepl.w xrD, RJsrc,simm10_10 is op20_31=0x322 & xrD & RJsrc & simm10_10 { xrD = xvldrepl.w(xrD, RJsrc, simm10_10:$(REGSIZE)); } @@ -470,7 +466,6 @@ define pcodeop xvldrepl.h; #lasx.txt xvldrepl.h mask=0x32400000 [@orig_fmt=XdJSk11ps1] #0x32400000 0xffe00000 x0:5, r5:5,so10:11<<1 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_11_s0'] -#TODO: FIX RELATIVE OFFSET :xvldrepl.h xrD, RJsrc,simm10_11 is op21_31=0x192 & xrD & RJsrc & simm10_11 { xrD = xvldrepl.h(xrD, RJsrc, simm10_11:$(REGSIZE)); } @@ -479,7 +474,6 @@ define pcodeop xvldrepl.b; #lasx.txt xvldrepl.b mask=0x32800000 #0x32800000 0xffc00000 x0:5, r5:5,so10:12 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :xvldrepl.b xrD, RJsrc,simm10_12 is op22_31=0xca & xrD & RJsrc & simm10_12 { xrD = xvldrepl.b(xrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -488,7 +482,6 @@ define pcodeop xvstelm.d; #lasx.txt xvstelm.d mask=0x33100000 [@orig_fmt=XdJSk8ps3Un2] #0x33100000 0xfff00000 x0:5, r5:5,so10:8<<3,u18:2 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_2_s0'] -#TODO: FIX RELATIVE OFFSET :xvstelm.d xrD, RJsrc,simm10_8, imm18_2 is op20_31=0x331 & xrD & RJsrc & simm10_8 & imm18_2 { xrD = xvstelm.d(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_2:$(REGSIZE)); } @@ -497,7 +490,6 @@ define pcodeop xvstelm.w; #lasx.txt xvstelm.w mask=0x33200000 [@orig_fmt=XdJSk8ps2Un3] #0x33200000 0xffe00000 x0:5, r5:5,so10:8<<2,u18:3 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_3_s0'] -#TODO: FIX RELATIVE OFFSET :xvstelm.w xrD, RJsrc,simm10_8, imm18_3 is op21_31=0x199 & xrD & RJsrc & simm10_8 & imm18_3 { xrD = xvstelm.w(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_3:$(REGSIZE)); } @@ -506,7 +498,6 @@ define pcodeop xvstelm.h; #lasx.txt xvstelm.h mask=0x33400000 [@orig_fmt=XdJSk8ps1Un4] #0x33400000 0xffc00000 x0:5, r5:5,so10:8<<1,u18:4 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_4_s0'] -#TODO: FIX RELATIVE OFFSET :xvstelm.h xrD, RJsrc,simm10_8, imm18_4 is op22_31=0xcd & xrD & RJsrc & simm10_8 & imm18_4 { xrD = xvstelm.h(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_4:$(REGSIZE)); } @@ -515,7 +506,6 @@ define pcodeop xvstelm.b; #lasx.txt xvstelm.b mask=0x33800000 #0x33800000 0xff800000 x0:5, r5:5,so10:8,u18:5 ['xreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_5_s0'] -#TODO: FIX RELATIVE OFFSET :xvstelm.b xrD, RJsrc,simm10_8, imm18_5 is op23_31=0x67 & xrD & RJsrc & simm10_8 & imm18_5 { xrD = xvstelm.b(xrD, RJsrc, simm10_8:$(REGSIZE), imm18_5:$(REGSIZE)); } diff --git a/Ghidra/Processors/Loongarch/data/languages/lbt.sinc b/Ghidra/Processors/Loongarch/data/languages/lbt.sinc index 1e0ae9b313..81d4b57c64 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lbt.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/lbt.sinc @@ -1330,7 +1330,6 @@ define pcodeop ldl.w; #lbt.txt ldl.w mask=0x2e000000 [@lbt] #0x2e000000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :ldl.w RD, RJ, simm10_12 is op22_31=0xb8 & RD & RJ & simm10_12 { RD = ldl.w(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1339,7 +1338,6 @@ define pcodeop ldr.w; #lbt.txt ldr.w mask=0x2e400000 [@lbt] #0x2e400000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :ldr.w RD, RJ, simm10_12 is op22_31=0xb9 & RD & RJ & simm10_12 { RD = ldr.w(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1348,7 +1346,6 @@ define pcodeop ldl.d; #lbt.txt ldl.d mask=0x2e800000 [@lbt] #0x2e800000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :ldl.d RD, RJ, simm10_12 is op22_31=0xba & RD & RJ & simm10_12 { RD = ldl.d(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1357,7 +1354,6 @@ define pcodeop ldr.d; #lbt.txt ldr.d mask=0x2ec00000 [@lbt] #0x2ec00000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :ldr.d RD, RJ, simm10_12 is op22_31=0xbb & RD & RJ & simm10_12 { RD = ldr.d(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1366,7 +1362,6 @@ define pcodeop stl.w; #lbt.txt stl.w mask=0x2f000000 [@lbt] #0x2f000000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :stl.w RD, RJ, simm10_12 is op22_31=0xbc & RD & RJ & simm10_12 { RD = stl.w(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1375,7 +1370,6 @@ define pcodeop str.w; #lbt.txt str.w mask=0x2f400000 [@lbt] #0x2f400000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :str.w RD, RJ, simm10_12 is op22_31=0xbd & RD & RJ & simm10_12 { RD = str.w(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1384,7 +1378,6 @@ define pcodeop stl.d; #lbt.txt stl.d mask=0x2f800000 [@lbt] #0x2f800000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :stl.d RD, RJ, simm10_12 is op22_31=0xbe & RD & RJ & simm10_12 { RD = stl.d(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1393,7 +1386,6 @@ define pcodeop str.d; #lbt.txt str.d mask=0x2fc00000 [@lbt] #0x2fc00000 0xffc00000 r0:5, r5:5, so10:12 ['reg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :str.d RD, RJ, simm10_12 is op22_31=0xbf & RD & RJ & simm10_12 { RD = str.d(RD, RJ, simm10_12:$(REGSIZE)); } @@ -1410,7 +1402,7 @@ define pcodeop jiscr1; #lbt.txt jiscr1 mask=0x48000300 [@lbt, @orig_fmt=Sd5k16ps2] #0x48000300 0xfc0003e0 s0:5|10:16<<2 ['simm0_0_s2'] -:jiscr1 Rel26 is op26_31=0x12 & op5_9=0x18 & off16 & Rel26 { +:jiscr1 Rel26 is op26_31=0x12 & op5_9=0x18 & Rel26 { jiscr1(Rel26); } diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs b/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs index 656cf52644..07cca957f8 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs @@ -10,7 +10,7 @@ processorspec="loongarch32.pspec" manualindexfile="../manuals/loongarch.idx" id="Loongarch:LE:32:ilp32f"> - Loongson Architecture + Loongson 3 32-bit with 32-bit FP @@ -24,7 +24,7 @@ processorspec="loongarch32.pspec" manualindexfile="../manuals/loongarch.idx" id="Loongarch:LE:32:ilp32d"> - Loongson Architecture + Loongson 3 32-bit with 64-bit FP @@ -39,8 +39,9 @@ processorspec="loongarch64.pspec" manualindexfile="../manuals/loongarch.idx" id="Loongarch:LE:64:lp64d"> - Loongson Architecture + Loongson 3 64-bit with 64-bit FP + - Loongson Architecture + Loongson 3 64-bit with 64-bit FP diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc index e7991ef90f..64c6f49911 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc @@ -1,7 +1,7 @@ define endian=little; -define alignment=1; +define alignment=4; define space ram type=ram_space size=$(REGSIZE) default; define space register type=register_space size=4; @@ -224,8 +224,8 @@ define token instr(32) op0_4 = ( 0, 4) op0_31 = ( 0,31) - cond = (16,19) - cond_s = (15,15) + ccf = (16,19) + ccf_s = (15,15) simm5_20 = ( 5,24) signed simm5_13 = ( 5,17) signed @@ -233,8 +233,7 @@ define token instr(32) simm10_8 = (10,17) signed simm10_5 = (10,14) signed simm10_14 = (10,23) signed - offs16 = (10,25) signed - off16 = (10,25) + simm10_16 = (10,25) signed simm10_12 = (10,21) signed simm10_11 = (10,20) signed simm10_10 = (10,19) signed @@ -295,6 +294,7 @@ define token instr(32) imm10_4 = (10,13) imm10_3 = (10,12) imm10_2 = (10,11) + imm10_16 = (10,25) imm10_14 = (10,23) imm10_12 = (10,21) imm10_1 = (10,10) @@ -431,7 +431,7 @@ FRK: frK is frK { export frK; } @endif # Immediate operand sub-constructors -addu16_imm: val is offs16 [val = offs16 << 16;] { export *[const]:$(REGSIZE) val; } +addu16_imm: val is simm10_16 [val = simm10_16 << 16;] { export *[const]:$(REGSIZE) val; } alsl_shift: sa2 is imm15_2 [sa2 = imm15_2 + 1;] { export *[const]:1 sa2; } @@ -446,14 +446,15 @@ pcadd12: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 12);] { expor pcala12: reloffs is simm5_20 [reloffs = (inst_start & ~0xfff) + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; } pcadd18: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 18);] { export *[const]:$(REGSIZE) reloffs; } -Rel16: reloc is offs16 [ reloc = inst_start + (offs16 << 2); ] { export *:$(ADDRSIZE) reloc; } -Rel21: reloc is off16 & simm0_5 [ reloc = inst_start + (((simm0_5 << 16) + off16) << 2); ] { export *:$(ADDRSIZE) reloc; } -Rel26: reloc is off16 & simm0_10 [ reloc = inst_start + (((simm0_10 << 16) | off16) << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel16: reloc is simm10_16 [ reloc = inst_start + (simm10_16 << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel21: reloc is imm10_16 & simm0_5 [ reloc = inst_start + (((simm0_5 << 16) + imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel26: reloc is imm10_16 & simm0_10 [ reloc = inst_start + (((simm0_10 << 16) | imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; } -RelJ16: RJsrc, offs16 is RJsrc & offs16 { local tmp:$(ADDRSIZE) = RJsrc + (offs16 << 2); export tmp; } - -simm12i: immed is simm5_20 [immed = simm5_20 << 12;] { export *[const]:$(REGSIZE) immed; } +RelJ16: RJsrc, simm10_16 is RJsrc & simm10_16 { local tmp:$(ADDRSIZE) = RJsrc + (simm10_16 << 2); export tmp; } +simm12i: immed is simm5_20 [immed = simm5_20 << 12; ] { export *[const]:$(REGSIZE) immed; } +simm32i: immed is simm5_20 [immed = simm5_20 << 32; ] { export *[const]:$(REGSIZE) immed; } +simm52i: immed is simm10_12 [immed = simm10_12 << 52; ] { export *[const]:$(REGSIZE) immed; } # general pcodeops define pcodeop break; diff --git a/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec b/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec index d5c1de2c9a..60bc475dbd 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec @@ -51,6 +51,21 @@ + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lsx.sinc b/Ghidra/Processors/Loongarch/data/languages/lsx.sinc index af1259713f..936d63a24b 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lsx.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/lsx.sinc @@ -434,7 +434,6 @@ define pcodeop vld; #lsx.txt vld mask=0x2c000000 #0x2c000000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :vld vrD, RJsrc, simm10_12 is op22_31=0xb0 & vrD & RJsrc & simm10_12 { vrD = vld(vrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -443,7 +442,6 @@ define pcodeop vst; #lsx.txt vst mask=0x2c400000 #0x2c400000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :vst vrD, RJsrc, simm10_12 is op22_31=0xb1 & vrD & RJsrc & simm10_12 { vrD = vst(vrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -452,7 +450,6 @@ define pcodeop vldrepl.d; #lsx.txt vldrepl.d mask=0x30100000 [@orig_fmt=VdJSk9ps3] #0x30100000 0xfff80000 v0:5, r5:5, so10:9<<3 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_9_s0'] -#TODO: FIX RELATIVE OFFSET :vldrepl.d vrD, RJsrc, simm10_9 is op19_31=0x602 & vrD & RJsrc & simm10_9 { vrD = vldrepl.d(vrD, RJsrc, simm10_9:$(REGSIZE)); } @@ -461,7 +458,6 @@ define pcodeop vldrepl.w; #lsx.txt vldrepl.w mask=0x30200000 [@orig_fmt=VdJSk10ps2] #0x30200000 0xfff00000 v0:5, r5:5, so10:10<<2 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_10_s0'] -#TODO: FIX RELATIVE OFFSET :vldrepl.w vrD, RJsrc, simm10_10 is op20_31=0x302 & vrD & RJsrc & simm10_10 { vrD = vldrepl.w(vrD, RJsrc, simm10_10:$(REGSIZE)); } @@ -470,7 +466,6 @@ define pcodeop vldrepl.h; #lsx.txt vldrepl.h mask=0x30400000 [@orig_fmt=VdJSk11ps1] #0x30400000 0xffe00000 v0:5, r5:5, so10:11<<1 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_11_s0'] -#TODO: FIX RELATIVE OFFSET :vldrepl.h vrD, RJsrc, simm10_11 is op21_31=0x182 & vrD & RJsrc & simm10_11 { vrD = vldrepl.h(vrD, RJsrc, simm10_11:$(REGSIZE)); } @@ -479,7 +474,6 @@ define pcodeop vldrepl.b; #lsx.txt vldrepl.b mask=0x30800000 #0x30800000 0xffc00000 v0:5, r5:5, so10:12 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] -#TODO: FIX RELATIVE OFFSET :vldrepl.b vrD, RJsrc, simm10_12 is op22_31=0xc2 & vrD & RJsrc & simm10_12 { vrD = vldrepl.b(vrD, RJsrc, simm10_12:$(REGSIZE)); } @@ -488,7 +482,6 @@ define pcodeop vstelm.d; #lsx.txt vstelm.d mask=0x31100000 [@orig_fmt=VdJSk8ps3Un1] #0x31100000 0xfff80000 v0:5, r5:5, so10:8<<3,u18:1 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_1_s0'] -#TODO: FIX RELATIVE OFFSET :vstelm.d vrD, RJsrc, simm10_8, imm18_1 is op19_31=0x622 & vrD & RJsrc & simm10_8 & imm18_1 { vrD = vstelm.d(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_1:$(REGSIZE)); } @@ -497,7 +490,6 @@ define pcodeop vstelm.w; #lsx.txt vstelm.w mask=0x31200000 [@orig_fmt=VdJSk8ps2Un2] #0x31200000 0xfff00000 v0:5, r5:5, so10:8<<2,u18:2 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_2_s0'] -#TODO: FIX RELATIVE OFFSET :vstelm.w vrD, RJsrc, simm10_8, imm18_2 is op20_31=0x312 & vrD & RJsrc & simm10_8 & imm18_2 { vrD = vstelm.w(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_2:$(REGSIZE)); } @@ -506,7 +498,6 @@ define pcodeop vstelm.h; #lsx.txt vstelm.h mask=0x31400000 [@orig_fmt=VdJSk8ps1Un3] #0x31400000 0xffe00000 v0:5, r5:5, so10:8<<1,u18:3 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_3_s0'] -#TODO: FIX RELATIVE OFFSET :vstelm.h vrD, RJsrc, simm10_8, imm18_3 is op21_31=0x18a & vrD & RJsrc & simm10_8 & imm18_3 { vrD = vstelm.h(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_3:$(REGSIZE)); } @@ -515,7 +506,6 @@ define pcodeop vstelm.b; #lsx.txt vstelm.b mask=0x31800000 #0x31800000 0xffc00000 v0:5, r5:5, so10:8,u18:4 ['vreg0_5_s0', 'reg5_5_s0', 'soffs10_8_s0', 'imm18_4_s0'] -#TODO: FIX RELATIVE OFFSET :vstelm.b vrD, RJsrc, simm10_8, imm18_4 is op22_31=0xc6 & vrD & RJsrc & simm10_8 & imm18_4 { vrD = vstelm.b(vrD, RJsrc, simm10_8:$(REGSIZE), imm18_4:$(REGSIZE)); } diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc index 463f177c92..582bd27843 100644 --- a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc @@ -1,6 +1,9 @@ #la-privileged-32.txt csrxchg mask=0x04000000 [@primary] #0x04000000 0xff000000 r0:5,r5:5,u10:14 ['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0'] -csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] {local tmp:$(REGSIZE) = csr; export *[register]:$(REGSIZE) tmp; } +csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] { + local tmp:$(REGSIZE) = csr; + export *[register]:$(REGSIZE) tmp; +} :csrxchg RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr { local csrval:$(REGSIZE) = csr; diff --git a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java index f4049951e6..bc24bf5010 100644 --- a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java +++ b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O0_EmulatorTest.java @@ -20,7 +20,7 @@ import junit.framework.Test; public class Loongarch64_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { - private static final String LANGUAGE_ID = "Loongarch:LE:64:default"; + private static final String LANGUAGE_ID = "Loongarch:LE:64:lp64d"; private static final String COMPILER_SPEC_ID = "default"; private static final String[] REG_DUMP_SET = new String[] {}; diff --git a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java index 81cbaab6b1..bcc6063d84 100644 --- a/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java +++ b/Ghidra/Processors/Loongarch/src/test.processors/java/ghidra/test/processors/Loongarch64_O3_EmulatorTest.java @@ -20,7 +20,7 @@ import junit.framework.Test; public class Loongarch64_O3_EmulatorTest extends ProcessorEmulatorTestAdapter { - private static final String LANGUAGE_ID = "Loongarch:LE:64:default"; + private static final String LANGUAGE_ID = "Loongarch:LE:64:lp64d"; private static final String COMPILER_SPEC_ID = "default"; private static final String[] REG_DUMP_SET = new String[] {}; From 81fb89e2591c7c28a6fa84c7d6e08371737a0d82 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Wed, 30 Aug 2023 14:30:36 +0000 Subject: [PATCH 04/15] GP-3211: Code review fix-up --- .../data/languages/Loongarch32_Instructions.sinc | 8 ++++++-- .../Loongarch/data/languages/privileged-32.sinc | 6 +++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc index be0d205bc2..2966aff9c4 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc @@ -579,6 +579,10 @@ call Rel26; } +:bl Rel26 is op26_31=0x15 & Rel26 & imm10_16=1 & simm0_10=0 { + ra = inst_next; + goto Rel26; +} #la-base-32.txt beq mask=0x58000000 [@orig_fmt=JDSk16ps2, @la32, @primary, @qemu] #0x58000000 0xfc000000 r5:5,r0:5,sb10:16<<2 ['reg5_5_s0', 'reg0_5_s0', 'sbranch10_16_s0'] @@ -660,10 +664,10 @@ return [retAddr]; } -# alias of jirl zer, rj, 0 +# alias of jirl zero, rj, 0 :jr RJsrc is op26_31=0x13 & rD=0x0 & RJsrc & simm10_16=0 { local retAddr = RJsrc; - return [retAddr]; + goto [retAddr]; } diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc index 582bd27843..2158a64094 100644 --- a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc @@ -1,8 +1,7 @@ #la-privileged-32.txt csrxchg mask=0x04000000 [@primary] #0x04000000 0xff000000 r0:5,r5:5,u10:14 ['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0'] csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] { - local tmp:$(REGSIZE) = csr; - export *[register]:$(REGSIZE) tmp; + export *[register]:$(REGSIZE) csr; } :csrxchg RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr { @@ -153,7 +152,8 @@ define pcodeop ertn; #la-privileged-32.txt eret mask=0x06483800 [@orig_name=ertn, @primary] #0x06483800 0xffffffff :ertn is instword=0x06483800 { - ertn(); + local ret = ertn(); + return [ret]; } From aa754f482beb06829dc61a71541bc43309f50049 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Wed, 6 Sep 2023 16:53:44 +0000 Subject: [PATCH 05/15] GP-3211: Code review fix --- .../app/util/bin/format/elf/ElfConstants.java | 57 ++++++- .../data/languages/loongarch_main.sinc | 153 ++++++++++-------- .../data/languages/privileged-32.sinc | 23 +-- .../data/languages/privileged-64.sinc | 6 +- 4 files changed, 151 insertions(+), 88 deletions(-) diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/elf/ElfConstants.java b/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/elf/ElfConstants.java index 8c910c9848..704b6e5e04 100644 --- a/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/elf/ElfConstants.java +++ b/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/elf/ElfConstants.java @@ -392,7 +392,10 @@ public interface ElfConstants { public static final short EM_TI_C2000 = 141; /** The Texas Instruments TMS320C55x DSP family */ public static final short EM_TI_C5500 = 142; - // 143 - 159 reserved + // 143 reserved + /** exas Instruments Programmable Realtime Unit */ + public static final short EM_TI_PRU = 144; + // 145 - 159 reserved /** STMicroelectronics 64bit VLIW Data Signal Processor */ public static final short EM_MMDSP_PLUS = 160; /** Cypress M8C microprocessor */ @@ -439,9 +442,10 @@ public interface ElfConstants { public static final short EM_L10M = 180; /** Intel K10M */ public static final short EM_K10M = 181; - // 182 reserved + // 182 reserved by Intel /** AARCH64 Architecture */ public static final short EM_AARCH64 = 183; + // 184 reserved by ARM /** Atmel Corporation 32-bit microprocessor family */ public static final short EM_AVR32 = 185; /** STMicroeletronics STM8 8-bit microcontroller */ @@ -480,7 +484,9 @@ public interface ElfConstants { public static final short EM_XCORE = 203; /** Microchip 8-bit PIC(r) family */ public static final short EM_MCHP_PIC = 204; - // 205 - 209 reserved by Intel + /** Intel Graphics Technology */ + public static final short EM_INTELGT = 205; + // 206 - 209 reserved by Intel /** KM211 KM32 32-bit processor */ public static final short EM_KM32 = 210; /** KM211 KMX32 32-bit processor */ @@ -501,16 +507,57 @@ public interface ElfConstants { public static final short EM_NORC = 218; /** CSR Kalimba architecture family */ public static final short EM_CSR_KALIMBA = 219; - // 220 - 223 reserved + /** Zilog Z80 */ + public static final short EM_Z80 = 220; + /** Controls and Data Services VISIUMcore processor */ + public static final short EM_VISIUM = 221; + /** FTDI Chip FT32 high performance 32-bit RISC architecture */ + public static final short EM_FT32 = 222; + /** Moxie processor family */ + public static final short EM_MOXIE = 223; /** AMD GPU architecture */ public static final short EM_AMDGPU = 224; /** RISC-V */ public static final short EM_RISCV = 243; /** Lanai 32-bit processor */ public static final short EM_LANAI = 244; + /** CEVA Processor Architecture Family */ + public static final short EM_CEVA = 245; + /** CEVA X2 Processor Family */ + public static final short EM_CEVA_X2 = 246; /** Linux kernel bpf virtual machine */ public static final short EM_BPF = 247; - + /** Graphcore Intelligent Processing Unit */ + public static final short EM_GRAPHCORE_IPU = 248; + /** Imagination Technologies */ + public static final short EM_IMG1 = 249; + /** Netronome Flow Processor. */ + public static final short EM_NFP = 250; + /** NEC Vector Engine */ + public static final short EM_VE = 251; + /** C-SKY processor family. */ + public static final short EM_CSKY = 252; + /** Synopsys ARCv2.3 64-bit */ + public static final short EM_ARC_COMPACT3_64 = 253; + /** MOS Technology MCS 6502 processor */ + public static final short EM_MCS6502 = 254; + /** Synopsys ARCv2.3 32-bit */ + public static final short EM_ARC_COMPACT3 = 255; + /** Kalray VLIW core of the MPPA processor family */ + public static final short EM_KVX = 256; + /** WDC 65816/65C816 */ + public static final short EM_65816 = 257; + /** LoongArch*/ + public static final short EM_LOONGARCH = 258; + /** ChipON KungFu32 */ + public static final short EM_KF32 = 259; + /** Linux kernel bpf virtual machine */ + public static final short EM_U16_U8CORE = 260; + /** Tachyum */ + public static final short EM_TACHYUM = 261; + /** NXP 56800EF Digital Signal Controller (DSC) */ + public static final short EM_56800EF = 262; + /** used by NetBSD/avr32 - AVR 32-bit */ public static final short EM_AVR32_unofficial = 0x18ad; diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc index 64c6f49911..66904fa451 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc @@ -3,11 +3,12 @@ define endian=little; define alignment=4; -define space ram type=ram_space size=$(REGSIZE) default; -define space register type=register_space size=4; +define space ram type=ram_space size=$(REGSIZE) default; +define space iocsr type=ram_space size=$(REGSIZE); +define space register type=register_space size=4; define register offset=0x0 size=8 [ - pc scr0 scr1 scr2 scr3 + pc scr0 scr1 scr2 scr3 ]; define register offset=0x40 size=1 [ @@ -38,11 +39,11 @@ define register offset=0x100 size=4 [ r0_lo r0_hi ra_lo ra_hi tp_lo tp_hi sp_lo sp_hi a0_lo a0_hi a1_lo a1_hi a2_lo a2_hi a3_lo a3_hi a4_lo a4_hi a5_lo a5_hi a6_lo a6_hi a7_lo a7_hi - t0_lo t0_hi t1_lo t1_hi t2_lo t2_hi t3_lo t3_hi - t4_lo t4_hi t5_lo t5_hi t6_lo t6_hi t7_lo t7_hi - t8_lo t8_hi r21_lo r21_hi fp_lo fp_hi s0_lo s0_hi - s1_lo s1_hi s2_lo s2_hi s3_lo s3_hi s4_lo s4_hi - s5_lo s5_hi s6_lo s6_hi s7_lo s7_hi s8_lo s8_hi + t0_lo t0_hi t1_lo t1_hi t2_lo t2_hi t3_lo t3_hi + t4_lo t4_hi t5_lo t5_hi t6_lo t6_hi t7_lo t7_hi + t8_lo t8_hi r21_lo r21_hi fp_lo fp_hi s0_lo s0_hi + s1_lo s1_hi s2_lo s2_hi s3_lo s3_hi s4_lo s4_hi + s5_lo s5_hi s6_lo s6_hi s7_lo s7_hi s8_lo s8_hi ]; @endif @@ -133,45 +134,44 @@ define register offset=0x1000 size=32 [ @define CSR_OFFSET "0x2000" #used for the csr instructions csrxchg/cssrd/cssrw define register offset=$(CSR_OFFSET) size=$(REGSIZE) [ - crmd prmd euen misc ecfg estat era badv - badi csr9 csr10 csr11 eentry csr13 csr14 csr15 - tlbidx tlbehi tlbelo0 tlbelo1 csr20 csr21 csr22 csr23 - asid pgdl pgdh pgd pwcl pwch stlbps rvacfg - cpuid prcfg1 prcfg2 prcfg3 csr36 csr37 csr38 csr39 - csr40 csr41 csr42 csr43 csr44 csr45 csr46 csr47 - save0 save1 save2 save3 save4 save5 save6 save7 - save8 save9 save10 save11 save12 save13 save14 save15 - tid tcfg tval cntc ticlr csr69 csr70 csr71 - csr72 csr73 csr74 csr75 csr76 csr78 csr79 - csr80 csr81 csr82 csr83 csr84 csr85 csr86 csr87 - csr88 csr89 csr90 csr91 csr92 csr93 csr94 csr95 - llbctl csr97 csr98 csr99 csr100 csr101 csr102 csr103 - csr104 csr105 csr106 csr107 csr108 csr109 csr110 csr111 - csr112 csr113 csr114 csr115 csr116 csr117 csr118 csr119 - csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127 - impctl1 impctl2 csr130 csr131 csr132 csr133 csr134 csr135 - tlbrentry tlbrbadv tlbrera tlbrsave tlbrelo0 tlbrelo1 tlbrehi tlbrprmd - merrctl merrinfo1 merrinfo2 merrentry merrera merrsave csr150 csr151 - ctag csr153 csr154 csr155 csr156 csr157 csr158 csr159 - csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167 - csr168 csr169 csr170 csr171 csr172 csr173 csr174 csr175 - csr176 csr177 csr178 csr179 csr180 csr181 csr182 csr183 - csr184 csr185 csr186 csr187 csr188 csr189 csr190 csr191 - csr192 csr193 csr194 csr195 csr196 csr197 csr198 csr199 - csr200 csr201 csr202 csr203 csr204 csr205 csr206 csr207 - csr208 csr209 csr210 csr211 csr212 csr213 csr214 csr215 - csr216 csr217 csr218 csr219 csr220 csr221 csr222 csr223 - csr224 csr225 csr226 csr227 csr228 csr229 csr230 csr231 - csr232 csr233 csr234 csr235 csr236 csr237 csr238 csr239 - csr240 csr241 csr242 csr243 csr244 csr245 csr246 csr247 - csr248 csr249 csr250 csr251 csr252 csr253 csr254 csr255 - csr256 csr257 csr258 csr259 csr260 csr261 csr262 csr263 - + crmd prmd euen misc ecfg estat era badv + badi csr9 csr10 csr11 eentry csr13 csr14 csr15 + tlbidx tlbehi tlbelo0 tlbelo1 csr20 csr21 csr22 csr23 + asid pgdl pgdh pgd pwcl pwch stlbps rvacfg + cpuid prcfg1 prcfg2 prcfg3 csr36 csr37 csr38 csr39 + csr40 csr41 csr42 csr43 csr44 csr45 csr46 csr47 + save0 save1 save2 save3 save4 save5 save6 save7 + save8 save9 save10 save11 save12 save13 save14 save15 + tid tcfg tval cntc ticlr csr69 csr70 csr71 + csr72 csr73 csr74 csr75 csr76 csr78 csr79 + csr80 csr81 csr82 csr83 csr84 csr85 csr86 csr87 + csr88 csr89 csr90 csr91 csr92 csr93 csr94 csr95 + llbctl csr97 csr98 csr99 csr100 csr101 csr102 csr103 + csr104 csr105 csr106 csr107 csr108 csr109 csr110 csr111 + csr112 csr113 csr114 csr115 csr116 csr117 csr118 csr119 + csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127 + impctl1 impctl2 csr130 csr131 csr132 csr133 csr134 csr135 + tlbrentry tlbrbadv tlbrera tlbrsave tlbrelo0 tlbrelo1 tlbrehi tlbrprmd + merrctl merrinfo1 merrinfo2 merrentry merrera merrsave csr150 csr151 + ctag csr153 csr154 csr155 csr156 csr157 csr158 csr159 + csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167 + csr168 csr169 csr170 csr171 csr172 csr173 csr174 csr175 + csr176 csr177 csr178 csr179 csr180 csr181 csr182 csr183 + csr184 csr185 csr186 csr187 csr188 csr189 csr190 csr191 + csr192 csr193 csr194 csr195 csr196 csr197 csr198 csr199 + csr200 csr201 csr202 csr203 csr204 csr205 csr206 csr207 + csr208 csr209 csr210 csr211 csr212 csr213 csr214 csr215 + csr216 csr217 csr218 csr219 csr220 csr221 csr222 csr223 + csr224 csr225 csr226 csr227 csr228 csr229 csr230 csr231 + csr232 csr233 csr234 csr235 csr236 csr237 csr238 csr239 + csr240 csr241 csr242 csr243 csr244 csr245 csr246 csr247 + csr248 csr249 csr250 csr251 csr252 csr253 csr254 csr255 + csr256 csr257 csr258 csr259 csr260 csr261 csr262 csr263 ]; # Dummy registers for floating point comparison define register offset=0x5000 size=4 [ - FCMP1 FCMP2 + FCMP1 FCMP2 ]; define register offset=0x5008 size=1 [ @@ -179,7 +179,7 @@ define register offset=0x5008 size=1 [ ]; define register offset=0x5100 size=8 [ - DCMP1 DCMP2 + DCMP1 DCMP2 ]; define register offset=0x5110 size=1 [ @@ -187,9 +187,9 @@ define register offset=0x5110 size=1 [ ]; define register offset=0x50 size=4 contextreg; + define context contextreg -phase = (0,1) -; + phase = (0,1) ; define token instr(32) instword = ( 0,31) @@ -224,9 +224,9 @@ define token instr(32) op0_4 = ( 0, 4) op0_31 = ( 0,31) - ccf = (16,19) - ccf_s = (15,15) - + ccf = (16,19) + ccf_s = (15,15) + simm5_20 = ( 5,24) signed simm5_13 = ( 5,17) signed simm10_9 = (10,18) signed @@ -239,7 +239,7 @@ define token instr(32) simm10_10 = (10,19) signed simm0_5 = ( 0, 4) signed simm0_10 = ( 0, 9) signed - + rK = (10,14) rK32 = (10,14) @@ -249,16 +249,16 @@ define token instr(32) rD = ( 0, 4) rD32 = ( 0, 4) - xrK = (10,14) - xrJ = ( 5, 9) - xrD = ( 0, 4) - xrA = (15,19) - - vrK = (10,14) - vrJ = ( 5, 9) - vrD = ( 0, 4) - vrA = (15,19) - + xrK = (10,14) + xrJ = ( 5, 9) + xrD = ( 0, 4) + xrA = (15,19) + + vrK = (10,14) + vrJ = ( 5, 9) + vrD = ( 0, 4) + vrA = (15,19) + lbtrJ = ( 5, 6) lbtrD = ( 0, 1) @@ -272,9 +272,9 @@ define token instr(32) drD = ( 0, 4) drA = (15,19) - fccJ = ( 5, 7) - fccD = ( 0, 2) - fccA = (15,17) + fccJ = ( 5, 7) + fccD = ( 0, 2) + fccA = (15,17) imm5_5 = ( 5, 9) imm5_3 = ( 5, 7) @@ -389,6 +389,7 @@ attach variables [xrD xrJ xrK xrA] [ attach variables [ fccD fccJ fccA] [ fcc0 fcc1 fcc2 fcc3 fcc4 fcc5 fcc6 fcc7 ]; + # Register subconstructors RD: rD is rD { export rD; } @@ -421,13 +422,21 @@ RK32src: rK is rK & rK32 { export rK32; } RK32src: rK is rK & rK32=0 { export 0:4; } @if FREGSIZE == "8" -FRD: drD is drD { export drD; } -FRJ: drJ is drJ { export drJ; } -FRK: drK is drK { export drK; } + +FRD: drD is drD { export drD; } + +FRJ: drJ is drJ { export drJ; } + +FRK: drK is drK { export drK; } + @else -FRD: frD is frD { export frD; } -FRJ: frJ is frJ { export frJ; } -FRK: frK is frK { export frK; } + +FRD: frD is frD { export frD; } + +FRJ: frJ is frJ { export frJ; } + +FRK: frK is frK { export frK; } + @endif # Immediate operand sub-constructors @@ -443,17 +452,21 @@ ldstx_addr: RJsrc(RKsrc) is RJsrc & RKsrc { local vaddr:$(REGSIZE) = RJsrc + RK pcadd2: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 2);] { export *[const]:$(REGSIZE) reloffs; } pcadd12: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; } + pcala12: reloffs is simm5_20 [reloffs = (inst_start & ~0xfff) + (simm5_20 << 12);] { export *[const]:$(REGSIZE) reloffs; } + pcadd18: reloffs is simm5_20 [reloffs = inst_start + (simm5_20 << 18);] { export *[const]:$(REGSIZE) reloffs; } -Rel16: reloc is simm10_16 [ reloc = inst_start + (simm10_16 << 2); ] { export *:$(ADDRSIZE) reloc; } +Rel16: reloc is simm10_16 [ reloc = inst_start + (simm10_16 << 2); ] { export *:$(ADDRSIZE) reloc; } Rel21: reloc is imm10_16 & simm0_5 [ reloc = inst_start + (((simm0_5 << 16) + imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; } Rel26: reloc is imm10_16 & simm0_10 [ reloc = inst_start + (((simm0_10 << 16) | imm10_16) << 2); ] { export *:$(ADDRSIZE) reloc; } RelJ16: RJsrc, simm10_16 is RJsrc & simm10_16 { local tmp:$(ADDRSIZE) = RJsrc + (simm10_16 << 2); export tmp; } simm12i: immed is simm5_20 [immed = simm5_20 << 12; ] { export *[const]:$(REGSIZE) immed; } + simm32i: immed is simm5_20 [immed = simm5_20 << 32; ] { export *[const]:$(REGSIZE) immed; } + simm52i: immed is simm10_12 [immed = simm10_12 << 52; ] { export *[const]:$(REGSIZE) immed; } # general pcodeops diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc index 2158a64094..5324de1e3d 100644 --- a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc @@ -57,7 +57,7 @@ seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } #la-privileged-32.txt iocsrrd.b mask=0x06480000 #0x06480000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] :iocsrrd.b RD, RJsrc is op10_31=0x19200 & RD & RJsrc { - local val:1 = iocsrrd(RJsrc, 1:1); + local val:1 = *[iocsr]:1 RJsrc; RD = sext(val); } @@ -65,7 +65,7 @@ seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } #la-privileged-32.txt iocsrrd.h mask=0x06480400 #0x06480400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] :iocsrrd.h RD, RJsrc is op10_31=0x19201 & RD & RJsrc { - local val:2 = iocsrrd(RJsrc, 2:1); + local val:2 = *[iocsr]:2 RJsrc; RD = sext(val); } @@ -73,7 +73,7 @@ seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } #la-privileged-32.txt iocsrrd.w mask=0x06480800 #0x06480800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] :iocsrrd.w RD, RJsrc is op10_31=0x19202 & RD & RJsrc { - local val:4 = iocsrrd(RJsrc, 4:1); + local val:4 = *[iocsr]:4 RJsrc; RD = sext(val); } @@ -81,22 +81,25 @@ seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } #la-privileged-32.txt iocsrwr.b mask=0x06481000 #0x06481000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrwr.b RD, RJsrc is op10_31=0x19204 & RD & RJsrc { - iocsrwr(RD, RJsrc, 1:1); +:iocsrwr.b RDsrc, RJsrc is op10_31=0x19204 & RDsrc & RJsrc { + local val:1 = RDsrc:1; + *[iocsr]:1 RJsrc = val; } #la-privileged-32.txt iocsrwr.h mask=0x06481400 #0x06481400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrwr.h RD, RJsrc is op10_31=0x19205 & RD & RJsrc { - iocsrwr(RD, RJsrc, 2:1); +:iocsrwr.h RDsrc, RJsrc is op10_31=0x19205 & RDsrc & RJsrc { + local val:2= RDsrc:2; + *[iocsr]:2 RJsrc = val; } #la-privileged-32.txt iocsrwr.w mask=0x06481800 #0x06481800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrwr.w RD, RJsrc is op10_31=0x19206 & RD & RJsrc { - iocsrwr(RD, RJsrc, 4:1); +:iocsrwr.w RDsrc, RJsrc is op10_31=0x19206 & RDsrc & RJsrc { + local val:4= RDsrc:4; + *[iocsr]:4 RJsrc = val; } @@ -152,7 +155,7 @@ define pcodeop ertn; #la-privileged-32.txt eret mask=0x06483800 [@orig_name=ertn, @primary] #0x06483800 0xffffffff :ertn is instword=0x06483800 { - local ret = ertn(); + local ret:$(REGSIZE) = ertn(); return [ret]; } diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc index e76db485ac..3a8972ed7a 100644 --- a/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc @@ -1,14 +1,14 @@ #la-privileged-64.txt iocsrrd.d mask=0x06480c00 #0x06480c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] :iocsrrd.d RD, RJsrc is op10_31=0x19203 & RD & RJsrc { - RD = iocsrrd(RJsrc, 8:1); + RD = *[iocsr]:8 RJsrc; } #la-privileged-64.txt iocsrwr.d mask=0x06481c00 #0x06481c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrwr.d RD, RJsrc is op10_31=0x19207 & RD & RJsrc { - iocsrwr(RD, RJsrc, 64:1); +:iocsrwr.d RDsrc, RJsrc is op10_31=0x19207 & RDsrc & RJsrc { + *[iocsr]:8 RJsrc = RDsrc; } From 9409cd5d284aa1f31b4bca64c5bc32f7a48be948 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Wed, 6 Sep 2023 21:34:31 +0000 Subject: [PATCH 06/15] GP-3211: Even more loongarch code review fixes! --- .../data/languages/double_Instructions.sinc | 5 ++-- .../data/languages/float_Instructions.sinc | 7 ++--- .../Loongarch/data/languages/ilp32d.cspec | 27 +++++++++++++++++++ .../Loongarch/data/languages/ilp32f.cspec | 27 +++++++++++++++++++ .../Loongarch/data/languages/lp64d.cspec | 27 +++++++++++++++++++ .../Loongarch/data/languages/lp64f.cspec | 27 +++++++++++++++++++ 6 files changed, 115 insertions(+), 5 deletions(-) diff --git a/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc index 019c425c73..47f075056c 100644 --- a/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc @@ -79,8 +79,9 @@ #la-fp-d.txt fcopysign.d mask=0x01130000 #0x01130000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] :fcopysign.d drD, drJ, drK is op15_31=0x226 & drD & drJ & drK { - local kval = drK; - drD = drJ f* (kval/abs(kval)); + local kval = drK & 0x8000000000000000; + local jval = drJ & 0x7fffffffffffffff; + drD = kval | jval ; } diff --git a/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc index c187c65257..14e29b7b26 100644 --- a/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc @@ -250,8 +250,9 @@ define pcodeop uncertain_fcsr; #la-fp-s.txt fcopysign.s mask=0x01128000 #0x01128000 0xffff8000 f0:5, f5:5, f10:5 ['freg0_5_s0', 'freg5_5_s0', 'freg10_5_s0'] :fcopysign.s frD, frJ, frK is op15_31=0x225 & frD & frJ & frK { - local kval = frK; - frD = frJ f* (kval/abs(kval)); + local kval = frK & 0x80000000; + local jval = frJ & 0x7fffffff; + frD = kval | jval ; } @@ -390,7 +391,7 @@ define pcodeop uncertain_fcsr; #la-fp-s.txt fld.s mask=0x2b000000 #0x2b000000 0xffc00000 f0:5,r5:5,so10:12 ['freg0_5_s0', 'reg5_5_s0', 'soffs10_12_s0'] :fld.s frD, ldst_addr is op22_31=0xac & frD & ldst_addr { - frD = sext(*[ram]:4 ldst_addr); + frD = *[ram]:4 ldst_addr; } diff --git a/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec b/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec index 1689513d1d..8688e222f4 100644 --- a/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec @@ -104,6 +104,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec index a643556d93..5981c476a7 100644 --- a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec @@ -119,6 +119,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lp64d.cspec b/Ghidra/Processors/Loongarch/data/languages/lp64d.cspec index 169416602e..ce2492d2be 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lp64d.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/lp64d.cspec @@ -102,6 +102,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec b/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec index 60bc475dbd..2b195e855f 100644 --- a/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/lp64f.cspec @@ -120,6 +120,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + From c3820d33b45078fcbd792398729a00377e5258bd Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Thu, 7 Sep 2023 17:35:26 +0000 Subject: [PATCH 07/15] GP-3211: Code review fixes to rename files --- Ghidra/Processors/Loongarch/certification.manifest | 8 ++++---- ...32_Instructions.sinc => Loongarch32_instructions.sinc} | 0 ...64_Instructions.sinc => Loongarch64_instructions.sinc} | 0 .../Loongarch/data/languages/loongarch32_f32.slaspec | 6 +++--- .../Loongarch/data/languages/loongarch32_f64.slaspec | 6 +++--- .../Loongarch/data/languages/loongarch64_f32.slaspec | 8 ++++---- .../Loongarch/data/languages/loongarch64_f64.slaspec | 8 ++++---- .../{double_Instructions.sinc => loongarch_double.sinc} | 0 .../{float_Instructions.sinc => loongarch_float.sinc} | 0 9 files changed, 18 insertions(+), 18 deletions(-) rename Ghidra/Processors/Loongarch/data/languages/{Loongarch32_Instructions.sinc => Loongarch32_instructions.sinc} (100%) rename Ghidra/Processors/Loongarch/data/languages/{Loongarch64_Instructions.sinc => Loongarch64_instructions.sinc} (100%) rename Ghidra/Processors/Loongarch/data/languages/{double_Instructions.sinc => loongarch_double.sinc} (100%) rename Ghidra/Processors/Loongarch/data/languages/{float_Instructions.sinc => loongarch_float.sinc} (100%) diff --git a/Ghidra/Processors/Loongarch/certification.manifest b/Ghidra/Processors/Loongarch/certification.manifest index bd59f7714c..b6a022a6a9 100644 --- a/Ghidra/Processors/Loongarch/certification.manifest +++ b/Ghidra/Processors/Loongarch/certification.manifest @@ -1,9 +1,7 @@ ##VERSION: 2.0 Module.manifest||GHIDRA||||END| -data/languages/Loongarch32_Instructions.sinc||GHIDRA||||END| -data/languages/Loongarch64_Instructions.sinc||GHIDRA||||END| -data/languages/double_Instructions.sinc||GHIDRA||||END| -data/languages/float_Instructions.sinc||GHIDRA||||END| +data/languages/Loongarch32_instructions.sinc||GHIDRA||||END| +data/languages/Loongarch64_instructions.sinc||GHIDRA||||END| data/languages/ilp32d.cspec||GHIDRA||||END| data/languages/ilp32f.cspec||GHIDRA||||END| data/languages/lasx.sinc||GHIDRA||||END| @@ -16,6 +14,8 @@ data/languages/loongarch32_f64.slaspec||GHIDRA||||END| data/languages/loongarch64.pspec||GHIDRA||||END| data/languages/loongarch64_f32.slaspec||GHIDRA||||END| data/languages/loongarch64_f64.slaspec||GHIDRA||||END| +data/languages/loongarch_double.sinc||GHIDRA||||END| +data/languages/loongarch_float.sinc||GHIDRA||||END| data/languages/loongarch_main.sinc||GHIDRA||||END| data/languages/lp64d.cspec||GHIDRA||||END| data/languages/lp64f.cspec||GHIDRA||||END| diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc similarity index 100% rename from Ghidra/Processors/Loongarch/data/languages/Loongarch32_Instructions.sinc rename to Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc similarity index 100% rename from Ghidra/Processors/Loongarch/data/languages/Loongarch64_Instructions.sinc rename to Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec index 02232078e4..b8078c2f41 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec @@ -2,10 +2,10 @@ @define FREGSIZE 4 @define ADDRSIZE 4 @include "loongarch_main.sinc" -@include "Loongarch32_Instructions.sinc" +@include "Loongarch32_instructions.sinc" @include "privileged-32.sinc" -@include "float_Instructions.sinc" -@include "double_Instructions.sinc" +@include "loongarch_float.sinc" +@include "loongarch_double.sinc" @include "lasx.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec index ef017d2e39..997c8649e8 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec @@ -2,10 +2,10 @@ @define FREGSIZE 8 @define ADDRSIZE 4 @include "loongarch_main.sinc" -@include "Loongarch32_Instructions.sinc" +@include "Loongarch32_instructions.sinc" @include "privileged-32.sinc" -@include "float_Instructions.sinc" -@include "double_Instructions.sinc" +@include "loongarch_float.sinc" +@include "loongarch_double.sinc" #@include "lasx.sinc" #@include "lbt.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec index 5d5ea02720..769a3e3e49 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec @@ -4,12 +4,12 @@ @define FREGSIZE 4 @define ADDRSIZE 8 @include "loongarch_main.sinc" -@include "Loongarch32_Instructions.sinc" -@include "Loongarch64_Instructions.sinc" +@include "Loongarch32_instructions.sinc" +@include "Loongarch64_instructions.sinc" @include "privileged-32.sinc" @include "privileged-64.sinc" -@include "float_Instructions.sinc" -@include "double_Instructions.sinc" +@include "loongarch_float.sinc" +@include "loongarch_double.sinc" @include "lasx.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec index 627012062e..08a76d648f 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec @@ -4,12 +4,12 @@ @define FREGSIZE 8 @define ADDRSIZE 8 @include "loongarch_main.sinc" -@include "Loongarch32_Instructions.sinc" -@include "Loongarch64_Instructions.sinc" +@include "Loongarch32_instructions.sinc" +@include "Loongarch64_instructions.sinc" @include "privileged-32.sinc" @include "privileged-64.sinc" -@include "float_Instructions.sinc" -@include "double_Instructions.sinc" +@include "loongarch_float.sinc" +@include "loongarch_double.sinc" @include "lasx.sinc" @include "lbt.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_double.sinc similarity index 100% rename from Ghidra/Processors/Loongarch/data/languages/double_Instructions.sinc rename to Ghidra/Processors/Loongarch/data/languages/loongarch_double.sinc diff --git a/Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_float.sinc similarity index 100% rename from Ghidra/Processors/Loongarch/data/languages/float_Instructions.sinc rename to Ghidra/Processors/Loongarch/data/languages/loongarch_float.sinc From f32cee22689df65ba53995a913e10f7173bfeddb Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Thu, 7 Sep 2023 17:38:19 +0000 Subject: [PATCH 08/15] GP-3211: Moved privileged instructions --- .../Loongarch/certification.manifest | 2 - .../languages/Loongarch32_instructions.sinc | 182 ++++++++++++++++++ .../languages/Loongarch64_instructions.sinc | 17 ++ .../data/languages/privileged-32.sinc | 178 ----------------- .../data/languages/privileged-64.sinc | 14 -- 5 files changed, 199 insertions(+), 194 deletions(-) delete mode 100644 Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc delete mode 100644 Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc diff --git a/Ghidra/Processors/Loongarch/certification.manifest b/Ghidra/Processors/Loongarch/certification.manifest index b6a022a6a9..2051080272 100644 --- a/Ghidra/Processors/Loongarch/certification.manifest +++ b/Ghidra/Processors/Loongarch/certification.manifest @@ -21,6 +21,4 @@ data/languages/lp64d.cspec||GHIDRA||||END| data/languages/lp64f.cspec||GHIDRA||||END| data/languages/lsx.sinc||GHIDRA||||END| data/languages/lvz.sinc||GHIDRA||||END| -data/languages/privileged-32.sinc||GHIDRA||||END| -data/languages/privileged-64.sinc||GHIDRA||||END| data/manuals/loongarch.idx||GHIDRA||||END| diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc index 2966aff9c4..217c9fcf15 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc @@ -1140,4 +1140,186 @@ define pcodeop bstrins.w; } +######################### +# PRIVILEGED INSTRUCTIONS +######################### + +#la-privileged-32.txt csrxchg mask=0x04000000 [@primary] +#0x04000000 0xff000000 r0:5,r5:5,u10:14 ['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0'] +csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] { + export *[register]:$(REGSIZE) csr; +} + +:csrxchg RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr { + local csrval:$(REGSIZE) = csr; + local mask = RJsrc; + csr = RD & mask; + RD = csrval & mask; +} + +:cssrd RD, csr is op24_31=0x4 & RD & op5_9=0 & csr { + RD = csr; +} + +:cssrw RD, csr is op24_31=0x4 & RD & op5_9=1 & csr { + local csrval:$(REGSIZE) = csr; + csr = RD; + RD = csrval; +} + +define pcodeop cacop; +#la-privileged-32.txt cacop mask=0x06000000 [@orig_fmt=Ud5JSk12, @primary] +#0x06000000 0xffc00000 u0:5,r5:5,s10:12 ['imm0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] +cache_obj: op0_2 is op0_2 { local tmp:1 = op0_2; export *[const]:1 tmp; } +op_type: "initialization" is op3_4=0 { export 0:1; } +op_type: "consistency" is op3_4=1 { export 1:1; } +op_type: "coherency" is op3_4=2 { export 2:1; } +op_type: "Custom" is op3_4=3 { export 3:1; } + +:cacop op_type^"("^cache_obj^")", ldst_addr is op22_31=0x18 & cache_obj & op_type & ldst_addr { + cacop(op_type, cache_obj, ldst_addr); +} + + +define pcodeop lddir; +level: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } +#la-privileged-32.txt lddir mask=0x06400000 +#0x06400000 0xfffc0000 r0:5,r5:5,u10:8 ['reg0_5_s0', 'reg5_5_s0', 'imm10_8_s0'] +:lddir RD, RJsrc, level is op18_31=0x190 & RD & RJsrc & level { + RD = lddir(RJsrc, level); +} + + +define pcodeop ldpte; +seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } +#la-privileged-32.txt ldpte mask=0x06440000 +#0x06440000 0xfffc001f r5:5,u10:8 ['reg5_5_s0', 'imm10_8_s0'] +:ldpte RJsrc, seq is op18_31=0x191 & op0_4=0x0 & RJsrc & seq { + ldpte(RJsrc, seq); +} + + + +#la-privileged-32.txt iocsrrd.b mask=0x06480000 +#0x06480000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrrd.b RD, RJsrc is op10_31=0x19200 & RD & RJsrc { + local val:1 = *[iocsr]:1 RJsrc; + RD = sext(val); +} + + +#la-privileged-32.txt iocsrrd.h mask=0x06480400 +#0x06480400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrrd.h RD, RJsrc is op10_31=0x19201 & RD & RJsrc { + local val:2 = *[iocsr]:2 RJsrc; + RD = sext(val); +} + + +#la-privileged-32.txt iocsrrd.w mask=0x06480800 +#0x06480800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrrd.w RD, RJsrc is op10_31=0x19202 & RD & RJsrc { + local val:4 = *[iocsr]:4 RJsrc; + RD = sext(val); +} + + + +#la-privileged-32.txt iocsrwr.b mask=0x06481000 +#0x06481000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrwr.b RDsrc, RJsrc is op10_31=0x19204 & RDsrc & RJsrc { + local val:1 = RDsrc:1; + *[iocsr]:1 RJsrc = val; +} + + +#la-privileged-32.txt iocsrwr.h mask=0x06481400 +#0x06481400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrwr.h RDsrc, RJsrc is op10_31=0x19205 & RDsrc & RJsrc { + local val:2= RDsrc:2; + *[iocsr]:2 RJsrc = val; +} + + +#la-privileged-32.txt iocsrwr.w mask=0x06481800 +#0x06481800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrwr.w RDsrc, RJsrc is op10_31=0x19206 & RDsrc & RJsrc { + local val:4= RDsrc:4; + *[iocsr]:4 RJsrc = val; +} + + +define pcodeop tlbclr; +#la-privileged-32.txt tlbclr mask=0x06482000 +#0x06482000 0xffffffff +:tlbclr is instword=0x06482000 { + tlbclr(); +} + + +define pcodeop tlbflush; +#la-privileged-32.txt tlbflush mask=0x06482400 +#0x06482400 0xffffffff +:tlbflush is instword=0x06482400 { + tlbflush(); +} + + +define pcodeop tlbsrch; +#la-privileged-32.txt tlbsrch mask=0x06482800 [@primary] +#0x06482800 0xffffffff +:tlbsrch is instword=0x06482800 { + tlbsrch(); +} + + +define pcodeop tlbrd; +#la-privileged-32.txt tlbrd mask=0x06482c00 [@primary] +#0x06482c00 0xffffffff +:tlbrd is instword=0x06482c00 { + tlbrd(); +} + + +define pcodeop tlbwr; +#la-privileged-32.txt tlbwr mask=0x06483000 [@primary] +#0x06483000 0xffffffff +:tlbwr is instword=0x06483000 { + tlbwr(); +} + + +define pcodeop tlbfill; +#la-privileged-32.txt tlbfill mask=0x06483400 [@primary] +#0x06483400 0xffffffff +:tlbfill is instword=0x06483400 { + tlbfill(); +} + + +define pcodeop ertn; +#la-privileged-32.txt eret mask=0x06483800 [@orig_name=ertn, @primary] +#0x06483800 0xffffffff +:ertn is instword=0x06483800 { + local ret:$(REGSIZE) = ertn(); + return [ret]; +} + + +define pcodeop idle; +#la-privileged-32.txt idle mask=0x06488000 [@primary] +#0x06488000 0xffff8000 u0:15 ['imm0_15_s0'] +:idle imm0_15 is op15_31=0xc91 & imm0_15 { + idle(imm0_15:2); +} + + +define pcodeop invtlb; +#la-privileged-32.txt tlbinv mask=0x06498000 [@orig_name=invtlb, @orig_fmt=Ud5JK, @primary] +#0x06498000 0xffff8000 u0:5,r5:5,r10:5 ['imm0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] +:invtlb RJsrc, RKsrc, imm0_5 is op15_31=0xc93 & RJsrc & RKsrc & imm0_5 { + invtlb(RJsrc, RKsrc, imm0_5:1); +} + + diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc index b3f142e728..a7f4cb24eb 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc @@ -740,4 +740,21 @@ define pcodeop crcc.w.d.w; } +######################### +# PRIVILEGED INSTRUCTIONS +######################### + +#la-privileged-64.txt iocsrrd.d mask=0x06480c00 +#0x06480c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrrd.d RD, RJsrc is op10_31=0x19203 & RD & RJsrc { + RD = *[iocsr]:8 RJsrc; +} + + +#la-privileged-64.txt iocsrwr.d mask=0x06481c00 +#0x06481c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] +:iocsrwr.d RDsrc, RJsrc is op10_31=0x19207 & RDsrc & RJsrc { + *[iocsr]:8 RJsrc = RDsrc; +} + diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc deleted file mode 100644 index 5324de1e3d..0000000000 --- a/Ghidra/Processors/Loongarch/data/languages/privileged-32.sinc +++ /dev/null @@ -1,178 +0,0 @@ -#la-privileged-32.txt csrxchg mask=0x04000000 [@primary] -#0x04000000 0xff000000 r0:5,r5:5,u10:14 ['reg0_5_s0', 'reg5_5_s0', 'imm10_14_s0'] -csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] { - export *[register]:$(REGSIZE) csr; -} - -:csrxchg RD, RJsrc, csr is op24_31=0x4 & RD & RJsrc & csr { - local csrval:$(REGSIZE) = csr; - local mask = RJsrc; - csr = RD & mask; - RD = csrval & mask; -} - -:cssrd RD, csr is op24_31=0x4 & RD & op5_9=0 & csr { - RD = csr; -} - -:cssrw RD, csr is op24_31=0x4 & RD & op5_9=1 & csr { - local csrval:$(REGSIZE) = csr; - csr = RD; - RD = csrval; -} - -define pcodeop cacop; -#la-privileged-32.txt cacop mask=0x06000000 [@orig_fmt=Ud5JSk12, @primary] -#0x06000000 0xffc00000 u0:5,r5:5,s10:12 ['imm0_5_s0', 'reg5_5_s0', 'simm10_12_s0'] -cache_obj: op0_2 is op0_2 { local tmp:1 = op0_2; export *[const]:1 tmp; } -op_type: "initialization" is op3_4=0 { export 0:1; } -op_type: "consistency" is op3_4=1 { export 1:1; } -op_type: "coherency" is op3_4=2 { export 2:1; } -op_type: "Custom" is op3_4=3 { export 3:1; } - -:cacop op_type^"("^cache_obj^")", ldst_addr is op22_31=0x18 & cache_obj & op_type & ldst_addr { - cacop(op_type, cache_obj, ldst_addr); -} - - -define pcodeop lddir; -level: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } -#la-privileged-32.txt lddir mask=0x06400000 -#0x06400000 0xfffc0000 r0:5,r5:5,u10:8 ['reg0_5_s0', 'reg5_5_s0', 'imm10_8_s0'] -:lddir RD, RJsrc, level is op18_31=0x190 & RD & RJsrc & level { - RD = lddir(RJsrc, level); -} - - -define pcodeop ldpte; -seq: imm10_8 is imm10_8 { export *[const]:1 imm10_8; } -#la-privileged-32.txt ldpte mask=0x06440000 -#0x06440000 0xfffc001f r5:5,u10:8 ['reg5_5_s0', 'imm10_8_s0'] -:ldpte RJsrc, seq is op18_31=0x191 & op0_4=0x0 & RJsrc & seq { - ldpte(RJsrc, seq); -} - - - -#la-privileged-32.txt iocsrrd.b mask=0x06480000 -#0x06480000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrrd.b RD, RJsrc is op10_31=0x19200 & RD & RJsrc { - local val:1 = *[iocsr]:1 RJsrc; - RD = sext(val); -} - - -#la-privileged-32.txt iocsrrd.h mask=0x06480400 -#0x06480400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrrd.h RD, RJsrc is op10_31=0x19201 & RD & RJsrc { - local val:2 = *[iocsr]:2 RJsrc; - RD = sext(val); -} - - -#la-privileged-32.txt iocsrrd.w mask=0x06480800 -#0x06480800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrrd.w RD, RJsrc is op10_31=0x19202 & RD & RJsrc { - local val:4 = *[iocsr]:4 RJsrc; - RD = sext(val); -} - - - -#la-privileged-32.txt iocsrwr.b mask=0x06481000 -#0x06481000 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrwr.b RDsrc, RJsrc is op10_31=0x19204 & RDsrc & RJsrc { - local val:1 = RDsrc:1; - *[iocsr]:1 RJsrc = val; -} - - -#la-privileged-32.txt iocsrwr.h mask=0x06481400 -#0x06481400 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrwr.h RDsrc, RJsrc is op10_31=0x19205 & RDsrc & RJsrc { - local val:2= RDsrc:2; - *[iocsr]:2 RJsrc = val; -} - - -#la-privileged-32.txt iocsrwr.w mask=0x06481800 -#0x06481800 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrwr.w RDsrc, RJsrc is op10_31=0x19206 & RDsrc & RJsrc { - local val:4= RDsrc:4; - *[iocsr]:4 RJsrc = val; -} - - -define pcodeop tlbclr; -#la-privileged-32.txt tlbclr mask=0x06482000 -#0x06482000 0xffffffff -:tlbclr is instword=0x06482000 { - tlbclr(); -} - - -define pcodeop tlbflush; -#la-privileged-32.txt tlbflush mask=0x06482400 -#0x06482400 0xffffffff -:tlbflush is instword=0x06482400 { - tlbflush(); -} - - -define pcodeop tlbsrch; -#la-privileged-32.txt tlbsrch mask=0x06482800 [@primary] -#0x06482800 0xffffffff -:tlbsrch is instword=0x06482800 { - tlbsrch(); -} - - -define pcodeop tlbrd; -#la-privileged-32.txt tlbrd mask=0x06482c00 [@primary] -#0x06482c00 0xffffffff -:tlbrd is instword=0x06482c00 { - tlbrd(); -} - - -define pcodeop tlbwr; -#la-privileged-32.txt tlbwr mask=0x06483000 [@primary] -#0x06483000 0xffffffff -:tlbwr is instword=0x06483000 { - tlbwr(); -} - - -define pcodeop tlbfill; -#la-privileged-32.txt tlbfill mask=0x06483400 [@primary] -#0x06483400 0xffffffff -:tlbfill is instword=0x06483400 { - tlbfill(); -} - - -define pcodeop ertn; -#la-privileged-32.txt eret mask=0x06483800 [@orig_name=ertn, @primary] -#0x06483800 0xffffffff -:ertn is instword=0x06483800 { - local ret:$(REGSIZE) = ertn(); - return [ret]; -} - - -define pcodeop idle; -#la-privileged-32.txt idle mask=0x06488000 [@primary] -#0x06488000 0xffff8000 u0:15 ['imm0_15_s0'] -:idle imm0_15 is op15_31=0xc91 & imm0_15 { - idle(imm0_15:2); -} - - -define pcodeop invtlb; -#la-privileged-32.txt tlbinv mask=0x06498000 [@orig_name=invtlb, @orig_fmt=Ud5JK, @primary] -#0x06498000 0xffff8000 u0:5,r5:5,r10:5 ['imm0_5_s0', 'reg5_5_s0', 'reg10_5_s0'] -:invtlb RJsrc, RKsrc, imm0_5 is op15_31=0xc93 & RJsrc & RKsrc & imm0_5 { - invtlb(RJsrc, RKsrc, imm0_5:1); -} - - diff --git a/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc b/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc deleted file mode 100644 index 3a8972ed7a..0000000000 --- a/Ghidra/Processors/Loongarch/data/languages/privileged-64.sinc +++ /dev/null @@ -1,14 +0,0 @@ -#la-privileged-64.txt iocsrrd.d mask=0x06480c00 -#0x06480c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrrd.d RD, RJsrc is op10_31=0x19203 & RD & RJsrc { - RD = *[iocsr]:8 RJsrc; -} - - -#la-privileged-64.txt iocsrwr.d mask=0x06481c00 -#0x06481c00 0xfffffc00 r0:5,r5:5 ['reg0_5_s0', 'reg5_5_s0'] -:iocsrwr.d RDsrc, RJsrc is op10_31=0x19207 & RDsrc & RJsrc { - *[iocsr]:8 RJsrc = RDsrc; -} - - From 3ad1c1ea29ea1ae0bc453f8322bc53d1479fb2a0 Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Thu, 7 Sep 2023 23:18:11 +0000 Subject: [PATCH 09/15] GP-3211 Added function start patterns, fixed issues with compile, fixed issues with .cspec load in 32-bit --- .../Loongarch/certification.manifest | 2 + .../Loongarch/data/languages/ilp32d.cspec | 18 +++---- .../Loongarch/data/languages/ilp32f.cspec | 49 +++++++------------ .../data/languages/loongarch32_f32.slaspec | 1 - .../data/languages/loongarch32_f64.slaspec | 1 - .../data/languages/loongarch64_f32.slaspec | 2 - .../data/languages/loongarch64_f64.slaspec | 2 - .../data/patterns/loongarch_patterns.xml | 38 ++++++++++++++ .../data/patterns/patternconstraints.xml | 5 ++ 9 files changed, 71 insertions(+), 47 deletions(-) create mode 100644 Ghidra/Processors/Loongarch/data/patterns/loongarch_patterns.xml create mode 100644 Ghidra/Processors/Loongarch/data/patterns/patternconstraints.xml diff --git a/Ghidra/Processors/Loongarch/certification.manifest b/Ghidra/Processors/Loongarch/certification.manifest index 2051080272..d9620aa789 100644 --- a/Ghidra/Processors/Loongarch/certification.manifest +++ b/Ghidra/Processors/Loongarch/certification.manifest @@ -22,3 +22,5 @@ data/languages/lp64f.cspec||GHIDRA||||END| data/languages/lsx.sinc||GHIDRA||||END| data/languages/lvz.sinc||GHIDRA||||END| data/manuals/loongarch.idx||GHIDRA||||END| +data/patterns/loongarch_patterns.xml||GHIDRA||||END| +data/patterns/patternconstraints.xml||GHIDRA||||END| diff --git a/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec b/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec index 8688e222f4..28d6ba85b5 100644 --- a/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/ilp32d.cspec @@ -77,7 +77,7 @@ - + @@ -143,14 +143,14 @@ - - - - - - - - + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec index 5981c476a7..f43c6a5fd0 100644 --- a/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec +++ b/Ghidra/Processors/Loongarch/data/languages/ilp32f.cspec @@ -29,42 +29,30 @@ - + - + - + - + - + - + - + - + - - - - - - - - - - - - @@ -106,10 +94,7 @@ - - - - + @@ -158,14 +143,14 @@ - - - - - - - - + + + + + + + + diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec index b8078c2f41..70ddd60e39 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec @@ -3,7 +3,6 @@ @define ADDRSIZE 4 @include "loongarch_main.sinc" @include "Loongarch32_instructions.sinc" -@include "privileged-32.sinc" @include "loongarch_float.sinc" @include "loongarch_double.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec index 997c8649e8..7ece89d419 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec @@ -3,7 +3,6 @@ @define ADDRSIZE 4 @include "loongarch_main.sinc" @include "Loongarch32_instructions.sinc" -@include "privileged-32.sinc" @include "loongarch_float.sinc" @include "loongarch_double.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec index 769a3e3e49..5b273e9aa2 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec @@ -6,8 +6,6 @@ @include "loongarch_main.sinc" @include "Loongarch32_instructions.sinc" @include "Loongarch64_instructions.sinc" -@include "privileged-32.sinc" -@include "privileged-64.sinc" @include "loongarch_float.sinc" @include "loongarch_double.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec index 08a76d648f..37096ef2cc 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec @@ -6,8 +6,6 @@ @include "loongarch_main.sinc" @include "Loongarch32_instructions.sinc" @include "Loongarch64_instructions.sinc" -@include "privileged-32.sinc" -@include "privileged-64.sinc" @include "loongarch_float.sinc" @include "loongarch_double.sinc" diff --git a/Ghidra/Processors/Loongarch/data/patterns/loongarch_patterns.xml b/Ghidra/Processors/Loongarch/data/patterns/loongarch_patterns.xml new file mode 100644 index 0000000000..b96f9c6a32 --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/patterns/loongarch_patterns.xml @@ -0,0 +1,38 @@ + + + + + + 0x20 0x00 0x00 0x4c + + + 0x63 ......00 111..... 0x02 01100001 .....000 11...... 0x29 + + + + + + + + + 11111111 ......11 ........ 01010011 + 0x80 0x01 0x00 0x4c + + + 0x63 ......00 111..... 0x02 + + + + + + + + 0x20 0x00 0x00 0x4c + + + 0x63 ......00 111..... 0x02 + + + + + \ No newline at end of file diff --git a/Ghidra/Processors/Loongarch/data/patterns/patternconstraints.xml b/Ghidra/Processors/Loongarch/data/patterns/patternconstraints.xml new file mode 100644 index 0000000000..2cb00bb42c --- /dev/null +++ b/Ghidra/Processors/Loongarch/data/patterns/patternconstraints.xml @@ -0,0 +1,5 @@ + + + loongarch_patterns.xml + + From 1ba4d49e5cf0d01819071c4309252a6876f750f8 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Tue, 12 Sep 2023 15:05:32 +0000 Subject: [PATCH 10/15] GP-3211: Fixed issue with gdb external tool naming in loongarch --- .../data/languages/Loongarch64_instructions.sinc | 16 ++++++++-------- .../Loongarch/data/languages/loongarch.ldefs | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc index a7f4cb24eb..cea0d59596 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc @@ -338,7 +338,7 @@ local val1:8 = *[ram]:8 RJsrc; local val2:8 = RKsrc; local test = (val1 s>= val2); - RD = sext(val1); + RD = val1; *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -349,7 +349,7 @@ local val1:8 = *[ram]:8 RJsrc; local val2:8 = RKsrc; local test = (val1 s<= val2); - RD = sext(val1); + RD = val1; *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -371,7 +371,7 @@ local val1:8 = *[ram]:8 RJsrc; local val2:8 = RKsrc; local test = (val1 >= val2); - RD = sext(val1); + RD = val1; *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -393,7 +393,7 @@ local val1:8 = *[ram]:8 RJsrc; local val2:8 = RKsrc; local test = (val1 <= val2); - RD = sext(val1); + RD = val1; *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -455,7 +455,7 @@ local val1:8 = *[ram]:8 RJsrc; local val2:8 = RKsrc; local test = (val1 s>= val2); - RD = sext(val1); + RD = val1; *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -467,7 +467,7 @@ local val1:8 = *[ram]:8 RJsrc; local val2:8 = RKsrc; local test = (val1 s<= val2); - RD = sext(val1); + RD = val1; *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -491,7 +491,7 @@ local val1:8 = *[ram]:8 RJsrc; local val2:8 = RKsrc; local test = (val1 >= val2); - RD = sext(val1); + RD = val1; *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } @@ -515,7 +515,7 @@ local val1:8 = *[ram]:8 RJsrc; local val2:8 = RKsrc; local test = (val1 <= val2); - RD = sext(val1); + RD = val1; *[ram]:8 RJsrc = (zext(test) * val1) + (zext(!test) * val2); } diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs b/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs index 07cca957f8..2661e7c86c 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch.ldefs @@ -12,7 +12,7 @@ id="Loongarch:LE:32:ilp32f"> Loongson 3 32-bit with 32-bit FP - + Loongson 3 32-bit with 64-bit FP - + @@ -41,7 +41,7 @@ id="Loongarch:LE:64:lp64d"> Loongson 3 64-bit with 64-bit FP - + Loongson 3 64-bit with 64-bit FP - + \ No newline at end of file From 141484c3a2c3235014cb7c362320e00c48becc1a Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Tue, 12 Sep 2023 19:56:29 +0000 Subject: [PATCH 11/15] GP-3211 break should not continue to disassemble by default. added compued goto to break instruction --- .../Loongarch/data/languages/Loongarch32_instructions.sinc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc index 217c9fcf15..fa25e1ceab 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc @@ -58,7 +58,8 @@ #0x002a0000 0xffff8000 u0:15 ['imm0_15_s0'] :break imm0_15 is op15_31=0x54 & imm0_15 { local code:2 = imm0_15; - break(code); + local addr:$(REGSIZE) = break(code); + goto [addr]; } From 366e614bd1e3df50f4f8d428659df2317cf54721 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Wed, 13 Sep 2023 21:36:56 +0000 Subject: [PATCH 12/15] GP-3211: Fixed spelling error in ElfConstants --- .../main/java/ghidra/app/util/bin/format/elf/ElfConstants.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/elf/ElfConstants.java b/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/elf/ElfConstants.java index 704b6e5e04..15a90c6748 100644 --- a/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/elf/ElfConstants.java +++ b/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/elf/ElfConstants.java @@ -393,7 +393,7 @@ public interface ElfConstants { /** The Texas Instruments TMS320C55x DSP family */ public static final short EM_TI_C5500 = 142; // 143 reserved - /** exas Instruments Programmable Realtime Unit */ + /** Texas Instruments Programmable Realtime Unit */ public static final short EM_TI_PRU = 144; // 145 - 159 reserved /** STMicroelectronics 64bit VLIW Data Signal Processor */ From e509a08bebdef14c6929a3586857e3ed291c5b79 Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Wed, 20 Sep 2023 18:44:13 +0000 Subject: [PATCH 13/15] GP-3211 lower case names, changed PC size to match address space --- Ghidra/Processors/Loongarch/certification.manifest | 4 ++-- .../Loongarch/data/languages/loongarch32_f32.slaspec | 2 +- .../Loongarch/data/languages/loongarch32_f64.slaspec | 2 +- ...arch32_instructions.sinc => loongarch32_instructions.sinc} | 4 ++-- .../Loongarch/data/languages/loongarch64_f32.slaspec | 4 ++-- .../Loongarch/data/languages/loongarch64_f64.slaspec | 4 ++-- ...arch64_instructions.sinc => loongarch64_instructions.sinc} | 0 .../Processors/Loongarch/data/languages/loongarch_main.sinc | 2 +- 8 files changed, 11 insertions(+), 11 deletions(-) rename Ghidra/Processors/Loongarch/data/languages/{Loongarch32_instructions.sinc => loongarch32_instructions.sinc} (99%) rename Ghidra/Processors/Loongarch/data/languages/{Loongarch64_instructions.sinc => loongarch64_instructions.sinc} (100%) diff --git a/Ghidra/Processors/Loongarch/certification.manifest b/Ghidra/Processors/Loongarch/certification.manifest index d9620aa789..04ad2afbc6 100644 --- a/Ghidra/Processors/Loongarch/certification.manifest +++ b/Ghidra/Processors/Loongarch/certification.manifest @@ -1,7 +1,5 @@ ##VERSION: 2.0 Module.manifest||GHIDRA||||END| -data/languages/Loongarch32_instructions.sinc||GHIDRA||||END| -data/languages/Loongarch64_instructions.sinc||GHIDRA||||END| data/languages/ilp32d.cspec||GHIDRA||||END| data/languages/ilp32f.cspec||GHIDRA||||END| data/languages/lasx.sinc||GHIDRA||||END| @@ -11,9 +9,11 @@ data/languages/loongarch.opinion||GHIDRA||||END| data/languages/loongarch32.pspec||GHIDRA||||END| data/languages/loongarch32_f32.slaspec||GHIDRA||||END| data/languages/loongarch32_f64.slaspec||GHIDRA||||END| +data/languages/loongarch32_instructions.sinc||GHIDRA||||END| data/languages/loongarch64.pspec||GHIDRA||||END| data/languages/loongarch64_f32.slaspec||GHIDRA||||END| data/languages/loongarch64_f64.slaspec||GHIDRA||||END| +data/languages/loongarch64_instructions.sinc||GHIDRA||||END| data/languages/loongarch_double.sinc||GHIDRA||||END| data/languages/loongarch_float.sinc||GHIDRA||||END| data/languages/loongarch_main.sinc||GHIDRA||||END| diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec index 70ddd60e39..cba316cf42 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f32.slaspec @@ -2,7 +2,7 @@ @define FREGSIZE 4 @define ADDRSIZE 4 @include "loongarch_main.sinc" -@include "Loongarch32_instructions.sinc" +@include "loongarch32_instructions.sinc" @include "loongarch_float.sinc" @include "loongarch_double.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec index 7ece89d419..35c8a2fea7 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_f64.slaspec @@ -2,7 +2,7 @@ @define FREGSIZE 8 @define ADDRSIZE 4 @include "loongarch_main.sinc" -@include "Loongarch32_instructions.sinc" +@include "loongarch32_instructions.sinc" @include "loongarch_float.sinc" @include "loongarch_double.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc similarity index 99% rename from Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc rename to Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc index fa25e1ceab..a3e3634f31 100644 --- a/Ghidra/Processors/Loongarch/data/languages/Loongarch32_instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc @@ -667,8 +667,8 @@ # alias of jirl zero, rj, 0 :jr RJsrc is op26_31=0x13 & rD=0x0 & RJsrc & simm10_16=0 { - local retAddr = RJsrc; - goto [retAddr]; + pc = RJsrc; + goto [pc]; } diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec index 5b273e9aa2..35dab48af8 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f32.slaspec @@ -4,8 +4,8 @@ @define FREGSIZE 4 @define ADDRSIZE 8 @include "loongarch_main.sinc" -@include "Loongarch32_instructions.sinc" -@include "Loongarch64_instructions.sinc" +@include "loongarch32_instructions.sinc" +@include "loongarch64_instructions.sinc" @include "loongarch_float.sinc" @include "loongarch_double.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec index 37096ef2cc..9c6a5c3cce 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch64_f64.slaspec @@ -4,8 +4,8 @@ @define FREGSIZE 8 @define ADDRSIZE 8 @include "loongarch_main.sinc" -@include "Loongarch32_instructions.sinc" -@include "Loongarch64_instructions.sinc" +@include "loongarch32_instructions.sinc" +@include "loongarch64_instructions.sinc" @include "loongarch_float.sinc" @include "loongarch_double.sinc" diff --git a/Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch64_instructions.sinc similarity index 100% rename from Ghidra/Processors/Loongarch/data/languages/Loongarch64_instructions.sinc rename to Ghidra/Processors/Loongarch/data/languages/loongarch64_instructions.sinc diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc index 66904fa451..f44179a22e 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch_main.sinc @@ -7,7 +7,7 @@ define space ram type=ram_space size=$(REGSIZE) default; define space iocsr type=ram_space size=$(REGSIZE); define space register type=register_space size=4; -define register offset=0x0 size=8 [ +define register offset=0x0 size=$(REGSIZE) [ pc scr0 scr1 scr2 scr3 ]; From 4795e5c5a4648485fae145e9e03854e6dfcd77bf Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Thu, 21 Sep 2023 00:15:42 +0000 Subject: [PATCH 14/15] GP-3211 added initial analyzer --- .../core/analysis/LoongsonAnalyzer.java | 144 ++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Ghidra/Processors/Loongarch/src/main/java/ghidra/app/plugin/core/analysis/LoongsonAnalyzer.java diff --git a/Ghidra/Processors/Loongarch/src/main/java/ghidra/app/plugin/core/analysis/LoongsonAnalyzer.java b/Ghidra/Processors/Loongarch/src/main/java/ghidra/app/plugin/core/analysis/LoongsonAnalyzer.java new file mode 100644 index 0000000000..b5cf375fd7 --- /dev/null +++ b/Ghidra/Processors/Loongarch/src/main/java/ghidra/app/plugin/core/analysis/LoongsonAnalyzer.java @@ -0,0 +1,144 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.plugin.core.analysis; + +import ghidra.framework.options.Options; +import ghidra.program.model.address.*; +import ghidra.program.model.lang.Processor; +import ghidra.program.model.lang.Register; +import ghidra.program.model.listing.*; +import ghidra.program.model.pcode.Varnode; +import ghidra.program.model.symbol.*; +import ghidra.program.util.SymbolicPropogator; +import ghidra.program.util.VarnodeContext; +import ghidra.util.exception.CancelledException; +import ghidra.util.task.TaskMonitor; + +public class LoongsonAnalyzer extends ConstantPropagationAnalyzer { + + private Register linkRegister; + + private final static String PROCESSOR_NAME = "Loongarch"; + + public LoongsonAnalyzer() { + super(PROCESSOR_NAME); + } + + @Override + public boolean canAnalyze(Program program) { + boolean canAnalyze = program.getLanguage() + .getProcessor() + .equals(Processor.findOrPossiblyCreateProcessor(PROCESSOR_NAME)); + + if (!canAnalyze) { + return false; + } + + linkRegister = program.getProgramContext().getRegister("ra"); + + return true; + } + + @Override + public AddressSet flowConstants(final Program program, final Address flowStart, + AddressSetView flowSet, final SymbolicPropogator symEval, final TaskMonitor monitor) + throws CancelledException { + + // follow all flows building up context + // use context to fill out addresses on certain instructions + ConstantPropagationContextEvaluator eval = + new ConstantPropagationContextEvaluator(monitor, trustWriteMemOption) { + + /** + * Check if there are any data references to this location. + * @param program + * @param addr + * @return true if there are any data references to addr + */ + private boolean hasDataReferenceTo(Program program, Address addr) { + ReferenceManager refMgr = program.getReferenceManager(); + if (!refMgr.hasReferencesTo(addr)) { + return false; + } + ReferenceIterator referencesTo = refMgr.getReferencesTo(addr); + while (referencesTo.hasNext()) { + Reference reference = referencesTo.next(); + if (reference.getReferenceType().isData()) { + return true; + } + } + return false; + } + + private boolean isLinkRegister(VarnodeContext context, Varnode pcVal) { + return (pcVal.isRegister() && + pcVal.getAddress().equals(linkRegister.getAddress())) || + (context.isSymbol(pcVal) && pcVal.getAddress() + .getAddressSpace() + .getName() + .equals(linkRegister.getName()) && + pcVal.getOffset() == 0); + } + + @Override + public boolean evaluateDestination(VarnodeContext context, Instruction instruction) { + return super.evaluateDestination(context, instruction); + } + + @Override + public boolean evaluateReturn(Varnode retVN, VarnodeContext context, + Instruction instruction) { + // check if a return is actually returning, or is branching with a constant PC + + // if flow already overridden, don't override again + if (instruction.getFlowOverride() != FlowOverride.NONE) { + return false; + } + + if (retVN != null && context.isConstant(retVN)) { + long offset = retVN.getOffset(); + if (offset > 3 && offset != -1) { + FlowOverride flowOverride = FlowOverride.CALL_RETURN; + // need to override the return flow to a branch + instruction.setFlowOverride(flowOverride); + + // need to analyze this flow again with the new return tag + AutoAnalysisManager aMgr= AutoAnalysisManager.getAnalysisManager(program); + aMgr.codeDefined(flowStart); + } + } + + return false; + } + }; + + eval.setTrustWritableMemory(trustWriteMemOption) + .setMinpeculativeOffset(minSpeculativeRefAddress) + .setMaxSpeculativeOffset(maxSpeculativeRefAddress) + .setMinStoreLoadOffset(minStoreLoadRefAddress) + .setCreateComplexDataFromPointers(createComplexDataFromPointers); + + AddressSet resultSet = symEval.flowConstants(flowStart, flowSet, eval, true, monitor); + + return resultSet; + } + + @Override + public void optionsChanged(Options options, Program program) { + super.optionsChanged(options, program); + } + +} From ef76cd31c03d4a501b02dfd27668fe84d5c1f7cb Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Thu, 21 Sep 2023 01:29:43 +0000 Subject: [PATCH 15/15] GP-3211 fixed cssrd->csrrd cssrw->csrrw --- .../Loongarch/data/languages/loongarch32_instructions.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc b/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc index a3e3634f31..9e7479d3f3 100644 --- a/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc +++ b/Ghidra/Processors/Loongarch/data/languages/loongarch32_instructions.sinc @@ -1158,11 +1158,11 @@ csr: csr is imm10_14 [csr = $(CSR_OFFSET) + imm10_14 * $(REGSIZE);] { RD = csrval & mask; } -:cssrd RD, csr is op24_31=0x4 & RD & op5_9=0 & csr { +:csrrd RD, csr is op24_31=0x4 & RD & op5_9=0 & csr { RD = csr; } -:cssrw RD, csr is op24_31=0x4 & RD & op5_9=1 & csr { +:csrrw RD, csr is op24_31=0x4 & RD & op5_9=1 & csr { local csrval:$(REGSIZE) = csr; csr = RD; RD = csrval;