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GP-2718: Fixed vmov disassembly regression

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ghidorahrex 2022-10-31 13:44:14 +00:00
parent 5a3209bca5
commit 15223fd4f5
2 changed files with 23 additions and 5 deletions
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8
Ghidra/Framework/SoftwareModeling/src/test/java/ghidra/app/plugin/assembler/sleigh/ARMAssemblyTest.java
View file

@ -111,8 +111,14 @@ public class ARMAssemblyTest extends AbstractAssemblyTest {
} }
@Test @Test
public void testAssemble_T_vmov_i32_d0_simdExpand_0x0_0x0_0xb1() { public void testAssemble_T_vmov_simd_immed() {
assertOneCompatRestExact("vmov.i32 d0,simdExpand(0x0,0x0,0xb1)", "83:ff:11:00", THUMB, assertOneCompatRestExact("vmov.i32 d0,simdExpand(0x0,0x0,0xb1)", "83:ff:11:00", THUMB,
0x00010100, "vmov.i32 d0,simdExpand(0x0,0x0,0xb1)"); 0x00010100, "vmov.i32 d0,simdExpand(0x0,0x0,0xb1)");
assertOneCompatRestExact("vmov.i16 d0,simdExpand(0x0,0xa,0xb1)", "83:ff:11:0a", THUMB,
0x00010100, "vmov.i16 d0,simdExpand(0x0,0xa,0xb1)");
assertOneCompatRestExact("vmov.i32 d0,simdExpand(0x0,0xd,0xb1)", "83:ff:11:0d", THUMB,
0x00010100, "vmov.i32 d0,simdExpand(0x0,0xd,0xb1)");
assertOneCompatRestExact("vmov.i64 d0,simdExpand(0x1,0xe,0xb1)", "83:ff:31:0e", THUMB,
0x00010100, "vmov.i64 d0,simdExpand(0x1,0xe,0xb1)");
} }
} }

20
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
View file

@ -3983,14 +3983,16 @@ vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5
Qd = VectorMultiplySubtract(Dn,vmlDm,esize2021,udt); Qd = VectorMultiplySubtract(Dn,vmlDm,esize2021,udt);
} }
:vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=0 & c0405=1 ) | # Addresses all versions of F6.1.134 except A2/T2 with Q=0
( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=0 & thv_c0405=1 )) & Dd & simdExpImmDT & simdExpImm_8 :vmov.^simdExpImmDT Dd,simdExpImm_8 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=0 & c0404=1 ) |
( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=0 & thv_c0404=1 )) & Dd & simdExpImmDT & simdExpImm_8
{ {
Dd = simdExpImm_8; Dd = simdExpImm_8;
} }
:vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=1 & c0405=1 ) | # Addresses all versions of F6.1.134 except At/T2 with Q=1
( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=1 & thv_c0405=1 )) & Qd & simdExpImmDT & simdExpImm_16 :vmov.^simdExpImmDT Qd,simdExpImm_16 is (( $(AMODE) & ARMcond=0 & cond=15 & c2527=1 & c2323=1 & c1921=0 & c0707=0 & Q6=1 & c0404=1 ) |
( $(TMODE_EorF) & thv_c2327=0x1f & thv_c1921=0 & thv_c0707=0 & thv_Q6=1 & thv_c0404=1 )) & Qd & simdExpImmDT & simdExpImm_16
{ {
Qd = simdExpImm_16; Qd = simdExpImm_16;
} }
@ -3999,6 +4001,15 @@ vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5
@if defined(VFPv3) @if defined(VFPv3)
# F6.1.134 vmov A2/T2
:vmov^COND^".f16" Sd,vfpExpImm_4 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0x90 ) |
( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0x90 ) ) & COND & Sd & vfpExpImm_4
{
build COND;
Sd = vfpExpImm_4;
}
:vmov^COND^".f32" Sd,vfpExpImm_4 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xa0 ) | :vmov^COND^".f32" Sd,vfpExpImm_4 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xa0 ) |
( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xa0 ) ) & COND & Sd & vfpExpImm_4 ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xa0 ) ) & COND & Sd & vfpExpImm_4
{ {
@ -4006,6 +4017,7 @@ vmlDm: thv_Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & thv_Dm_4 & thv_M5
Sd = vfpExpImm_4; Sd = vfpExpImm_4;
} }
# F6.1.134 vmov A2/T2
:vmov^COND^".f64" Dd,vfpExpImm_8 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xb0 ) | :vmov^COND^".f64" Dd,vfpExpImm_8 is ( ( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=3 & c0411=0xb0 ) |
( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xb0 ) ) & COND & Dd & vfpExpImm_8 ( $(TMODE_E) & thv_c2327=0x1d & thv_c2021=3 & thv_c0411=0xb0 ) ) & COND & Dd & vfpExpImm_8
{ {