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https://github.com/NationalSecurityAgency/ghidra.git
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Update ASL/ASR/LSL/LSR/ROL/ROR/ROXL/ROXR behavior.
This commit is contained in:
Alessandro Gatti
parent
9c04807c8c
commit
1c6b0140bc
1 changed files with 194 additions and 44 deletions
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@ -700,6 +700,100 @@ macro extendedResultFlags(result) {
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ZF = (result == 0) && (ZF == 1);
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ZF = (result == 0) && (ZF == 1);
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}
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}
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macro arithmeticShiftLeft(count, register, width) {
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local modcount = count % 64;
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CF = 0;
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resflags(register);
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if (count == 0) goto inst_next;
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local msbBefore:4 = zext(register) >> (width - 1);
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getbit(CF, register, width - modcount);
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register = register << modcount;
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resflags(register);
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local msbAfter:4 = zext(register) >> (width - 1);
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VF = (msbBefore ^ msbAfter) != 0;
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XF = CF;
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}
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macro arithmeticShiftRight(count, register, width) {
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local modcount = count % 64;
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CF = 0;
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resflags(register);
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if (count == 0) goto inst_next;
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local msbBefore:4 = zext(register) >> (width - 1);
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getbit(CF, register, modcount - 1);
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register = register s>> modcount;
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resflags(register);
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local msbAfter:4 = zext(register) >> (width - 1);
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VF = (msbBefore ^ msbAfter) != 0;
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XF = CF;
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}
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macro logicalShiftLeft(count, register, width) {
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local modcount = count % 64;
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CF = 0;
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VF = 0;
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resflags(register);
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if (modcount == 0) goto inst_next;
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getbit(CF, register, width - modcount);
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register = register << modcount;
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resflags(register);
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XF = CF;
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}
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macro logicalShiftRight(count, register, width) {
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local modcount = count % 64;
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CF = 0;
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VF = 0;
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resflags(register);
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if (modcount == 0) goto inst_next;
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getbit(CF, register, width - modcount);
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register = register >> modcount;
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resflags(register);
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XF = CF;
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}
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macro rotateLeft(count, register, width) {
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local modcount = (count % 64) % width;
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VF = 0;
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register = (register << modcount) | (register >> (width - modcount));
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getbit(CF, register, width - 1);
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resflags(register);
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}
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macro rotateRight(count, register, width) {
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local modcount = (count % 64) % width;
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VF = 0;
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register = (register << (width - modcount)) | (register >> modcount);
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getbit(CF, register, 0);
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resflags(register);
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}
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macro rotateLeftExtended(count, register, width) {
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local modcount = (count % 64) % width;
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CF = XF;
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VF = 0;
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resflags(register);
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if (modcount == 0) goto inst_next;
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local xflag = (register & (1 << (width - modcount))) != 0;
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register = (register << modcount) | (zext(XF) << (modcount - 1)) | (register >> (width - modcount + 1));
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XF = xflag;
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CF = XF;
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resflags(register);
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}
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macro rotateRightExtended(count, register, width) {
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local modcount = (count % 64) % width;
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CF = XF;
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VF = 0;
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resflags(register);
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if (modcount == 0) goto inst_next;
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local xflag = (register & (1 << (modcount - 1))) != 0;
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register = (zext(XF) << (width - modcount)) | (register >> modcount) | (register << (width - modcount + 1));
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XF = xflag;
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CF = XF;
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resflags(register);
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}
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:^instruction is extGUARD=0 & mode2 & reg9an & mode & regan & instruction
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:^instruction is extGUARD=0 & mode2 & reg9an & mode & regan & instruction
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[ extGUARD=1; regtfan=regan; savmod1=mode; regtsan=reg9an; savmod2=mode2; ] {}
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[ extGUARD=1; regtfan=regan; savmod1=mode; regtsan=reg9an; savmod2=mode2; ] {}
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@ -751,15 +845,35 @@ with : extGUARD=1 {
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:andi const8,"CCR" is d16=0x23c; const8 { packflags(SR); SR = SR & zext(const8); unpackflags(SR); }
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:andi const8,"CCR" is d16=0x23c; const8 { packflags(SR); SR = SR & zext(const8); unpackflags(SR); }
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:andi const16,SR is opbig=0x2 & d8base=0x7c; const16 & SR { packflags(SR); SR = SR & const16; unpackflags(SR); }
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:andi const16,SR is opbig=0x2 & d8base=0x7c; const16 & SR { packflags(SR); SR = SR & const16; unpackflags(SR); }
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:asl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=0 & regdnb { getbit(CF,regdnb,8-cntreg); regdnb=regdnb<<cntreg; resflags(regdnb);}
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:asl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=0 & regdnb { arithmeticShiftLeft(cntreg, regdnb, 8); }
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:asl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=0 & regdnw { getbit(CF,regdnw,16-cntreg); regdnw=regdnw<<cntreg; resflags(regdnw);}
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:asl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=0 & regdnw { arithmeticShiftLeft(cntreg, regdnw, 16); }
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:asl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=0 & regdn { getbit(CF,regdn,32-cntreg); regdn=regdn<<cntreg; resflags(regdn); }
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:asl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=0 & regdn { arithmeticShiftLeft(cntreg, regdn, 32); }
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:asl eaw is (opbig=0xe1 & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eaw { getbit(CF,eaw,31); eaw=eaw<<1; resflags(eaw); }
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:asl eaw is (opbig=0xe1 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
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local value:2 = eaw;
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local msbBefore = value & 0x8000;
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getbit(CF, value, 15);
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value = value << 1;
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resflags(value);
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local msbAfter = value & 0x8000;
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VF = (msbBefore ^ msbAfter) != 0;
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eaw = value;
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XF = CF;
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}
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:asr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=0 & regdnb { getbit(CF,regdnb,cntreg-1);regdnb=regdnb s>>cntreg; resflags(regdnb);}
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:asr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=0 & regdnb { arithmeticShiftRight(cntreg, regdnb, 8); }
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:asr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=0 & regdnw { getbit(CF,regdnw,cntreg-1);regdnw=regdnw s>>cntreg; resflags(regdnw);}
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:asr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=0 & regdnw { arithmeticShiftRight(cntreg, regdnw, 16); }
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:asr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=0 & regdn { getbit(CF,regdn,cntreg-1); regdn=regdn s>>cntreg; resflags(regdn); }
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:asr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=0 & regdn { arithmeticShiftRight(cntreg, regdn, 32); }
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:asr eaw is (opbig=0xe0 & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eaw { getbit(CF,eaw,0); eaw=eaw s>>1; resflags(eaw); }
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:asr eaw is (opbig=0xe0 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
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local value:2 = eaw;
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local msbBefore = value & 0x8000;
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getbit(CF, value, 0);
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value = value s>> 1;
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resflags(value);
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local msbAfter = value & 0x8000;
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VF = (msbBefore ^ msbAfter) != 0;
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eaw = value;
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XF = CF;
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}
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:b^cc^".b" addr8 is op=6 & cc & addr8 { if (cc) goto addr8; }
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:b^cc^".b" addr8 is op=6 & cc & addr8 { if (cc) goto addr8; }
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:b^cc^".w" addr16 is op=6 & cc & d8base=0; addr16 { if (cc) goto addr16; }
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:b^cc^".w" addr16 is op=6 & cc & d8base=0; addr16 { if (cc) goto addr16; }
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@ -1173,15 +1287,31 @@ macro shiftCXFlags(cntreg) {
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XF = CF * (cntreg != 0) + XF * (cntreg == 0);
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XF = CF * (cntreg != 0) + XF * (cntreg == 0);
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}
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}
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:lsl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=1 & regdnb { getbit(CF,regdnb,8-cntreg); shiftCXFlags(cntreg); regdnb=regdnb<<cntreg; resflags(regdnb);}
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:lsl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=1 & regdnb { logicalShiftLeft(cntreg, regdnb, 8); }
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:lsl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=1 & regdnw { getbit(CF,regdnw,16-cntreg); shiftCXFlags(cntreg); regdnw=regdnw<<cntreg; resflags(regdnw);}
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:lsl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=1 & regdnw { logicalShiftLeft(cntreg, regdnw, 16); }
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:lsl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=1 & regdn { getbit(CF,regdn,32-cntreg); shiftCXFlags(cntreg); regdn=regdn<<cntreg; resflags(regdn); }
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:lsl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=1 & regdn { logicalShiftLeft(cntreg, regdn, 32); }
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:lsl eaw is (opbig=0xe3 & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eaw { getbit(CF,eaw,31); shiftCXFlags(eaw); eaw=eaw<<1; resflags(eaw); }
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:lsl eaw is (opbig=0xe3 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
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local value:2 = eaw;
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getbit(CF, value, 15);
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value = value << 1;
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resflags(value);
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eaw = value;
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VF = 0;
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XF = CF;
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}
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:lsr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=1 & regdnb { getbit(CF,regdnb,cntreg-1); shiftCXFlags(cntreg); regdnb=regdnb >>cntreg; resflags(regdnb);}
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:lsr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=1 & regdnb { logicalShiftRight(cntreg, regdnb, 8); }
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:lsr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=1 & regdnw { getbit(CF,regdnw,cntreg-1); shiftCXFlags(cntreg); regdnw=regdnw >>cntreg; resflags(regdnw);}
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:lsr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=1 & regdnw { logicalShiftRight(cntreg, regdnw, 16); }
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:lsr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=1 & regdn { getbit(CF,regdn,cntreg-1); shiftCXFlags(cntreg); regdn=regdn >>cntreg; resflags(regdn); }
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:lsr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=1 & regdn { logicalShiftRight(cntreg, regdn, 32); }
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:lsr eaw is (opbig=0xe2 & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eaw { getbit(CF,eaw,0); shiftCXFlags(eaw); eaw=eaw >>1; resflags(eaw); }
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:lsr eaw is (opbig=0xe2 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
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local value:2 = eaw;
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getbit(CF, value, 0);
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value = value >> 1;
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resflags(value);
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eaw = value;
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VF = 0;
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XF = CF;
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}
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:move.b eab,e2b is (op=1 & $(DAT_ALTER_ADDR_MODES2))... & eab ; e2b { build eab; local tmp = eab; build e2b; e2b = tmp; resflags(tmp); logflags(); }
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:move.b eab,e2b is (op=1 & $(DAT_ALTER_ADDR_MODES2))... & eab ; e2b { build eab; local tmp = eab; build e2b; e2b = tmp; resflags(tmp); logflags(); }
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:move.w eaw,e2w is (op=3 & $(DAT_ALTER_ADDR_MODES2))... & eaw ; e2w { build eaw; local tmp = eaw; build e2w; e2w = tmp; resflags(tmp); logflags(); }
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:move.w eaw,e2w is (op=3 & $(DAT_ALTER_ADDR_MODES2))... & eaw ; e2w { build eaw; local tmp = eaw; build e2w; e2w = tmp; resflags(tmp); logflags(); }
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@ -1677,37 +1807,57 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; }
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:reset is d16=0x4e70 { reset(); }
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:reset is d16=0x4e70 { reset(); }
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:rol.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=3 & regdnb { regdnb=(regdnb<<cntreg)|(regdnb>>(8-cntreg));
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:rol.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=3 & regdnb { rotateLeft(cntreg, regdnb, 8); }
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getbit(CF,regdnb,0); VF=0; resflags(regdnb); }
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:rol.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=3 & regdnw { rotateLeft(cntreg, regdnw, 16); }
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:rol.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=3 & regdnw { regdnw=(regdnw<<cntreg)|(regdnw>>(16-cntreg));
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:rol.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=3 & regdn { rotateLeft(cntreg, regdn, 32); }
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getbit(CF,regdnw,0); VF=0; resflags(regdnw); }
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:rol eaw is (opbig=0xe7 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
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:rol.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=3 & regdn { regdn=(regdn<<cntreg)|(regdn>>(32-cntreg));
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local value:2 = eaw;
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getbit(CF,regdn,0); VF=0; resflags(regdn); }
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value = (value << 1) | (value >> 15);
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:rol eaw is (opbig=0xe7 & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eaw { eaw = (eaw<<1)|(eaw>>15); getbit(CF,eaw,0); VF=0; resflags(eaw); }
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getbit(CF, value, 0);
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resflags(value);
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eaw = value;
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VF = 0;
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}
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:ror.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=3 & regdnb { regdnb=(regdnb<<(8-cntreg))|(regdnb>>cntreg);
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:ror.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=3 & regdnb { rotateRight(cntreg, regdnb, 8); }
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getbit(CF,regdnb,7); VF=0; resflags(regdnb); }
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:ror.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=3 & regdnw { rotateRight(cntreg, regdnw, 16); }
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:ror.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=3 & regdnw { regdnw=(regdnw<<(16-cntreg))|(regdnw>>cntreg);
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:ror.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=3 & regdn { rotateRight(cntreg, regdn, 32); }
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getbit(CF,regdnw,15); VF=0; resflags(regdnw); }
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:ror eaw is (opbig=0xe6 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
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:ror.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=3 & regdn { regdn=(regdn<<(32-cntreg))|(regdn>>cntreg);
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local value:2 = eaw;
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getbit(CF,regdn,31); VF=0; resflags(regdn); }
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value = (value << 15) | (value >> 1);
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:ror eaw is (opbig=0xe6 & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eaw { eaw = (eaw<<15)|(eaw>>1); getbit(CF,eaw,15); VF=0; resflags(eaw); }
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getbit(CF, value, 15);
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resflags(value);
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eaw = value;
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VF = 0;
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}
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:roxl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=2 & regdnb { CF=(regdnb&(1<<( 8-cntreg)))!=0; regdnb=(zext(XF)<<(cntreg-1))|(regdnb<<cntreg)|(regdnb>>(9-cntreg));
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:roxl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=2 & regdnb { rotateLeftExtended(cntreg, regdnb, 8); }
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XF=CF; VF=0; resflags(regdnb); }
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:roxl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=2 & regdnw { rotateLeftExtended(cntreg, regdnw, 16); }
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:roxl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=2 & regdnw { CF=(regdnw&(1<<(16-cntreg)))!=0; regdnw=(zext(XF)<<(cntreg-1))|(regdnw<<cntreg)|(regdnw>>(17-cntreg));
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:roxl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=2 & regdn { rotateLeftExtended(cntreg, regdn, 32); }
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XF=CF; VF=0; resflags(regdnw); }
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:roxl eaw is (opbig=0xe5 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
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:roxl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=2 & regdn { CF=(regdn &(1<<(32-cntreg)))!=0; regdn =(zext(XF)<<(cntreg-1))|(regdn <<cntreg)|(regdn >>(33-cntreg));
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local value:2 = eaw;
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XF=CF; VF=0; resflags(regdn ); }
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local xflag = (value & 0x8000) != 0;
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:roxl eaw is (opbig=0xe5 & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eaw { CF=(eaw&0x8000)!=0; eaw=zext(XF)|(eaw<<1)|(eaw>>16); XF=CF; VF=0; resflags(eaw); }
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value = (value << 1) | zext(XF);
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||||||
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resflags(value);
|
||||||
|
eaw = value;
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VF = 0;
|
||||||
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XF = xflag;
|
||||||
|
CF = XF;
|
||||||
|
}
|
||||||
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|
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:roxr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=2 & regdnb { CF=(regdnb&(1<<(cntreg-1)))!=0; regdnb=(zext(XF)<<( 8-cntreg))|(regdnb>>cntreg)|(regdnb<<(9 -cntreg));
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:roxr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=2 & regdnb { rotateRightExtended(cntreg, regdnb, 8); }
|
||||||
XF=CF; VF=0; resflags(regdnb); }
|
:roxr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=2 & regdnw { rotateRightExtended(cntreg, regdnw, 16); }
|
||||||
:roxr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=2 & regdnw { CF=(regdnw&(1<<(cntreg-1)))!=0; regdnw=(zext(XF)<<(16-cntreg))|(regdnw>>cntreg)|(regdnw<<(17-cntreg));
|
:roxr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=2 & regdn { rotateRightExtended(cntreg, regdn, 32); }
|
||||||
XF=CF; VF=0; resflags(regdnw); }
|
:roxr eaw is (opbig=0xe4 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
|
||||||
:roxr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=2 & regdn { CF=(regdn &(1<<(cntreg-1)))!=0; regdn =(zext(XF)<<(32-cntreg))|(regdn >>cntreg)|(regdn <<(33-cntreg));
|
local value:2 = eaw;
|
||||||
XF=CF; VF=0; resflags(regdn); }
|
local xflag = (value & 0x0001) != 0;
|
||||||
:roxr eaw is (opbig=0xe4 & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eaw { CF=(eaw&1)!=0; eaw=(zext(XF)<<15)|(eaw>>1); XF=CF; VF=0; resflags(eaw); }
|
value = (zext(XF) << 15) | (value >> 1);
|
||||||
|
resflags(value);
|
||||||
|
eaw = value;
|
||||||
|
VF = 0;
|
||||||
|
XF = xflag;
|
||||||
|
CF = XF;
|
||||||
|
}
|
||||||
|
|
||||||
:rtd "#"^d16 is opbig=0x4e & op37=14 & op02=4; d16 { PC = *SP; SP = SP + 4 + d16; return [PC]; }
|
:rtd "#"^d16 is opbig=0x4e & op37=14 & op02=4; d16 { PC = *SP; SP = SP + 4 + d16; return [PC]; }
|
||||||
:rte is d16=0x4e73 { tmp:4 = 0; return [tmp]; }
|
:rte is d16=0x4e73 { tmp:4 = 0; return [tmp]; }
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue