From 24b2275c0b7bbdb30243d6b3877d0a5fb852243a Mon Sep 17 00:00:00 2001
From: srichmo1 <srichmond2486@gmail.com>
Date: Tue, 5 Sep 2023 10:03:20 -0400
Subject: [PATCH] tmp assigned rd0 instead of LR

---
 .../Atmel/data/languages/avr32a_instruction_flow.sinc           | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc b/Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc
index e45d24bfb8..bcfa9a2479 100644
--- a/Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc
+++ b/Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc
@@ -154,7 +154,7 @@ RJMPdisp: disp is disp4_8 & sdisp0_2
 # 0101 1101 0001 dddd
 
 :ICALL rd0 is op4_12=0x5d1 & rd0 {
-        tmp:4 = LR;
+        tmp:4 = rd0;
         LR = inst_next;
         call [tmp];
 }