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bad endian processing

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This commit is contained in:
mumbel 2019-08-26 17:18:56 -05:00
parent 1bce22e2c7
commit 2f3eeed8ca
2 changed files with 42 additions and 57 deletions
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15
Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
View file

@ -1685,13 +1685,6 @@ macro loadReg(reg) {
tea = tea+4; tea = tea+4;
} }
@ifdef BIT_64
macro loadRegHigh(reg) {
reg[32,32] = *:4(tea);
tea = tea + 4;
}
@endif
macro loadRegisterPartial(reg, ea, sa) { macro loadRegisterPartial(reg, ea, sa) {
mask:$(REGISTER_SIZE) = 0xffffffff; mask:$(REGISTER_SIZE) = 0xffffffff;
sa = ((4-sa) & 3) * 8; sa = ((4-sa) & 3) * 8;
@ -1723,14 +1716,6 @@ macro storeReg(reg) {
tea = tea+4; tea = tea+4;
} }
@ifdef BIT_64
macro storeRegHigh(reg) {
*:4(tea) = reg[32,32];
tea = tea + 4;
}
@endif
macro storeRegisterPartial(reg, ea, sa) { macro storeRegisterPartial(reg, ea, sa) {
@ifdef BIT_64 @ifdef BIT_64
*:4(ea) = reg:4; *:4(ea) = reg:4;

84
Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
View file

@ -213,33 +213,33 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
:e_ldmvcsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=5 :e_ldmvcsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=5
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
loadRegHigh(spr03a); loadReg(spr03a);
loadRegHigh(spr03b); loadReg(spr03b);
} }
# e_ldmvdsrrw 6 (0b0001_10) 0b00110 RA 0b0001_0000 D8 # e_ldmvdsrrw 6 (0b0001_10) 0b00110 RA 0b0001_0000 D8
:e_ldmvdsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=6 :e_ldmvdsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=6
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
loadRegHigh(spr23e); loadReg(spr23e);
loadRegHigh(spr23f); loadReg(spr23f);
} }
# e_ldmvgprw 6 (0b0001_10) 0b00000 RA 0b0001_0000 D8 # e_ldmvgprw 6 (0b0001_10) 0b00000 RA 0b0001_0000 D8
:e_ldmvgprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=0 :e_ldmvgprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=0
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
loadRegHigh(r0); loadReg(r0);
loadRegHigh(r3); loadReg(r3);
loadRegHigh(r4); loadReg(r4);
loadRegHigh(r5); loadReg(r5);
loadRegHigh(r6); loadReg(r6);
loadRegHigh(r7); loadReg(r7);
loadRegHigh(r8); loadReg(r8);
loadRegHigh(r9); loadReg(r9);
loadRegHigh(r10); loadReg(r10);
loadRegHigh(r11); loadReg(r11);
loadRegHigh(r12); loadReg(r12);
} }
# e_ldmvsprw 6 (0b0001_10) 0b00001 RA 0b0001_0000 D8 # e_ldmvsprw 6 (0b0001_10) 0b00001 RA 0b0001_0000 D8
@ -249,7 +249,7 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
#TODO is there a better way to handle this, CR are 4 bit #TODO is there a better way to handle this, CR are 4 bit
# so crall can't be used. And not much code accesses # so crall can't be used. And not much code accesses
# CR in this way, also CRM_CR seems backwards? # CR in this way, also CRM_CR seems backwards?
# loadRegHigh(CR); # loadReg(CR);
local tmpCR:4 = *:4 tea; local tmpCR:4 = *:4 tea;
cr0 = zext(tmpCR[0,4]); cr0 = zext(tmpCR[0,4]);
cr1 = zext(tmpCR[4,4]); cr1 = zext(tmpCR[4,4]);
@ -260,17 +260,17 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
cr6 = zext(tmpCR[24,4]); cr6 = zext(tmpCR[24,4]);
cr7 = zext(tmpCR[28,4]); cr7 = zext(tmpCR[28,4]);
tea = tea + 4; tea = tea + 4;
loadRegHigh(LR); loadReg(LR);
loadRegHigh(CTR); loadReg(CTR);
loadRegHigh(XER); loadReg(XER);
} }
# e_ldmvsrrw 6 (0b0001_10) 0b00100 RA 0b0001_0000 D8 # e_ldmvsrrw 6 (0b0001_10) 0b00100 RA 0b0001_0000 D8
:e_ldmvsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=4 :e_ldmvsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x10 & BITS_21_25=4
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
loadRegHigh(SRR0); loadReg(SRR0);
loadRegHigh(SRR1); loadReg(SRR1);
} }
:e_lha D,dPlusRaOrZeroAddress is $(ISVLE) & OP=14 & D & dPlusRaOrZeroAddress :e_lha D,dPlusRaOrZeroAddress is $(ISVLE) & OP=14 & D & dPlusRaOrZeroAddress
@ -348,33 +348,33 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
:e_stmvcsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=5 :e_stmvcsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=5
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
storeRegHigh(spr03a); storeReg(spr03a);
storeRegHigh(spr03b); storeReg(spr03b);
} }
# e_stmvdsrrw 6 (0b0001_10) 0b00110 RA 0b0001_0001 D8 # e_stmvdsrrw 6 (0b0001_10) 0b00110 RA 0b0001_0001 D8
:e_stmvdsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=6 :e_stmvdsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=6
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
storeRegHigh(spr23e); storeReg(spr23e);
storeRegHigh(spr23f); storeReg(spr23f);
} }
# e_stmvgprw 6 (0b0001_10) 0b00000 RA 0b0001_0001 D8 # e_stmvgprw 6 (0b0001_10) 0b00000 RA 0b0001_0001 D8
:e_stmvgprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=0 :e_stmvgprw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=0
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
storeRegHigh(r0); storeReg(r0);
storeRegHigh(r3); storeReg(r3);
storeRegHigh(r4); storeReg(r4);
storeRegHigh(r5); storeReg(r5);
storeRegHigh(r6); storeReg(r6);
storeRegHigh(r7); storeReg(r7);
storeRegHigh(r8); storeReg(r8);
storeRegHigh(r9); storeReg(r9);
storeRegHigh(r10); storeReg(r10);
storeRegHigh(r11); storeReg(r11);
storeRegHigh(r12); storeReg(r12);
} }
# e_stmvsprw 6 (0b0001_10) 0b00001 RA 0b0001_0001 D8 # e_stmvsprw 6 (0b0001_10) 0b00001 RA 0b0001_0001 D8
@ -382,7 +382,7 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
#TODO SEE TODO in e_ldmvsprw #TODO SEE TODO in e_ldmvsprw
# storeRegHigh(CR); # storeReg(CR);
local tmpCR:4 = 0; local tmpCR:4 = 0;
tmpCR = tmpCR | zext((cr0 & 0xf) << 0); tmpCR = tmpCR | zext((cr0 & 0xf) << 0);
tmpCR = tmpCR | zext((cr1 & 0xf) << 4); tmpCR = tmpCR | zext((cr1 & 0xf) << 4);
@ -394,17 +394,17 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
tmpCR = tmpCR | zext((cr7 & 0xf) << 28); tmpCR = tmpCR | zext((cr7 & 0xf) << 28);
*:4 tea = tmpCR; *:4 tea = tmpCR;
tea = tea + 4; tea = tea + 4;
storeRegHigh(LR); storeReg(LR);
storeRegHigh(CTR); storeReg(CTR);
storeRegHigh(XER); storeReg(XER);
} }
# e_stmvsrrw 6 (0b0001_10) 0b00100 RA 0b0001_0001 D8 # e_stmvsrrw 6 (0b0001_10) 0b00100 RA 0b0001_0001 D8
:e_stmvsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=4 :e_stmvsrrw d8PlusRaOrZeroAddress is $(ISVLE) & OP=6 & d8PlusRaOrZeroAddress & XOP_8_VLE=0x11 & BITS_21_25=4
{ {
tea = d8PlusRaOrZeroAddress; tea = d8PlusRaOrZeroAddress;
storeRegHigh(SRR0); storeReg(SRR0);
storeRegHigh(SRR1); storeReg(SRR1);
} }
:e_stw S,dPlusRaOrZeroAddress is $(ISVLE) & OP=21 & S & dPlusRaOrZeroAddress :e_stw S,dPlusRaOrZeroAddress is $(ISVLE) & OP=21 & S & dPlusRaOrZeroAddress