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First pass at LaneDivide transformer
This commit is contained in:
caheckman
parent
5ef7347ca3
commit
31eab44f54
2 changed files with 466 additions and 0 deletions
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@ -1917,3 +1917,441 @@ bool SubfloatFlow::doTrace(void)
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if (terminatorCount == 0) return false; // Must see at least 1 terminator
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return true;
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}
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/// \brief Find or build the placeholder objects for a Varnode that needs to be split into lanes
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///
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/// The Varnode is split based on the given subset of the lane description.
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/// Constants can be split. Decide if the Varnode needs to go into the work list.
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/// If the Varnode cannot be acceptably split, return null.
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/// \param vn is the Varnode that needs to be split
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/// \param numLanes is the number of lanes in the subset
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/// \param skipLanes is the start (least significant) lane in the subset
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/// \return the array of placeholders describing the split or null
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TransformVar *LaneDivide::setReplacement(Varnode *vn,int4 numLanes,int4 skipLanes)
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{
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if (vn->isMark()) // Already seen before
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return getSplit(vn, description, numLanes, skipLanes);
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if (vn->isConstant()) {
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return newSplit(vn,description, numLanes, skipLanes);
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}
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if (vn->isFree())
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return (TransformVar *)0; // Abort
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if (vn->isTypeLock())
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return (TransformVar *)0;
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vn->setMark();
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TransformVar *res = newSplit(vn, description, numLanes, skipLanes);
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workList.push_back(WorkNode());
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workList.back().lanes = res;
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workList.back().numLanes = numLanes;
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workList.back().skipLanes = skipLanes;
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return res;
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}
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/// \brief Build unary op placeholders with the same opcode across a set of lanes
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///
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/// We assume the input and output placeholder variables have already been collected
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/// \param opc is the desired opcode for the new op placeholders
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/// \param op is the PcodeOp getting replaced
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/// \param inVars is the array of input variables, 1 for each unary op
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/// \param outVars is the array of output variables, 1 for each unary op
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/// \param numLanes is the number of unary ops to create
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void LaneDivide::buildUnaryOp(OpCode opc,PcodeOp *op,TransformVar *inVars,TransformVar *outVars,int4 numLanes)
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{
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for(int4 i=0;i<numLanes;++i) {
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TransformVar *outVn = outVars + i;
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TransformOp *rop = newOpReplace(1, opc, op);
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opSetOutput(rop, outVn);
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opSetInput(rop,inVars + i,0);
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}
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}
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/// \brief Build binary op placeholders with the same opcode across a set of lanes
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///
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/// We assume the input and output placeholder variables have already been collected
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/// \param opc is the desired opcode for the new op placeholders
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/// \param op is the PcodeOp getting replaced
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/// \param in0Vars is the array of input[0] variables, 1 for each binary op
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/// \param in1Vars is the array of input[1] variables, 1 for each binar op
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/// \param outVars is the array of output variables, 1 for each binary op
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/// \param numLanes is the number of binary ops to create
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void LaneDivide::buildBinaryOp(OpCode opc,PcodeOp *op,TransformVar *in0Vars,TransformVar *in1Vars,
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TransformVar *outVars,int4 numLanes)
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{
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for(int4 i=0;i<numLanes;++i) {
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TransformOp *rop = newOpReplace(2, opc, op);
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opSetOutput(rop, outVars + i);
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opSetInput(rop,in0Vars + i, 0);
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opSetInput(rop,in1Vars + i, 1);
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}
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}
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/// \brief Convert a CPUI_PIECE operation into copies between placeholders, given the output lanes
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///
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/// Model the given CPUI_PIECE either as either copies from preexisting Varnodes into the
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/// output lanes, or as copies from placeholder variables into the output lanes. Return \b false
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/// if the operation cannot be modeled as natural copies between lanes.
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/// \param op is the original CPUI_PIECE PcodeOp
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/// \param outVars is the placeholder variables making up the lanes of the output
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/// \param numLanes is the number of lanes in the output
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/// \param skipLanes is the index of the least significant output lane within the global description
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/// \return \b true if the CPUI_PIECE was modeled as natural lane copies
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bool LaneDivide::buildPiece(PcodeOp *op,TransformVar *outVars,int4 numLanes,int4 skipLanes)
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{
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int4 highLanes,highSkip;
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int4 lowLanes,lowSkip;
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TransformVar *highVars,*lowVars;
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Varnode *outVn = op->getOut();
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Varnode *highVn = op->getIn(0);
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Varnode *lowVn = op->getIn(1);
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if (!description.restriction(numLanes,skipLanes,lowVn->getSize(),outVn->getSize(),highLanes,highSkip))
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return false;
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if (!description.restriction(numLanes,skipLanes,0,outVn->getSize(),lowLanes,lowSkip))
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return false;
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if (highLanes == 1) {
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TransformVar *highRvn = getPreexistingVarnode(highVn);
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TransformOp *rop = newOpReplace(1, CPUI_COPY, op);
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opSetInput(rop,highRvn,0);
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opSetOutput(rop,outVars + (numLanes-1));
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}
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else { // Multi-lane high
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TransformVar *highRvn = setReplacement(highVn, highLanes, highSkip);
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if (highRvn == (TransformVar *)0) return false;
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int4 outHighStart = numLanes - highLanes;
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for(int4 i=0;i<highLanes;++i) {
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TransformOp *rop = newOpReplace(1, CPUI_COPY, op);
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opSetInput(rop,highRvn+i,0);
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opSetOutput(rop,outVars + (outHighStart + i));
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}
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}
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if (lowLanes == 1) {
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TransformVar *lowRvn = getPreexistingVarnode(lowVn);
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TransformOp *rop = newOpReplace(1, CPUI_COPY, op);
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opSetInput(rop,lowRvn,0);
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opSetOutput(rop,outVars);
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}
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else { // Multi-lane low
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TransformVar *lowRvn = setReplacement(lowVn, lowLanes, lowSkip);
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if (lowRvn == (TransformVar *)0) return false;
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for(int4 i=0;i<lowLanes;++i) {
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TransformOp *rop = newOpReplace(1, CPUI_COPY, op);
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opSetInput(rop,lowRvn+i,0);
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opSetOutput(rop,outVars + i);
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}
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}
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return true;
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}
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/// \brief Split a given CPUI_MULTIEQUAL operation into placeholders given the output lanes
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///
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/// Model the single given CPUI_MULTIEQUAL as a sequence of smaller MULTIEQUALs on
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/// each individual lane. Return \b false if the operation cannot be modeled as naturally.
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/// \param op is the original CPUI_MULTIEQUAL PcodeOp
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/// \param outVars is the placeholder variables making up the lanes of the output
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/// \param numLanes is the number of lanes in the output
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/// \param skipLanes is the index of the least significant output lane within the global description
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/// \return \b true if the operation was fully modeled
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bool LaneDivide::buildMultiequal(PcodeOp *op,TransformVar *outVars,int4 numLanes,int4 skipLanes)
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{
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vector<TransformVar *> inVarSets;
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int4 numInput = op->numInput();
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for(int4 i=0;i<numInput;++i) {
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TransformVar *inVn = setReplacement(op->getIn(i), numLanes, skipLanes);
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if (inVn == (TransformVar *)0) return false;
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inVarSets.push_back(inVn);
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}
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for(int4 i=0;i<numLanes;++i) {
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TransformOp *rop = newOpReplace(numInput, CPUI_MULTIEQUAL, op);
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opSetOutput(rop, outVars + i);
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for(int4 j=0;j<numInput;++j)
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opSetInput(rop, inVarSets[j] + i, j);
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}
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return true;
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}
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/// \brief Split a given CPUI_STORE operation into a sequence of STOREs of individual lanes
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///
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/// A new pointer is constructed for each individual lane into a temporary, then a
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/// STORE is created using the pointer that stores an individual lane.
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/// \param op is the given CPUI_STORE PcodeOp
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/// \param numLanes is the number of lanes the STORE is split into
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/// \param skipLanes is the starting lane (within the global description) of the value being stored
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/// \return \b true if the CPUI_STORE was successfully modeled on lanes
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bool LaneDivide::buildStore(PcodeOp *op,int4 numLanes,int4 skipLanes)
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{
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TransformVar *inVars = setReplacement(op->getIn(2), numLanes, skipLanes);
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if (inVars == (TransformVar *)0) return false;
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uintb spaceConst = op->getIn(0)->getOffset();
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int4 spaceConstSize = op->getIn(0)->getSize();
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AddrSpace *spc = Address::getSpaceFromConst(op->getIn(0)->getAddr()); // Address space being stored to
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Varnode *origPtr = op->getIn(1);
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if (origPtr->isFree()) {
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if (!origPtr->isConstant()) return false;
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}
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TransformVar *basePtr = getPreexistingVarnode(origPtr);
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int4 ptrSize = origPtr->getSize();
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Varnode *valueVn = op->getIn(2);
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for(int4 i=0;i<numLanes;++i) {
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TransformOp *ropStore = newOpReplace(3, CPUI_STORE, op);
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int4 bytePos = description.getPosition(skipLanes + i);
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int4 sz = description.getSize(skipLanes + i);
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if (spc->isBigEndian())
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bytePos = valueVn->getSize() - (bytePos + sz); // Convert position to address order
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// Construct the pointer
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TransformVar *ptrVn;
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if (bytePos == 0)
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ptrVn = basePtr;
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else {
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ptrVn = newUnique(ptrSize);
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TransformOp *addOp = newOp(2, CPUI_INT_ADD, ropStore);
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opSetOutput(addOp,ptrVn);
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opSetInput(addOp,basePtr,0);
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opSetInput(addOp,newConstant(ptrSize, 0, bytePos), 1);
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}
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opSetInput(ropStore,newConstant(spaceConstSize,0,spaceConst),0);
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opSetInput(ropStore,ptrVn,1);
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opSetInput(ropStore,inVars+i,2);
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}
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return true;
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}
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/// \brief Split a given CPUI_LOAD operation into a sequence of LOADs of individual lanes
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///
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/// A new pointer is constructed for each individual lane into a temporary, then a
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/// LOAD is created using the pointer that loads an individual lane.
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/// \param op is the given CPUI_LOAD PcodeOp
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/// \param outVars is the output placeholders for the LOAD
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/// \param numLanes is the number of lanes the LOAD is split into
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/// \param skipLanes is the starting lane (within the global description) of the value being loaded
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/// \return \b true if the CPUI_LOAD was successfully modeled on lanes
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bool LaneDivide::buildLoad(PcodeOp *op,TransformVar *outVars,int4 numLanes,int4 skipLanes)
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{
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uintb spaceConst = op->getIn(0)->getOffset();
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int4 spaceConstSize = op->getIn(0)->getSize();
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AddrSpace *spc = Address::getSpaceFromConst(op->getIn(0)->getAddr()); // Address space being stored to
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Varnode *origPtr = op->getIn(1);
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if (origPtr->isFree()) {
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if (!origPtr->isConstant()) return false;
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}
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TransformVar *basePtr = getPreexistingVarnode(origPtr);
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int4 ptrSize = origPtr->getSize();
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int4 outSize = op->getOut()->getSize();
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for(int4 i=0;i<numLanes;++i) {
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TransformOp *ropLoad = newOpReplace(2, CPUI_LOAD, op);
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int4 bytePos = description.getPosition(skipLanes + i);
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int4 sz = description.getSize(skipLanes + i);
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if (spc->isBigEndian())
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bytePos = outSize - (bytePos + sz); // Convert position to address order
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// Construct the pointer
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TransformVar *ptrVn;
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if (bytePos == 0)
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ptrVn = basePtr;
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else {
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ptrVn = newUnique(ptrSize);
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TransformOp *addOp = newOp(2, CPUI_INT_ADD, ropLoad);
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opSetOutput(addOp,ptrVn);
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opSetInput(addOp,basePtr,0);
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opSetInput(addOp,newConstant(ptrSize, 0, bytePos), 1);
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}
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opSetInput(ropLoad,newConstant(spaceConstSize,0,spaceConst),0);
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opSetInput(ropLoad,ptrVn,1);
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opSetOutput(ropLoad,outVars+i);
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}
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return true;
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}
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/// \brief Push the logical lanes forward through any PcodeOp reading the given variable
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///
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/// Determine if the logical lanes can be pushed forward naturally, and create placeholder
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/// variables and ops representing the logical data-flow. Update the worklist with any
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/// new Varnodes that the lanes get pushed into.
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/// \param rvn is the placeholder variable to push forward from
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/// \param numLanes is the number of lanes represented by the placeholder variable
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/// \param skipLanes is the index of the starting lane within the global description of the placeholder variable
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/// \return \b true if the lanes can be naturally pushed forward
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bool LaneDivide::traceForward(TransformVar *rvn,int4 numLanes,int4 skipLanes)
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{
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Varnode *origvn = rvn->getOriginal();
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list<PcodeOp *>::const_iterator iter,enditer;
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iter = origvn->beginDescend();
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enditer = origvn->endDescend();
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while(iter != enditer) {
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PcodeOp *op = *iter++;
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Varnode *outvn = op->getOut();
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if ((outvn!=(Varnode *)0)&&(outvn->isMark()))
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continue;
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switch(op->code()) {
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case CPUI_SUBPIECE:
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{
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int4 bytePos = (int4)op->getIn(1)->getOffset();
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int4 outLanes,outSkip;
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if (!description.restriction(numLanes, skipLanes, bytePos, outvn->getSize(), outLanes, outSkip))
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return false;
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if (outLanes == 1) {
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TransformOp *rop = newPreexistingOp(1, CPUI_COPY, op);
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opSetInput(rop,rvn + (outLanes-skipLanes), 0);
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}
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else {
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TransformVar *outRvn = setReplacement(outvn,outLanes,outSkip);
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if (outRvn == (TransformVar *)0) return false;
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buildUnaryOp(CPUI_COPY,op,rvn + (outLanes-skipLanes),outRvn,outLanes);
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}
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break;
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}
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case CPUI_PIECE:
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{
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int4 outLanes,outSkip;
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int4 bytePos = (op->getIn(0) == origvn) ? op->getIn(1)->getSize() : 0;
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if (!description.extension(numLanes, skipLanes, bytePos, outvn->getSize(), outLanes, outSkip))
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return false;
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TransformVar *outRvn = setReplacement(outvn,outLanes,outSkip);
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if (outRvn == (TransformVar *)0) return false;
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// Don't create the placeholder ops, let traceBackward make them
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break;
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}
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case CPUI_COPY:
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case CPUI_INT_NEGATE:
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case CPUI_INT_AND:
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case CPUI_INT_OR:
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case CPUI_INT_XOR:
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case CPUI_MULTIEQUAL:
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{
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TransformVar *outRvn = setReplacement(outvn,numLanes,skipLanes);
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if (outRvn == (TransformVar *)0) return false;
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// Don't create the placeholder ops, let traceBackward make them
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break;
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}
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case CPUI_STORE:
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if (op->getIn(2) != origvn) return false; // Can only propagate through value being stored
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if (!buildStore(op,numLanes,skipLanes))
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return false;
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break;
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default:
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return false;
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}
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}
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}
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/// \brief Pull the logical lanes back through the defining PcodeOp of the given variable
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///
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/// Determine if the logical lanes can be pulled back naturally, and create placeholder
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/// variables and ops representing the logical data-flow. Update the worklist with any
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/// new Varnodes that the lanes get pulled back into.
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/// \param rvn is the placeholder variable to pull back
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/// \param numLanes is the number of lanes represented by the placeholder variable
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/// \param skipLanes is the index of the starting lane within the global description of the placeholder variable
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/// \return \b true if the lanes can be naturally pulled back
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bool LaneDivide::traceBackward(TransformVar *rvn,int4 numLanes,int4 skipLanes)
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{
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PcodeOp *op = rvn->getOriginal()->getDef();
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if (op == (PcodeOp *)0) return true; // If vn is input
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switch(op->code()) {
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case CPUI_INT_NEGATE:
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case CPUI_COPY:
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{
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TransformVar *inVars = setReplacement(op->getIn(0),numLanes,skipLanes);
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if (inVars == (TransformVar *)0) return false;
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buildUnaryOp(op->code(), op, inVars, rvn, numLanes);
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break;
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}
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case CPUI_INT_AND:
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case CPUI_INT_OR:
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case CPUI_INT_XOR:
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{
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TransformVar *in0Vars = setReplacement(op->getIn(0),numLanes,skipLanes);
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if (in0Vars == (TransformVar *)0) return false;
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TransformVar *in1Vars = setReplacement(op->getIn(1),numLanes,skipLanes);
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if (in1Vars == (TransformVar *)0) return false;
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buildBinaryOp(op->code(),op,in0Vars,in1Vars,rvn,numLanes);
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break;
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}
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case CPUI_MULTIEQUAL:
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if (!buildMultiequal(op, rvn, numLanes, skipLanes))
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return false;
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break;
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case CPUI_SUBPIECE:
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{
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Varnode *inVn = op->getIn(0);
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int4 bytePos = (int4)op->getIn(1)->getOffset();
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int4 inLanes,inSkip;
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if (!description.extension(numLanes, skipLanes, bytePos, inVn->getSize(), inLanes, inSkip))
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return false;
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TransformVar *inVars = setReplacement(inVn,inLanes,inSkip);
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if (inVars == (TransformVar *)0) return false;
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buildUnaryOp(CPUI_COPY,op,inVars + (skipLanes - inSkip), rvn, inLanes);
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break;
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}
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case CPUI_PIECE:
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if (!buildPiece(op, rvn, numLanes, skipLanes))
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return false;
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break;
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case CPUI_LOAD:
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if (!buildLoad(op, rvn, numLanes, skipLanes))
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return false;
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break;
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default:
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return false;
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}
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return true;
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}
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/// \return \b true if the lane split for the top Varnode on the work list is propagated through local operators
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||||
bool LaneDivide::processNextWork(void)
|
||||
|
||||
{
|
||||
TransformVar *rvn = workList.back();
|
||||
int4 numLanes = workList.back().numLanes;
|
||||
int4 skipLanes = workList.back().skipLanes;
|
||||
|
||||
workList.pop_back();
|
||||
|
||||
if (!traceBackward(rvn,numLanes,skipLanes)) return false;
|
||||
return traceForward(rvn,numLanes,skipLanes);
|
||||
}
|
||||
|
||||
/// \param f is the function being transformed
|
||||
/// \param root is the root Varnode to start tracing lanes from
|
||||
/// \param desc is a description of the lanes on the root Varnode
|
||||
LaneDivide::LaneDivide(Funcdata *f,Varnode *root,const LaneDescription &desc)
|
||||
: TransformManager(f), description(desc)
|
||||
{
|
||||
setReplacement(root, desc.getNumLanes(), 0);
|
||||
}
|
||||
|
||||
/// Push the lanes around from the root, setting up the explicit transforms as we go.
|
||||
/// If at any point, the lanes cannot be naturally pushed, return \b false.
|
||||
/// \return \b true if a full transform has been constructed that can split into explicit lanes
|
||||
bool LaneDivide::doTrace(void)
|
||||
|
||||
{
|
||||
if (workList.empty())
|
||||
return false; // Nothing to do
|
||||
bool retval = true;
|
||||
while(!workList.empty()) { // Process the work list until its done
|
||||
if (!processNextWork()) {
|
||||
retval = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
clearVarnodeMarks();
|
||||
if (!retval) return false;
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -154,4 +154,32 @@ public:
|
|||
bool doTrace(void); ///< Trace logical value as far as possible
|
||||
};
|
||||
|
||||
class LaneDivide : public TransformManager {
|
||||
/// \brief Description of a large Varnode that needs to be traced (in the worklist)
|
||||
class WorkNode {
|
||||
friend class LaneDivide;
|
||||
Varnode *vn; ///< The underlying Varnode with lanes
|
||||
TransformVar *lanes; ///< Lane placeholders for underyling Varnode
|
||||
int4 numLanes; ///< Number of lanes in the particular Varnode
|
||||
int4 skipLanes; ///< Number of lanes to skip in the global description
|
||||
};
|
||||
|
||||
LaneDescription description; ///< Global description of lanes that need to be split
|
||||
vector<WorkNode> workList; ///< List of Varnodes still left to trace
|
||||
|
||||
TransformVar *setReplacement(Varnode *vn,int4 numLanes,int4 skipLanes);
|
||||
void buildUnaryOp(OpCode opc,PcodeOp *op,TransformVar *inVars,TransformVar *outVars,int4 numLanes);
|
||||
void buildBinaryOp(OpCode opc,PcodeOp *op,TransformVar *in0Vars,TransformVar *in1Vars,TransformVar *outVars,int4 numLanes);
|
||||
bool buildPiece(PcodeOp *op,TransformVar *outVars,int4 numLanes,int4 skipLanes);
|
||||
bool buildMultiequal(PcodeOp *op,TransformVar *outVars,int4 numLanes,int4 skipLanes);
|
||||
bool buildStore(PcodeOp *op,int4 numLanes,int4 skipLanes);
|
||||
bool buildLoad(PcodeOp *op,TransformVar *outVars,int4 numLanes,int4 skipLanes);
|
||||
bool traceForward(TransformVar *rvn,int4 numLanes,int4 skipLanes);
|
||||
bool traceBackward(TransformVar *rvn,int4 numLanes,int4 skipLanes);
|
||||
bool processNextWork(void); ///< Process the next Varnode on the work list
|
||||
public:
|
||||
LaneDivide(Funcdata *f,Varnode *root,const LaneDescription &desc); ///< Constructor
|
||||
bool doTrace(void); ///< Trace lanes as far as possible from the root Varnode
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue