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Code Issues Releases Wiki Activity

Merge remote-tracking branch 'origin/Ghidra_10.2'

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This commit is contained in:
Ryan Kurtz 2022-10-28 01:00:17 -04:00
commit 41db174443
11 changed files with 1371 additions and 1024 deletions
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10
Ghidra/Framework/Docking/src/main/java/docking/DockableToolBarManager.java
View file

@ -173,6 +173,7 @@ class DockableToolBarManager {
Tool tool = dwm.getTool(); Tool tool = dwm.getTool();
ComponentProvider provider = dockableComponent.getComponentProvider(); ComponentProvider provider = dockableComponent.getComponentProvider();
tool.removeLocalAction(provider, closeButtonManager.getAction()); tool.removeLocalAction(provider, closeButtonManager.getAction());
tool.removeLocalAction(provider, menuButtonManager.getAction());
} }
headerUpdater.dispose(); headerUpdater.dispose();
@ -253,5 +254,14 @@ class DockableToolBarManager {
popupMenu.addPopupMenuListener(menuManager.getMenuHandler()); popupMenu.addPopupMenuListener(menuManager.getMenuHandler());
popupMenu.show(myButton, 0, d.height); popupMenu.show(myButton, 0, d.height);
} }
@Override
public boolean isEnabledForContext(ActionContext context) {
if (myButton == null) {
return false; // no menu items; no drop-down menu
}
ComponentProvider provider = context.getComponentProvider();
return provider == dockableComponent.getComponentProvider();
}
} }
} }

38
Ghidra/Processors/ARM/data/languages/ARM.ldefs
View file

@ -5,7 +5,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v8" variant="v8"
version="1.104" version="1.105"
slafile="ARM8_le.sla" slafile="ARM8_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -29,7 +29,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v8T" variant="v8T"
version="1.104" version="1.105"
slafile="ARM8_le.sla" slafile="ARM8_le.sla"
processorspec="ARMtTHUMB.pspec" processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -49,7 +49,7 @@
instructionEndian="little" instructionEndian="little"
size="32" size="32"
variant="v8LEInstruction" variant="v8LEInstruction"
version="1.104" version="1.105"
slafile="ARM8_le.sla" slafile="ARM8_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -64,7 +64,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v8" variant="v8"
version="1.104" version="1.105"
slafile="ARM8_be.sla" slafile="ARM8_be.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -87,7 +87,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v8T" variant="v8T"
version="1.104" version="1.105"
slafile="ARM8_be.sla" slafile="ARM8_be.sla"
processorspec="ARMtTHUMB.pspec" processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -104,7 +104,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v7" variant="v7"
version="1.104" version="1.105"
slafile="ARM7_le.sla" slafile="ARM7_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -124,7 +124,7 @@
instructionEndian="little" instructionEndian="little"
size="32" size="32"
variant="v7LEInstruction" variant="v7LEInstruction"
version="1.104" version="1.105"
slafile="ARM7_le.sla" slafile="ARM7_le.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -139,7 +139,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v7" variant="v7"
version="1.104" version="1.105"
slafile="ARM7_be.sla" slafile="ARM7_be.sla"
processorspec="ARMt.pspec" processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -157,7 +157,7 @@
endian="little" endian="little"
size="32" size="32"
variant="Cortex" variant="Cortex"
version="1.104" version="1.105"
slafile="ARM7_le.sla" slafile="ARM7_le.sla"
processorspec="ARMCortex.pspec" processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -177,7 +177,7 @@
endian="big" endian="big"
size="32" size="32"
variant="Cortex" variant="Cortex"
version="1.104" version="1.105"
slafile="ARM7_be.sla" slafile="ARM7_be.sla"
processorspec="ARMCortex.pspec" processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -196,7 +196,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v6" variant="v6"
version="1.104" version="1.105"
slafile="ARM6_le.sla" slafile="ARM6_le.sla"
processorspec="ARMt_v6.pspec" processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -216,7 +216,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v6" variant="v6"
version="1.104" version="1.105"
slafile="ARM6_be.sla" slafile="ARM6_be.sla"
processorspec="ARMt_v6.pspec" processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -236,7 +236,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v5t" variant="v5t"
version="1.104" version="1.105"
slafile="ARM5t_le.sla" slafile="ARM5t_le.sla"
processorspec="ARMt_v45.pspec" processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -254,7 +254,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v5t" variant="v5t"
version="1.104" version="1.105"
slafile="ARM5t_be.sla" slafile="ARM5t_be.sla"
processorspec="ARMt_v45.pspec" processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -272,7 +272,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v5" variant="v5"
version="1.104" version="1.105"
slafile="ARM5_le.sla" slafile="ARM5_le.sla"
processorspec="ARM_v45.pspec" processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -304,7 +304,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v4t" variant="v4t"
version="1.104" version="1.105"
slafile="ARM4t_le.sla" slafile="ARM4t_le.sla"
processorspec="ARMt_v45.pspec" processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -321,7 +321,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v4t" variant="v4t"
version="1.104" version="1.105"
slafile="ARM4t_be.sla" slafile="ARM4t_be.sla"
processorspec="ARMt_v45.pspec" processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -338,7 +338,7 @@
endian="little" endian="little"
size="32" size="32"
variant="v4" variant="v4"
version="1.104" version="1.105"
slafile="ARM4_le.sla" slafile="ARM4_le.sla"
processorspec="ARM_v45.pspec" processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"
@ -358,7 +358,7 @@
endian="big" endian="big"
size="32" size="32"
variant="v4" variant="v4"
version="1.104" version="1.105"
slafile="ARM4_be.sla" slafile="ARM4_be.sla"
processorspec="ARM_v45.pspec" processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx" manualindexfile="../manuals/ARM.idx"

4
Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
View file

@ -2276,14 +2276,14 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(val); Rt1215 = zext(val);
} }
:ldrsb^ItCond".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12 :ldrsb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12
{ {
build ItCond; build ItCond;
tmp:1 = *RnIndirect12; tmp:1 = *RnIndirect12;
Rt1215 = sext(tmp); Rt1215 = sext(tmp);
} }
:ldrsb^ItCond".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf91; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) :ldrsb^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf91; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW)
{ {
build ItCond; build ItCond;
build RnIndirectPUW; build RnIndirectPUW;

848
Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
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File diff suppressed because it is too large Load diff

1061
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
View file

File diff suppressed because it is too large Load diff

151
Ghidra/Processors/ARM/data/languages/ARMv8.sinc
View file

@ -434,7 +434,7 @@ define pcodeop PolynomialMult;
# F6.1.59 p8000 A1 op == 1 (c0808) # F6.1.59 p8000 A1 op == 1 (c0808)
:vcvt.f32.f16 Qd,Dm :vcvt.f32.f16 Qd,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=1)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=1)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=1))
& Qd & Dm & Qd & Dm
{ {
@ -443,7 +443,7 @@ define pcodeop PolynomialMult;
# F6.1.59 p8000 A1 op == 0 (c0808) # F6.1.59 p8000 A1 op == 0 (c0808)
:vcvt.f16.f32 Dd,Qm :vcvt.f16.f32 Dd,Qm
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b01 & c1617=0b10 & c0911=0b011 & c0607=0b00 & c0404=0 & c0808=0)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=0)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b01 & thv_c1617=0b10 & thv_c0911=0b011 & thv_c0607=0b00 & thv_c0404=0 & thv_c0808=0))
& Dd & Qm & Dd & Qm
{ Dd = float2float(Qm); } { Dd = float2float(Qm); }
@ -492,14 +492,14 @@ vcvt_56_128_dt: ".u32.f32"
# F6.1.60 p8002 A1 Q == 0 (c0606) # F6.1.60 p8002 A1 Q == 0 (c0606)
:vcvt^vcvt_56_64_dt Dd,Dm :vcvt^vcvt_56_64_dt Dd,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=0)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=0)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=0))
& vcvt_56_64_dt & Dd & Dm & vcvt_56_64_dt & Dd & Dm
unimpl unimpl
# F6.1.60 p8002 A1 Q == 1 (c0606) # F6.1.60 p8002 A1 Q == 1 (c0606)
:vcvt^vcvt_56_128_dt Qd,Qm :vcvt^vcvt_56_128_dt Qd,Qm
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c0911=0b011 & c0404=0 & c0606=1)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=1)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c0911=0b011 & thv_c0404=0 & thv_c0606=1))
& vcvt_56_128_dt & Qd & Qm & vcvt_56_128_dt & Qd & Qm
unimpl unimpl
@ -576,44 +576,84 @@ vcvt_59_fbits: "#"^fbits is TMode=0 & c1621 [ fbits = 64 - c1621; ] {
vcvt_59_fbits: "#"^fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { } vcvt_59_fbits: "#"^fbits is TMode=1 & thv_c1621 [ fbits = 64 - thv_c1621; ] { }
vcvt_59_32_dt: ".f32.s32" vcvt_59_32_dt: ".f32.s32"
is ((TMode=0 & c0808=0 & c2424=0) is ((TMode=0 & c0809=2 & c2424=0)
| (TMode=1 & thv_c0808=0 & thv_c2828=0)) | (TMode=1 & thv_c0809=2 & thv_c2828=0))
& Dd & Dm & vcvt_59_fbits_built & Dd & Dm & vcvt_59_fbits_built
{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }
vcvt_59_32_dt: ".f32.u32" vcvt_59_32_dt: ".f32.u32"
is ((TMode=0 & c0808=0 & c2424=1) is ((TMode=0 & c0809=2 & c2424=1)
| (TMode=1 & thv_c0808=0 & thv_c2828=1)) | (TMode=1 & thv_c0809=2 & thv_c2828=1))
& Dd & Dm & vcvt_59_fbits_built & Dd & Dm & vcvt_59_fbits_built
{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } { Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }
vcvt_59_32_dt: ".s32.f32" vcvt_59_32_dt: ".s32.f32"
is ((TMode=0 & c0808=1 & c2424=0) is ((TMode=0 & c0809=3 & c2424=0)
| (TMode=1 & thv_c0808=1 & thv_c2828=0)) | (TMode=1 & thv_c0809=3 & thv_c2828=0))
& Dd & Dm & vcvt_59_fbits_built & Dd & Dm & vcvt_59_fbits_built
{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }
vcvt_59_32_dt: ".u32.f32" vcvt_59_32_dt: ".u32.f32"
is ((TMode=0 & c0808=1 & c2424=1) is ((TMode=0 & c0809=3 & c2424=1)
| (TMode=1 & thv_c0808=1 & thv_c2828=1)) | (TMode=1 & thv_c0809=3 & thv_c2828=1))
& Dd & Dm & vcvt_59_fbits_built & Dd & Dm & vcvt_59_fbits_built
{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } { Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }
vcvt_59_32_dt: ".f16.s16"
is ((TMode=0 & c0809=0 & c2424=0)
| (TMode=1 & thv_c0809=0 & thv_c2828=0))
& Dd & Dm & vcvt_59_fbits_built
{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }
vcvt_59_32_dt: ".f16.u16"
is ((TMode=0 & c0809=0 & c2424=1)
| (TMode=1 & thv_c0809=0 & thv_c2828=1))
& Dd & Dm & vcvt_59_fbits_built
{ Dd = FixedToFP(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }
vcvt_59_32_dt: ".s16.f16"
is ((TMode=0 & c0809=1 & c2424=0)
| (TMode=1 & thv_c0809=1 & thv_c2828=0))
& Dd & Dm & vcvt_59_fbits_built
{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }
vcvt_59_32_dt: ".u16.f16"
is ((TMode=0 & c0809=1 & c2424=1)
| (TMode=1 & thv_c0809=1 & thv_c2828=1))
& Dd & Dm & vcvt_59_fbits_built
{ Dd = FPToFixed(Dm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }
vcvt_59_64_dt: ".f32.s32" vcvt_59_64_dt: ".f32.s32"
is ((TMode=0 & c0808=0 & c2424=0) is ((TMode=0 & c0809=2 & c2424=0)
| (TMode=1 & thv_c0808=0 & thv_c2828=0)) | (TMode=1 & thv_c0809=2 & thv_c2828=0))
& Qd & Qm & vcvt_59_fbits_built & Qd & Qm & vcvt_59_fbits_built
{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); } { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }
vcvt_59_64_dt: ".f32.u32" vcvt_59_64_dt: ".f32.u32"
is ((TMode=0 & c0808=0 & c2424=1) is ((TMode=0 & c0809=2 & c2424=1)
| (TMode=1 & thv_c0808=0 & thv_c2828=1)) | (TMode=1 & thv_c0809=2 & thv_c2828=1))
& Qd & Qm & vcvt_59_fbits_built & Qd & Qm & vcvt_59_fbits_built
{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); } { Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }
vcvt_59_64_dt: ".s32.f32" vcvt_59_64_dt: ".s32.f32"
is ((TMode=0 & c0808=1 & c2424=0) is ((TMode=0 & c0809=3 & c2424=0)
| (TMode=1 & thv_c0808=1 & thv_c2828=0)) | (TMode=1 & thv_c0809=3 & thv_c2828=0))
& Qd & Qm & vcvt_59_fbits_built & Qd & Qm & vcvt_59_fbits_built
{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); } { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }
vcvt_59_64_dt: ".u32.f32" vcvt_59_64_dt: ".u32.f32"
is ((TMode=0 & c0808=1 & c2424=1) is ((TMode=0 & c0809=3 & c2424=1)
| (TMode=1 & thv_c0808=1 & thv_c2828=1)) | (TMode=1 & thv_c0809=3 & thv_c2828=1))
& Qd & Qm & vcvt_59_fbits_built
{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }
vcvt_59_64_dt: ".f16.s16"
is ((TMode=0 & c0809=0 & c2424=0)
| (TMode=1 & thv_c0809=0 & thv_c2828=0))
& Qd & Qm & vcvt_59_fbits_built
{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_TIEEVEN)); }
vcvt_59_64_dt: ".f16.u16"
is ((TMode=0 & c0809=0 & c2424=1)
| (TMode=1 & thv_c0809=0 & thv_c2828=1))
& Qd & Qm & vcvt_59_fbits_built
{ Qd = FixedToFP(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_TIEEVEN)); }
vcvt_59_64_dt: ".s16.f16"
is ((TMode=0 & c0809=1 & c2424=0)
| (TMode=1 & thv_c0809=1 & thv_c2828=0))
& Qd & Qm & vcvt_59_fbits_built
{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 0:1, $(FPRounding_ZERO)); }
vcvt_59_64_dt: ".u16.f16"
is ((TMode=0 & c0809=1 & c2424=1)
| (TMode=1 & thv_c0809=1 & thv_c2828=1))
& Qd & Qm & vcvt_59_fbits_built & Qd & Qm & vcvt_59_fbits_built
{ Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); } { Qd = FPToFixed(Qm, 32:1, 32:1, vcvt_59_fbits_built, 1:1, $(FPRounding_ZERO)); }
@ -622,15 +662,15 @@ vcvt_59_64_dt: ".u32.f32"
# F6.1.63 p8012 A1 Q = 0 (c0606) # F6.1.63 p8012 A1 Q = 0 (c0606)
:vcvt^vcvt_59_32_dt Dd,Dm,vcvt_59_fbits :vcvt^vcvt_59_32_dt Dd,Dm,vcvt_59_fbits
is ((TMode=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c0911=0b111 & c0707=0 & c0404=1 & c0606=0) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=0)
| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c0911=0b111 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0)) | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=0))
& vcvt_59_32_dt & vcvt_59_fbits & Dd & Dm & vcvt_59_32_dt & vcvt_59_fbits & Dd & Dm
unimpl unimpl
# F6.1.63 p8012 A1 Q = 1 (c0606) # F6.1.63 p8012 A1 Q = 1 (c0606)
:vcvt^vcvt_59_64_dt Qd,Qm,vcvt_59_fbits :vcvt^vcvt_59_64_dt Qd,Qm,vcvt_59_fbits
is ((TMode=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c0911=0b111 & c0707=0 & c0404=1 & c0606=1) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2527=0b001 & c2323=1 & c2121=1 & c1011=0b11 & c0707=0 & c0404=1 & c0606=1)
| (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c0911=0b111 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1)) | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & thv_c2121=1 & thv_c1011=0b11 & thv_c0707=0 & thv_c0404=1 & thv_c0606=1))
& vcvt_59_64_dt & vcvt_59_fbits & Qd & Qm & vcvt_59_64_dt & vcvt_59_fbits & Qd & Qm
unimpl unimpl
@ -771,14 +811,14 @@ vcvt_amnp_simd_128_dt: ".u32" is TMode=1 & thv_c0707=1 & thv_c0809 & vcvt_amnp_s
# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 64-bit SIMD vector variant Q = 0 (c0606) # F6.1.65,69,71,73 p8019,8028,8032,8036 A1 64-bit SIMD vector variant Q = 0 (c0606)
:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_64_dt^".f32" Dd,Dm :vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_64_dt^".f32" Dd,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=0)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=0)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=0))
& vcvt_amnp_simd_RM & vcvt_amnp_simd_64_dt & Dd & Dm & vcvt_amnp_simd_RM & vcvt_amnp_simd_64_dt & Dd & Dm
unimpl unimpl
# F6.1.65,69,71,73 p8019,8028,8032,8036 A1 128-bit SIMD vector variant Q = 1(c0606) # F6.1.65,69,71,73 p8019,8028,8032,8036 A1 128-bit SIMD vector variant Q = 1(c0606)
:vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_128_dt^".f32" Qd,Qm :vcvt^vcvt_amnp_simd_RM^vcvt_amnp_simd_128_dt^".f32" Qd,Qm
is ((TMode=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00111 & c2021=0b11 & c1819=0b10 & c1617=0b11 & c1011=0b00 & c0404=0 & c0606=1)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=1)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11111 & thv_c2021=0b11 & thv_c1819=0b10 & thv_c1617=0b11 & thv_c1011=0b00 & thv_c0404=0 & thv_c0606=1))
& vcvt_amnp_simd_RM & vcvt_amnp_simd_128_dt & Qd & Qm & vcvt_amnp_simd_RM & vcvt_amnp_simd_128_dt & Qd & Qm
unimpl unimpl
@ -810,16 +850,23 @@ vcvt_amnp_fp_d_dt: ".u32" is TMode=1 & thv_c0707=0 & thv_c1617 & vcvt_amnp_fp_RM
vcvt_amnp_fp_d_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } vcvt_amnp_fp_d_dt: ".s32" is TMode=0 & c0707=1 & c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }
vcvt_amnp_fp_d_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); } vcvt_amnp_fp_d_dt: ".s32" is TMode=1 & thv_c0707=1 & thv_c1617 & vcvt_amnp_fp_RM & Sd & Dm { Sd = FPToFixed(Dm, 64:1, 32:1, 0:1, 0:1, vcvt_amnp_fp_RM); }
# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 01 (c0809)
:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f16" Sd,Sm
is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01))
& vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm
unimpl
# F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 11 (c0809) # F6.1.66,70,72,74 p8021,8030,8034,8038 Single-precision scalar variant size = 11 (c0809)
:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f32" Sd,Sm :vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_s_dt^".f32" Sd,Sm
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))
& vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm & vcvt_amnp_fp_RM & vcvt_amnp_fp_s_dt & Sd & Sm
unimpl unimpl
# F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 10 (c0809) # F6.1.66,70,72,74 p8021,8030,8034,8038 Double-precision scalar variant size = 11 (c0809)
:vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_d_dt^".f64" Sd,Dm :vcvt^vcvt_amnp_fp_RM^vcvt_amnp_fp_d_dt^".f64" Sd,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b11 & c1819=0b11 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b11 & thv_c1819=0b11 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))
& vcvt_amnp_fp_RM & vcvt_amnp_fp_d_dt & Sd & Dm & vcvt_amnp_fp_RM & vcvt_amnp_fp_d_dt & Sd & Dm
unimpl unimpl
@ -950,98 +997,98 @@ define pcodeop FPMinNum;
# F6.1.117 p8178 A1/T1 Q = 0 (c0606) # F6.1.117 p8178 A1/T1 Q = 0 (c0606)
:vmaxnm^".f32" Dd,Dn,Dm :vmaxnm^".f32" Dd,Dn,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=0)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
& Dd & Dn & Dm & Dd & Dn & Dm
{ Dd = FPMaxNum(Dn, Dm); } { Dd = FPMaxNum(Dn, Dm); }
# F6.1.117 p8178 A1/T1 Q = 1 (c0606) # F6.1.117 p8178 A1/T1 Q = 1 (c0606)
:vmaxnm^".f32" Qd,Qn,Qm :vmaxnm^".f32" Qd,Qn,Qm
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b00 & c0811=0b1111 & c0404=1 & c0606=1)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b00 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
& Qd & Qn & Qm & Qd & Qn & Qm
{ Qd = FPMaxNum(Qn, Qm); } { Qd = FPMaxNum(Qn, Qm); }
# F6.1.117 p8178 A1/T1 Q = 0 (c0606) # F6.1.117 p8178 A1/T1 Q = 0 (c0606)
:vmaxnm^".f16" Dd,Dn,Dm :vmaxnm^".f16" Dd,Dn,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=0)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
& Dd & Dn & Dm & Dd & Dn & Dm
{ Dd = FPMaxNum(Dn, Dm); } { Dd = FPMaxNum(Dn, Dm); }
# F6.1.117 p8178 A1/T1 Q = 1 (c0606) # F6.1.117 p8178 A1/T1 Q = 1 (c0606)
:vmaxnm^".f16" Qd,Qn,Qm :vmaxnm^".f16" Qd,Qn,Qm
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b01 & c0811=0b1111 & c0404=1 & c0606=1)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b01 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
& Qd & Qn & Qm & Qd & Qn & Qm
{ Qd = FPMaxNum(Qn, Qm); } { Qd = FPMaxNum(Qn, Qm); }
# F6.1.117 p8178 A2/T2 size = 01 (c0809) # F6.1.117 p8178 A2/T2 size = 01 (c0809)
:vmaxnm^".f16" Sd,Sn,Sm :vmaxnm^".f16" Sd,Sn,Sm
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b01)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b01)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b01))
& Sd & Sn & Sm & Sd & Sn & Sm
{ Sd = FPMaxNum(Sn, Sm); } { Sd = FPMaxNum(Sn, Sm); }
# F6.1.117 p8178 A2/T2 size = 10 (c0809) # F6.1.117 p8178 A2/T2 size = 10 (c0809)
:vmaxnm^".f32" Sd,Sn,Sm :vmaxnm^".f32" Sd,Sn,Sm
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10))
& Sd & Sn & Sm & Sd & Sn & Sm
{ Sd = FPMaxNum(Sn, Sm); } { Sd = FPMaxNum(Sn, Sm); }
# F6.1.117 p8178 A2/T2 size = 11 (c0809) # F6.1.117 p8178 A2/T2 size = 11 (c0809)
:vmaxnm^".f64" Dd,Dn,Dm :vmaxnm^".f64" Dd,Dn,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11))
& Dd & Dn & Dm & Dd & Dn & Dm
{ Dd = FPMaxNum(Dn, Dm); } { Dd = FPMaxNum(Dn, Dm); }
# F6.1.120 p8178 A1/T1 Q = 0 (c0606) # F6.1.120 p8178 A1/T1 Q = 0 (c0606)
:vminnm^".f32" Dd,Dn,Dm :vminnm^".f32" Dd,Dn,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=0)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
& Dd & Dn & Dm & Dd & Dn & Dm
{ Dd = FPMinNum(Dn, Dm); } { Dd = FPMinNum(Dn, Dm); }
# F6.1.120 p8178 A1/T1 Q = 1 (c0606) # F6.1.120 p8178 A1/T1 Q = 1 (c0606)
:vminnm^".f32" Qd,Qn,Qm :vminnm^".f32" Qd,Qn,Qm
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b10 & c0811=0b1111 & c0404=1 & c0606=1)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b10 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
& Qd & Qn & Qm & Qd & Qn & Qm
{ Qd = FPMinNum(Qn, Qm); } { Qd = FPMinNum(Qn, Qm); }
# F6.1.120 p8178 A1/T1 Q = 0 (c0606) # F6.1.120 p8178 A1/T1 Q = 0 (c0606)
:vminnm^".f16" Dd,Dn,Dm :vminnm^".f16" Dd,Dn,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=0)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=0))
& Dd & Dn & Dm & Dd & Dn & Dm
{ Dd = FPMinNum(Dn, Dm); } { Dd = FPMinNum(Dn, Dm); }
# F6.1.120 p8178 A1/T1 Q = 1 (c0606) # F6.1.120 p8178 A1/T1 Q = 1 (c0606)
:vminnm^".f16" Qd,Qn,Qm :vminnm^".f16" Qd,Qn,Qm
is ((TMode=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b00110 & c2021=0b11 & c0811=0b1111 & c0404=1 & c0606=1)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11110 & thv_c2021=0b11 & thv_c0811=0b1111 & thv_c0404=1 & thv_c0606=1))
& Qd & Qn & Qm & Qd & Qn & Qm
{ Qd = FPMinNum(Qn, Qm); } { Qd = FPMinNum(Qn, Qm); }
# F6.1.120 p8178 A2/T2 size = 01 (c0809) # F6.1.120 p8178 A2/T2 size = 01 (c0809)
:vminnm^".f16" Sd,Sn,Sm :vminnm^".f16" Sd,Sn,Sm
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b01)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b01))
& Sd & Sn & Sm & Sd & Sn & Sm
{ Sd = FPMinNum(Sn, Sm); } { Sd = FPMinNum(Sn, Sm); }
# F6.1.120 p8178 A2/T2 size = 10 (c0809) # F6.1.120 p8178 A2/T2 size = 10 (c0809)
:vminnm^".f32" Sd,Sn,Sm :vminnm^".f32" Sd,Sn,Sm
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b10)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b10))
& Sd & Sn & Sm & Sd & Sn & Sm
{ Sd = FPMinNum(Sn, Sm); } { Sd = FPMinNum(Sn, Sm); }
# F6.1.120 p8178 A2/T2 size = 11 (c0809) # F6.1.120 p8178 A2/T2 size = 11 (c0809)
:vminnm^".f64" Dd,Dn,Dm :vminnm^".f64" Dd,Dn,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11101 & c2021=0b00 & c1011=0b10 & c0606=1 & c0404=0 & c0809=0b11)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11101 & thv_c2021=0b00 & thv_c1011=0b10 & thv_c0606=1 & thv_c0404=0 & thv_c0809=0b11))
& Dd & Dn & Dm & Dd & Dn & Dm
{ Dd = FPMinNum(Dn, Dm); } { Dd = FPMinNum(Dn, Dm); }
@ -1091,15 +1138,15 @@ vmull_dt: ".p64"
# F6.1.149 p8266 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01) # F6.1.149 p8266 VMULL (-integer and +polynomial) op=1 (c0909) (with condition U!=1 and size!=0b11 and size!=01)
:vmull^vmull_dt Qd,Dn,Dm :vmull^vmull_dt Qd,Dn,Dm
is ((TMode=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1) is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2424=0 & c2323=1 & ( c2121 & c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=1)
| (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1)) | (TMode=1 & thv_c2931=0b111 & thv_c2828=0 & thv_c2327=0b11111 & (thv_c2121 & thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=1))
& vmull_dt & Qd & Dn & Dm & vmull_dt & Qd & Dn & Dm
{ Qd = PolynomialMult(Dn, Dm); } { Qd = PolynomialMult(Dn, Dm); }
# F6.1.149 p8266 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11) # F6.1.149 p8266 VMULL (+integer and -polynomial) op=0 (c0909) (with condition size!=0b11)
:vmull^vmull_dt Qd,Dn,Dm :vmull^vmull_dt Qd,Dn,Dm
is ((TMode=0 & c2531=0b1111001 & c2424 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0) is ((TMode=0 & ARMcond=0 & c2531=0b1111001 & c2323=1 & ( c2121=0 | c2020=0) & c1011=0b11 & c0808=0 & c0606=0 & c0404=0 & c0909=0)
| (TMode=1 & thv_c2931=0b111 & thv_c2828 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0)) | (TMode=1 & thv_c2931=0b111 & thv_c2327=0b11111 & (thv_c2121=0 | thv_c2020=0) & thv_c1011=0b11 & thv_c0808=0 & thv_c0606=0 & thv_c0404=0 & thv_c0909=0))
& vmull_dt & Qd & Dn & Dm & vmull_dt & Qd & Dn & Dm
{ Qd = VectorMultiply(Dn, Dm); } { Qd = VectorMultiply(Dn, Dm); }
@ -1201,14 +1248,14 @@ vrint_fp_RM: "p"
# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 10 (c0809) # F6.1.200,202,204,206 p8398,8402,8406,8410 size = 10 (c0809)
:vrint^vrint_fp_RM^".f32" Sd,Sm :vrint^vrint_fp_RM^".f32" Sd,Sm
is ((TMode=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10) is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b10)
| (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b10)) | (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b10))
& vrint_fp_RM & Sd & Sm & vrint_fp_RM & Sd & Sm
{ Sd = FPRoundInt(Sm, 32:1, vrint_fp_RM, 0:1); } { Sd = FPRoundInt(Sm, 32:1, vrint_fp_RM, 0:1); }
# F6.1.200,202,204,206 p8398,8402,8406,8410 size = 11 (c0809) # F6.1.200,202,204,206 p8398,8402,8406,8410 size = 11 (c0809)
:vrint^vrint_fp_RM^".f64" Dd,Dm :vrint^vrint_fp_RM^".f64" Dd,Dm
is ((TMode=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11) is ((TMode=0 & ARMcond=0 & c2331=0b111111101 & c1821=0b1110 & c1011=0b10 & c0607=0b01 & c0404=0 & c0809=0b11)
| (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b11)) | (TMode=1 & thv_c2331=0b111111101 & thv_c1821=0b1110 & thv_c1011=0b10 & thv_c0607=0b01 & thv_c0404=0 & thv_c0809=0b11))
& vrint_fp_RM & Dd & Dm & vrint_fp_RM & Dd & Dm
{ Dd = FPRoundInt(Dm, 32:1, vrint_fp_RM, 0:1); } { Dd = FPRoundInt(Dm, 32:1, vrint_fp_RM, 0:1); }
@ -1286,14 +1333,14 @@ vselcond: "vs"
# F6.1.223 p8447 A1/T1 size = 11 doubleprec (c0809) # F6.1.223 p8447 A1/T1 size = 11 doubleprec (c0809)
:vsel^vselcond^".f64" Dd,Dn,Dm :vsel^vselcond^".f64" Dd,Dn,Dm
is ((TMode=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b11)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b11))
& vselcond & Dn & Dd & Dm & vselcond & Dn & Dd & Dm
{ Dd = zext(vselcond != 0) * Dn + zext(vselcond == 0) * Dm; } { Dd = zext(vselcond != 0) * Dn + zext(vselcond == 0) * Dm; }
# F6.1.223 p8447 A1/T1 size = 10 singleprec (c0809) # F6.1.223 p8447 A1/T1 size = 10 singleprec (c0809)
:vsel^vselcond".f32" Sd,Sn,Sm :vsel^vselcond".f32" Sd,Sn,Sm
is ((TMode=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10) is ((TMode=0 & ARMcond=0 & c2831=0b1111 & c2327=0b11100 & c1011=0b10 & c0606=0 & c0404=0 & c0809=0b10)
| (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10)) | (TMode=1 & thv_c2831=0b1111 & thv_c2327=0b11100 & thv_c1011=0b10 & thv_c0606=0 & thv_c0404=0 & thv_c0809=0b10))
& vselcond & Sn & Sd & Sm & vselcond & Sn & Sd & Sm
{ Sd = zext(vselcond != 0) * Sn + zext(vselcond == 0) * Sm; } { Sd = zext(vselcond != 0) * Sn + zext(vselcond == 0) * Sm; }

2
Ghidra/Processors/MIPS/certification.manifest
View file

@ -13,8 +13,10 @@ data/languages/mips32R6le.slaspec||GHIDRA||||END|
data/languages/mips32_fp64.cspec||GHIDRA||||END| data/languages/mips32_fp64.cspec||GHIDRA||||END|
data/languages/mips32be.cspec||GHIDRA||||END| data/languages/mips32be.cspec||GHIDRA||||END|
data/languages/mips32be.slaspec||GHIDRA||||END| data/languages/mips32be.slaspec||GHIDRA||||END|
data/languages/mips32be_eabi.cspec||GHIDRA||||END|
data/languages/mips32le.cspec||GHIDRA||||END| data/languages/mips32le.cspec||GHIDRA||||END|
data/languages/mips32le.slaspec||GHIDRA||||END| data/languages/mips32le.slaspec||GHIDRA||||END|
data/languages/mips32le_eabi.cspec||GHIDRA||||END|
data/languages/mips32micro.pspec||GHIDRA||||END| data/languages/mips32micro.pspec||GHIDRA||||END|
data/languages/mips64.cspec||GHIDRA||||END| data/languages/mips64.cspec||GHIDRA||||END|
data/languages/mips64.pspec||GHIDRA||||END| data/languages/mips64.pspec||GHIDRA||||END|

29
Ghidra/Processors/MIPS/data/languages/MIPS.opinion
View file

@ -98,10 +98,19 @@ Elf e_flags are used for the secondary attribute, the following are pulled from
<constraint primary="8,10" processor="MIPS" size="32" variant="default" <constraint primary="8,10" processor="MIPS" size="32" variant="default"
secondary= "0b 01.1 ..00 .... .... 00.1 0.0. 0000 ...."/> secondary= "0b 01.1 ..00 .... .... 00.1 0.0. 0000 ...."/>
<!-- MIPS32-R1 and -R2, with microMIPS, don't cares: MDMX, EABI, FPU --> <!-- MIPS32-R1 and -R2, don't cares: MDMX, MIPS16e, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="default" compilerSpecID="eabi"
secondary= "0b 01.1 ..00 .... .... 0011 0.0. 0000 ...."/>
<!-- MIPS32-R1 and -R2, with microMIPS, don't cares: MDMX, EABI, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="micro" <constraint primary="8,10" processor="MIPS" size="32" variant="micro"
secondary= "0b 0111 .010 .... .... 00.1 0.0. 0000 ...."/> secondary= "0b 0111 .010 .... .... 00.1 0.0. 0000 ...."/>
<!-- MIPS32-R1 and -R2, with microMIPS, don't cares: MDMX, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="micro" compilerSpecID="eabi"
secondary= "0b 0111 .010 .... .... 0011 0.0. 0000 ...."/>
<!-- MIPS64 Pre-Release 6 --> <!-- MIPS64 Pre-Release 6 -->
<!-- MIPS64-R1 with 32-bit addresses, don't cares: MDMX, MIPS16e, EABI, FPU --> <!-- MIPS64-R1 with 32-bit addresses, don't cares: MDMX, MIPS16e, EABI, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr" <constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr"
@ -113,7 +122,23 @@ Elf e_flags are used for the secondary attribute, the following are pulled from
<!-- MIPS64-R2 with 32-bit addresses, don't cares: MDMX, MIPS16e, EABI, FPU --> <!-- MIPS64-R2 with 32-bit addresses, don't cares: MDMX, MIPS16e, EABI, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr" <constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr"
secondary= "0b 1000 ..00 .... .... 0... 0.0. 00.0 ...."/> secondary= "0b 1000 ..00 .... .... 0... 0.0. 0000 ...."/>
<!-- MIPS64-R2 with 32-bit addresses, n32 don't cares: MDMX, MIPS16e, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr" compilerSpecID="n32"
secondary= "0b 1000 ..00 .... .... 0... 0.0. 0010 ...."/>
<!-- MIPS64-R2 with 32-bit addresses, o32 don't cares: MDMX, MIPS16e, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr" compilerSpecID="o32"
secondary= "0b 1000 ..00 .... .... 0.01 0.0. 0000 ...."/>
<!-- MIPS64-R2 with 32-bit addresses, o64 don't cares: MDMX, MIPS16e, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr" compilerSpecID="o64"
secondary= "0b 1000 ..00 .... .... 0.10 0.0. 0000 ...."/>
<!-- MIPS64-R2 with 32-bit addresses, eabi don't cares: MDMX, MIPS16e, FPU -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr" compilerSpecID="eabi"
secondary= "0b 1000 ..00 .... .... 0.11 0.0. 0000 ...."/>
<!-- MIPS64-R2 with 32-bit addresses and with micromips --> <!-- MIPS64-R2 with 32-bit addresses and with micromips -->
<constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr-micro" <constraint primary="8,10" processor="MIPS" size="32" variant="64-32addr-micro"

2
Ghidra/Processors/MIPS/data/languages/mips.ldefs
View file

@ -12,6 +12,7 @@
<description>MIPS32 32-bit addresses, big endian, with mips16e</description> <description>MIPS32 32-bit addresses, big endian, with mips16e</description>
<compiler name="default" spec="mips32be.cspec" id="default"/> <compiler name="default" spec="mips32be.cspec" id="default"/>
<compiler name="Visual Studio" spec="mips32be.cspec" id="windows"/> <compiler name="Visual Studio" spec="mips32be.cspec" id="windows"/>
<compiler name="eabi" spec="mips32be_eabi.cspec" id="eabi"/>
<external_name tool="gnu" name="mips:4000"/> <external_name tool="gnu" name="mips:4000"/>
<external_name tool="IDA-PRO" name="mipsb"/> <external_name tool="IDA-PRO" name="mipsb"/>
<external_name tool="DWARF.register.mapping.file" name="mips.dwarf"/> <external_name tool="DWARF.register.mapping.file" name="mips.dwarf"/>
@ -28,6 +29,7 @@
<description>MIPS32 32-bit addresses, little endian, with mips16e</description> <description>MIPS32 32-bit addresses, little endian, with mips16e</description>
<compiler name="default" spec="mips32le.cspec" id="default"/> <compiler name="default" spec="mips32le.cspec" id="default"/>
<compiler name="Visual Studio" spec="mips32le.cspec" id="windows"/> <compiler name="Visual Studio" spec="mips32le.cspec" id="windows"/>
<compiler name="eabi" spec="mips32le_eabi.cspec" id="eabi"/>
<external_name tool="gnu" name="mips:4000"/> <external_name tool="gnu" name="mips:4000"/>
<external_name tool="IDA-PRO" name="mipsl"/> <external_name tool="IDA-PRO" name="mipsl"/>
<external_name tool="DWARF.register.mapping.file" name="mips.dwarf"/> <external_name tool="DWARF.register.mapping.file" name="mips.dwarf"/>

125
Ghidra/Processors/MIPS/data/languages/mips32be_eabi.cspec Normal file
View file

@ -0,0 +1,125 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<pointer_size value="4"/>
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>
<returnaddress>
<register name="ra"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="f12_13"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="f14_15"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="f16_17"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="f18_19"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="t0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="t1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="t2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="t3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="f0_1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="v0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="v0" piece2="v1"/>
</pentry>
</output>
<unaffected>
<register name="s0"/>
<register name="s1"/>
<register name="s2"/>
<register name="s3"/>
<register name="s4"/>
<register name="s5"/>
<register name="s6"/>
<register name="s7"/>
<register name="s8"/>
<register name="sp"/>
<register name="gp"/>
<register name="f20"/>
<register name="f22"/>
<register name="f24"/>
<register name="f26"/>
<register name="f28"/>
<register name="f30"/>
</unaffected>
<killedbycall>
<register name="at"/>
<register name="a0"/>
<register name="a1"/>
<register name="a2"/>
<register name="a3"/>
<register name="t0"/>
<register name="t1"/>
<register name="t2"/>
<register name="t3"/>
<register name="t4"/>
<register name="t5"/>
<register name="t6"/>
<register name="t7"/>
<register name="t8"/>
<register name="t9"/>
</killedbycall>
<localrange>
<range space="stack" first="0xfff0bdc0" last="0xffffffff"/>
<range space="stack" first="0" last="15"/> <!-- This is backup storage space for register params, but we treat as locals -->
</localrange>
</prototype>
</default_proto>
</compiler_spec>

125
Ghidra/Processors/MIPS/data/languages/mips32le_eabi.cspec Normal file
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@ -0,0 +1,125 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<pointer_size value="4"/>
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>
<returnaddress>
<register name="ra"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="f12_13"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="f14_15"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="f16_17"/>
</pentry>
<pentry minsize="4" maxsize="8" metatype="float">
<register name="f18_19"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="t0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="t1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="t2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="t3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="f0_1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="v0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="v1" piece2="v0"/>
</pentry>
</output>
<unaffected>
<register name="s0"/>
<register name="s1"/>
<register name="s2"/>
<register name="s3"/>
<register name="s4"/>
<register name="s5"/>
<register name="s6"/>
<register name="s7"/>
<register name="s8"/>
<register name="sp"/>
<register name="gp"/>
<register name="f20"/>
<register name="f22"/>
<register name="f24"/>
<register name="f26"/>
<register name="f28"/>
<register name="f30"/>
</unaffected>
<killedbycall>
<register name="at"/>
<register name="a0"/>
<register name="a1"/>
<register name="a2"/>
<register name="a3"/>
<register name="t0"/>
<register name="t1"/>
<register name="t2"/>
<register name="t3"/>
<register name="t4"/>
<register name="t5"/>
<register name="t6"/>
<register name="t7"/>
<register name="t8"/>
<register name="t9"/>
</killedbycall>
<localrange>
<range space="stack" first="0xfff0bdc0" last="0xffffffff"/>
<range space="stack" first="0" last="15"/> <!-- This is backup storage space for register params, but we treat as locals -->
</localrange>
</prototype>
</default_proto>
</compiler_spec>