From 53d7e1608f5aeb680c53a08cf2a28ff932df5f19 Mon Sep 17 00:00:00 2001
From: MetalliC <0vetal0@gmail.com>
Date: Fri, 23 May 2025 15:03:55 +0300
Subject: [PATCH 1/3] SuperH4: fix fpu registers order

---
 .../SuperH4/data/languages/SuperH4_le.cspec          | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.cspec b/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.cspec
index 92dc5b39e1..899305783e 100644
--- a/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.cspec
+++ b/Ghidra/Processors/SuperH4/data/languages/SuperH4_le.cspec
@@ -29,30 +29,30 @@
   <default_proto>
     <prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
     <input>
-      <pentry minsize="1" maxsize="4" metatype="float">
-        <register name="fr5"/>
-      </pentry>
       <pentry minsize="1" maxsize="4" metatype="float">
         <register name="fr4"/>
       </pentry>
       <pentry minsize="1" maxsize="4" metatype="float">
-        <register name="fr7"/>
+        <register name="fr5"/>
       </pentry>
       <pentry minsize="1" maxsize="4" metatype="float">
         <register name="fr6"/>
       </pentry>
       <pentry minsize="1" maxsize="4" metatype="float">
-        <register name="fr9"/>
+        <register name="fr7"/>
       </pentry>
       <pentry minsize="1" maxsize="4" metatype="float">
         <register name="fr8"/>
       </pentry>
       <pentry minsize="1" maxsize="4" metatype="float">
-        <register name="fr11"/>
+        <register name="fr9"/>
       </pentry>
       <pentry minsize="1" maxsize="4" metatype="float">
         <register name="fr10"/>
       </pentry>
+      <pentry minsize="1" maxsize="4" metatype="float">
+        <register name="fr11"/>
+      </pentry>
       <pentry minsize="5" maxsize="8" metatype="float">
         <register name="dr4"/>
       </pentry>

From 24c0699a38246fea7e32900d54d2cfa3ae42358a Mon Sep 17 00:00:00 2001
From: MetalliC <0vetal0@gmail.com>
Date: Fri, 23 May 2025 15:08:01 +0300
Subject: [PATCH 2/3] SuperH4: fix FSCA opcode destination location

---
 Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc b/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
index 372fe95b8d..f584afbd8f 100644
--- a/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
+++ b/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
@@ -346,9 +346,9 @@ define token instr(16)
 	N_1   = ( 9,11) # register id
 	N_2   = (10,11) # register id
 	FRN_0 = ( 8,11) # float register id
-        FRN_1 = ( 8,10) # float register id
-        FRN_2 = ( 8,10) # float register id
-        DRN_0 = ( 8,10) # double register id
+        FRN_1 = ( 9,11) # float register id
+        FRN_2 = ( 9,11) # float register id
+        DRN_0 = ( 9,11) # double register id
 	DRN_1 = ( 9,11) # double register id
 	XDN_1 = ( 9,11) # double register id
 	XDRN  = ( 8,11) # float register id

From 997c64f6db8bc50c4f02f15a29d88f02a2dfeadc Mon Sep 17 00:00:00 2001
From: ghidorahrex <ghidorahrex@users.noreply.github.com>
Date: Mon, 16 Jun 2025 14:29:10 +0000
Subject: [PATCH 3/3] GP-5759: Fixed token piece formatting

---
 Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc b/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
index f584afbd8f..1b0e76cda8 100644
--- a/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
+++ b/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
@@ -346,9 +346,9 @@ define token instr(16)
 	N_1   = ( 9,11) # register id
 	N_2   = (10,11) # register id
 	FRN_0 = ( 8,11) # float register id
-        FRN_1 = ( 9,11) # float register id
-        FRN_2 = ( 9,11) # float register id
-        DRN_0 = ( 9,11) # double register id
+	FRN_1 = ( 9,11) # float register id
+	FRN_2 = ( 9,11) # float register id
+	DRN_0 = ( 9,11) # double register id
 	DRN_1 = ( 9,11) # double register id
 	XDN_1 = ( 9,11) # double register id
 	XDRN  = ( 8,11) # float register id