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GP-3524: Fixed ARM Thumb vdup instruction to use correct registers

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This commit is contained in:
ghidorahrex 2023-06-07 19:07:48 +00:00
parent be95714f86
commit 7a145a75e4
2 changed files with 11 additions and 11 deletions
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20
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
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@ -2507,24 +2507,24 @@ vdupSize2: 8 is c2222=1 & c0505=0 { }
vdupSize2: 16 is c2222=0 & c0505=1 { } vdupSize2: 16 is c2222=0 & c0505=1 { }
vdupSize2: 32 is c2222=0 & c0505=0 { } vdupSize2: 32 is c2222=0 & c0505=0 { }
vdupRd8: Rd is Rd & c2222=1 & c0505=0 vdupRd8: VRd is VRd & c2222=1 & c0505=0
{ {
val:8 = 0; val:8 = 0;
local tmpRd = Rd; local tmpRd = VRd;
replicate1to8(tmpRd:1, val); replicate1to8(tmpRd:1, val);
export val; export val;
} }
vdupRd8: Rd is Rd & c2222=0 & c0505=1 vdupRd8: VRd is VRd & c2222=0 & c0505=1
{ {
val:8 = 0; val:8 = 0;
local tmpRd = Rd; local tmpRd = VRd;
replicate2to8(tmpRd:2, val); replicate2to8(tmpRd:2, val);
export val; export val;
} }
vdupRd8: Rd is Rd & c2222=0 & c0505=0 vdupRd8: VRd is VRd & c2222=0 & c0505=0
{ {
val:8 = 0; val:8 = 0;
local tmpRd = Rd; local tmpRd = VRd;
replicate4to8(tmpRd:4, val); replicate4to8(tmpRd:4, val);
export val; export val;
} }
@ -2536,8 +2536,8 @@ vdupRd16: vdupRd8 is vdupRd8
export val; export val;
} }
:vdup^COND^"."^vdupSize2 Dn,vdupRd8 is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0004=0x10) | :vdup^COND^"."^vdupSize2 Dn,VRd is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=0 & c0811=11 & c0606=0 & c0004=0x10) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & COND & Dn & vdupSize2 & vdupRd8 ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=0 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & VRd & COND & Dn & vdupSize2 & vdupRd8
{ {
build COND; build COND;
build vdupRd8; build vdupRd8;
@ -2545,8 +2545,8 @@ vdupRd16: vdupRd8 is vdupRd8
Dn = vdupRd8; Dn = vdupRd8;
} }
:vdup^COND^"."^vdupSize2 Qn,vdupRd16 is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=2 & c0811=11 & c0606=0 & c0004=0x10) | :vdup^COND^"."^vdupSize2 Qn,VRd is (( $(AMODE) & ARMcond=1 & c2327=0x1d & c2021=2 & c0811=11 & c0606=0 & c0004=0x10) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & COND & Qn & vdupSize2 & vdupRd16 ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=11 & thv_c0606=0 & thv_c0004=0x10 ) ) & VRd & COND & Qn & vdupSize2 & vdupRd16
{ {
build COND; build COND;
build vdupRd16; build vdupRd16;