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https://github.com/NationalSecurityAgency/ghidra.git
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GP-2292: The Decompiler now supports simplification of more forms of
optimized modulo/remainder calculations
This commit is contained in:
caheckman
Ryan Kurtz
parent
a438a1e1ea
commit
7a2810a649
6 changed files with 688 additions and 2 deletions
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@ -5065,9 +5065,14 @@ void ActionDatabase::universalAction(Architecture *conf)
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actprop->addRule( new RuleDivTermAdd2("analysis") );
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actprop->addRule( new RuleDivOpt("analysis") );
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actprop->addRule( new RuleSignForm("analysis") );
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actprop->addRule( new RuleSignForm2("analysis") );
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actprop->addRule( new RuleSignDiv2("analysis") );
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actprop->addRule( new RuleDivChain("analysis") );
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actprop->addRule( new RuleSignNearMult("analysis") );
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actprop->addRule( new RuleModOpt("analysis") );
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actprop->addRule( new RuleSignMod2nOpt("analysis") );
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actprop->addRule( new RuleSignMod2nOpt2("analysis") );
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actprop->addRule( new RuleSignMod2Opt("analysis") );
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actprop->addRule( new RuleSwitchSingle("analysis") );
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actprop->addRule( new RuleCondNegate("analysis") );
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actprop->addRule( new RuleBoolNegate("analysis") );
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@ -2957,7 +2957,7 @@ int4 RuleMultiCollapse::applyOp(PcodeOp *op,Funcdata &data)
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else
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nofunc = true; // Unwritten cannot match by functional equal
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}
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else if (*defcopyr == *copyr) continue; // A matching branch
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else if (defcopyr == copyr) continue; // A matching branch
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else if ((defcopyr!=copyr)&&(!nofunc)&&functionalEquality(defcopyr,copyr)) {
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// Cannot match MULTIEQUAL by functional equality
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// if (nofunc) return 0; // Not allowed to match by func equal
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@ -6710,6 +6710,11 @@ int4 RuleSubRight::applyOp(PcodeOp *op,Funcdata &data)
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if (outvn->getSize() + c == a->getSize()) {
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// If SUB is "hi" lump the SUB and shift together
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d += lone->getIn(1)->getOffset();
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if (d >= a->getSize() * 8) {
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if (opc2 == CPUI_INT_RIGHT)
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return 0; // Result should have been 0
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d = a->getSize() * 8 - 1; // sign extraction
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}
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data.opUnlink(op);
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op = lone;
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data.opSetOpcode(op,CPUI_SUBPIECE);
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@ -6932,7 +6937,7 @@ int4 RuleSubNormal::applyOp(PcodeOp *op,Funcdata &data)
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return 1;
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}
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else
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k = insize-c-outsize; // Or we can shrunk the cut
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k = insize-c-outsize; // Or we can shrink the cut
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}
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// if n == k*8, then a shift is unnecessary
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@ -6943,6 +6948,11 @@ int4 RuleSubNormal::applyOp(PcodeOp *op,Funcdata &data)
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data.opSetInput(op,data.newConstant(4,c),1);
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return 1;
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}
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else if (n >= outsize * 8) {
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n = outsize * 8; // Can only shift so far
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if (opc == CPUI_INT_SRIGHT)
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n -= 1;
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}
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PcodeOp *newop = data.newOp(2,op->getAddr());
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data.opSetOpcode(newop,CPUI_SUBPIECE);
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@ -7570,6 +7580,59 @@ int4 RuleSignDiv2::applyOp(PcodeOp *op,Funcdata &data)
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return 1;
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}
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/// \class RuleDivChain
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/// \brief Collapse two consecutive divisions: `(x / c1) / c2 => x / (c1*c2)`
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void RuleDivChain::getOpList(vector<uint4> &oplist) const
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{
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oplist.push_back(CPUI_INT_DIV);
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oplist.push_back(CPUI_INT_SDIV);
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}
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int4 RuleDivChain::applyOp(PcodeOp *op,Funcdata &data)
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{
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OpCode opc2 = op->code();
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Varnode *constVn2 = op->getIn(1);
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if (!constVn2->isConstant()) return 0;
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Varnode *vn = op->getIn(0);
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if (!vn->isWritten()) return 0;
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PcodeOp *divOp = vn->getDef();
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OpCode opc1 = divOp->code();
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if (opc1 != opc2 && (opc2 != CPUI_INT_DIV || opc1 != CPUI_INT_RIGHT))
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return 0;
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Varnode *constVn1 = divOp->getIn(1);
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if (!constVn1->isConstant()) return 0;
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// If the intermediate result is being used elsewhere, don't apply
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// Its likely collapsing the divisions will interfere with the modulo rules
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if (vn->loneDescend() == (PcodeOp *)0) return 0;
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uintb val1;
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if (opc1 == opc2) {
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val1 = constVn1->getOffset();
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}
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else { // Unsigned case with INT_RIGHT
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int4 sa = constVn1->getOffset();
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val1 = 1;
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val1 <<= sa;
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}
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Varnode *baseVn = divOp->getIn(0);
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if (baseVn->isFree()) return 0;
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int4 sz = vn->getSize();
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uintb val2 = constVn2->getOffset();
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uintb resval = (val1 * val2) & calc_mask(sz);
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if (resval == 0) return 0;
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if (signbit_negative(val1, sz))
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val1 = (~val1 + 1) & calc_mask(sz);
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if (signbit_negative(val2, sz))
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val2 = (~val2 + 1) & calc_mask(sz);
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int4 bitcount = mostsigbit_set(val1) + mostsigbit_set(val2) + 2;
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if (opc2 == CPUI_INT_DIV && bitcount > sz * 8 ) return 0; // Unsigned overflow
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if (opc2 == CPUI_INT_SDIV && bitcount > sz * 8 - 2) return 0; // Signed overflow
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data.opSetInput(op, baseVn, 0);
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data.opSetInput(op,data.newConstant(sz, resval), 1);
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return 1;
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}
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/// \class RuleSignForm
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/// \brief Normalize sign extraction: `sub(sext(V),c) => V s>> 31`
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void RuleSignForm::getOpList(vector<uint4> &oplist) const
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@ -7601,6 +7664,63 @@ int4 RuleSignForm::applyOp(PcodeOp *op,Funcdata &data)
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return 1;
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}
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/// \class RuleSignForm2
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/// \brief Normalize sign extraction: `sub(sext(V) * small,c) s>> 31 => V s>> 31`
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///
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/// V and small must be small enough so that there is no overflow in the INT_MULT.
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/// The SUBPIECE must be extracting the high part of the INT_MULT.
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void RuleSignForm2::getOpList(vector<uint4> &oplist) const
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{
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oplist.push_back(CPUI_INT_SRIGHT);
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}
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int4 RuleSignForm2::applyOp(PcodeOp *op,Funcdata &data)
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{
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Varnode *constVn = op->getIn(1);
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if (!constVn->isConstant()) return 0;
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Varnode *inVn = op->getIn(0);
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int4 sizeout = inVn->getSize();
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if ((int4)constVn->getOffset() != sizeout*8 -1) return 0;
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if (!inVn->isWritten()) return 0;
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PcodeOp *subOp = inVn->getDef();
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if (subOp->code() != CPUI_SUBPIECE) return 0;
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int4 c = subOp->getIn(1)->getOffset();
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Varnode *multOut = subOp->getIn(0);
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int4 multSize = multOut->getSize();
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if (c + sizeout != multSize) return 0; // Must be extracting high part
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if (!multOut->isWritten()) return 0;
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PcodeOp *multOp = multOut->getDef();
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if (multOp->code() != CPUI_INT_MULT) return 0;
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int4 slot;
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PcodeOp *sextOp;
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for(slot=0;slot<2;++slot) { // Search for the INT_SEXT
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Varnode *vn = multOp->getIn(slot);
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if (!vn->isWritten()) continue;
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sextOp = vn->getDef();
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if (sextOp->code() == CPUI_INT_SEXT) break;
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}
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if (slot > 1) return 0;
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Varnode *a = sextOp->getIn(0);
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if (a->isFree() || a->getSize() != sizeout) return 0;
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Varnode *otherVn = multOp->getIn(1-slot);
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// otherVn must be a positive integer and small enough so the INT_MULT can't overflow into the sign-bit
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if (otherVn->isConstant()) {
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if (otherVn->getOffset() > calc_mask(sizeout)) return 0;
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if (2 * sizeout > multSize) return 0;
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}
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else if (otherVn->isWritten()) {
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PcodeOp *zextOp = otherVn->getDef();
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if (zextOp->code() != CPUI_INT_ZEXT) return 0;
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if (zextOp->getIn(0)->getSize() + sizeout > multSize) return 0;
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}
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else
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return 0;
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data.opSetInput(op, a, 0);
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return 0;
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}
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/// \class RuleSignNearMult
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/// \brief Simplify division form: `(V + (V s>> 0x1f)>>(32-n)) & (-1<<n) => (V s/ 2^n) * 2^n`
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void RuleSignNearMult::getOpList(vector<uint4> &oplist) const
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@ -7723,6 +7843,338 @@ int4 RuleModOpt::applyOp(PcodeOp *op,Funcdata &data)
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return 0;
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}
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/// \class RuleSignMod2nOpt
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/// \brief Convert INT_SREM forms: `(V + (sign >> (64-n)) & (2^n-1)) - (sign >> (64-n) => V s% 2^n`
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///
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/// Note: `sign = V s>> 63` The INT_AND may be performed on a truncated result and then reextended.
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void RuleSignMod2nOpt::getOpList(vector<uint4> &oplist) const
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{
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oplist.push_back(CPUI_INT_RIGHT);
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}
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int4 RuleSignMod2nOpt::applyOp(PcodeOp *op,Funcdata &data)
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{
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if (!op->getIn(1)->isConstant()) return 0;
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int4 shiftAmt = op->getIn(1)->getOffset();
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Varnode *a = checkSignExtraction(op->getIn(0));
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if (a == (Varnode *)0 || a->isFree()) return 0;
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Varnode *correctVn = op->getOut();
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int4 n = a->getSize() * 8 - shiftAmt;
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uintb mask = 1;
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mask = (mask << n) - 1;
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list<PcodeOp *>::const_iterator iter;
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for(iter=correctVn->beginDescend();iter!=correctVn->endDescend();++iter) {
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PcodeOp *multop = *iter;
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if (multop->code() != CPUI_INT_MULT) continue;
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Varnode *negone = multop->getIn(1);
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if (!negone->isConstant()) continue;
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if (negone->getOffset() != calc_mask(correctVn->getSize())) continue;
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PcodeOp *baseOp = multop->getOut()->loneDescend();
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if (baseOp == (PcodeOp *)0) continue;
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if (baseOp->code() != CPUI_INT_ADD) continue;
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int4 slot = 1 - baseOp->getSlot(multop->getOut());
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Varnode *andOut = baseOp->getIn(slot);
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if (!andOut->isWritten()) continue;
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PcodeOp *andOp = andOut->getDef();
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int4 truncSize = -1;
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if (andOp->code() == CPUI_INT_ZEXT) { // Look for intervening extension after INT_AND
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andOut = andOp->getIn(0);
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if (!andOut->isWritten()) continue;
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andOp = andOut->getDef();
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if (andOp->code() != CPUI_INT_AND) continue;
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truncSize = andOut->getSize(); // If so we have a truncated form
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}
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else if (andOp->code() != CPUI_INT_AND)
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continue;
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Varnode *constVn = andOp->getIn(1);
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if (!constVn->isConstant()) continue;
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if (constVn->getOffset() != mask) continue;
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Varnode *addOut = andOp->getIn(0);
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if (!addOut->isWritten()) continue;
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PcodeOp *addOp = addOut->getDef();
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if (addOp->code() != CPUI_INT_ADD) continue;
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// Search for "a" as one of the inputs to addOp
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int4 aSlot;
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for(aSlot=0;aSlot < 2;++aSlot) {
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Varnode *vn = addOp->getIn(aSlot);
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if (truncSize >= 0) {
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if (!vn->isWritten()) continue;
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PcodeOp *subOp = vn->getDef();
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if (subOp->code() != CPUI_SUBPIECE) continue;
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if (subOp->getIn(1)->getOffset() != 0) continue;
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vn = subOp->getIn(0);
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}
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if (a == vn) break;
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}
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if (aSlot > 1) continue;
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// Verify that the other input to addOp is an INT_RIGHT by shiftAmt
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Varnode *extVn = addOp->getIn(1-aSlot);
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if (!extVn->isWritten()) continue;
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PcodeOp *shiftOp = extVn->getDef();
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if (shiftOp->code() != CPUI_INT_RIGHT) continue;
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constVn = shiftOp->getIn(1);
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if (!constVn->isConstant()) continue;
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int4 shiftval = constVn->getOffset();
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if (truncSize >= 0)
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shiftval += (a->getSize() - truncSize) * 8;
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if (shiftval != shiftAmt) continue;
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// Verify that the input to INT_RIGHT is a sign extraction of "a"
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extVn = checkSignExtraction(shiftOp->getIn(0));
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if (extVn == (Varnode *)0) continue;
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if (truncSize >= 0) {
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if (!extVn->isWritten()) continue;
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PcodeOp *subOp = extVn->getDef();
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if (subOp->code() != CPUI_SUBPIECE) continue;
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if ((int4)subOp->getIn(1)->getOffset() != truncSize) continue;
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extVn = subOp->getIn(0);
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}
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if (a != extVn) continue;
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data.opSetOpcode(baseOp, CPUI_INT_SREM);
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data.opSetInput(baseOp, a, 0);
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data.opSetInput(baseOp, data.newConstant(a->getSize(), mask+1), 1);
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return 1;
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}
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return 0;
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}
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/// \brief Verify that the given Varnode is a sign extraction of the form `V s>> 63`
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///
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/// If not, null is returned. Otherwise the Varnode whose sign is extracted is returned.
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/// \param outVn is the given Varnode
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/// \return the Varnode being extracted or null
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Varnode *RuleSignMod2nOpt::checkSignExtraction(Varnode *outVn)
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{
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if (!outVn->isWritten()) return 0;
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PcodeOp *signOp = outVn->getDef();
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if (signOp->code() != CPUI_INT_SRIGHT)
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return (Varnode *)0;
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Varnode *constVn = signOp->getIn(1);
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if (!constVn->isConstant())
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return (Varnode *)0;
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int4 val = constVn->getOffset();
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Varnode *resVn = signOp->getIn(0);
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int4 insize = resVn->getSize();
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if (val != insize*8 - 1)
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return (Varnode *)0;
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return resVn;
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}
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/// \class RuleSignMod2Opt
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/// \brief Convert INT_SREM form: `(V - sign)&1 + sign => V s% 2`
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///
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/// Note: `sign = V s>> 63` The INT_AND may be performed on a truncated result and then reextended.
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/// This is a specialized form of RuleSignMod2nOpt.
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void RuleSignMod2Opt::getOpList(vector<uint4> &oplist) const
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{
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oplist.push_back(CPUI_INT_AND);
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}
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int4 RuleSignMod2Opt::applyOp(PcodeOp *op,Funcdata &data)
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{
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Varnode *constVn = op->getIn(1);
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if (!constVn->isConstant()) return 0;
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if (constVn->getOffset() != 1) return 0;
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Varnode *addOut = op->getIn(0);
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if (!addOut->isWritten()) return 0;
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PcodeOp *addOp = addOut->getDef();
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if (addOp->code() != CPUI_INT_ADD) return 0;
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int4 multSlot;
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PcodeOp *multOp;
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bool trunc = false;
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for(multSlot = 0;multSlot < 2;++multSlot) {
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Varnode *vn = addOp->getIn(multSlot);
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if (!vn->isWritten()) continue;
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multOp = vn->getDef();
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if (multOp->code() != CPUI_INT_MULT) continue;
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constVn = multOp->getIn(1);
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if (!constVn->isConstant()) continue;
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if (constVn->getOffset() == calc_mask(constVn->getSize())) break; // Check for INT_MULT by -1
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}
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if (multSlot > 1) return 0;
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Varnode *base = RuleSignMod2nOpt::checkSignExtraction(multOp->getIn(0));
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if (base == (Varnode *)0) return 0;
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Varnode *otherBase = addOp->getIn(1-multSlot);
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if (base != otherBase) {
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if (!base->isWritten() || !otherBase->isWritten()) return 0;
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PcodeOp *subOp = base->getDef();
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if (subOp->code() != CPUI_SUBPIECE) return 0;
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int4 truncAmt = subOp->getIn(1)->getOffset();
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if (truncAmt + base->getSize() != subOp->getIn(0)->getSize()) return 0; // Must truncate all but high part
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base = subOp->getIn(0);
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subOp = otherBase->getDef();
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if (subOp->code() != CPUI_SUBPIECE) return 0;
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if (subOp->getIn(1)->getOffset() != 0) return 0;
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otherBase = subOp->getIn(0);
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if (otherBase != base) return 0;
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trunc = true;
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}
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if (base->isFree()) return 0;
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Varnode *andOut = op->getOut();
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if (trunc) {
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PcodeOp *extOp = andOut->loneDescend();
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if (extOp == (PcodeOp *)0 || extOp->code() != CPUI_INT_ZEXT) return 0;
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andOut = extOp->getOut();
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}
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list<PcodeOp *>::const_iterator iter;
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for(iter=andOut->beginDescend();iter!=andOut->endDescend();++iter) {
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PcodeOp *rootOp = *iter;
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if (rootOp->code() != CPUI_INT_ADD) continue;
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int4 slot = rootOp->getSlot(andOut);
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otherBase = RuleSignMod2nOpt::checkSignExtraction(rootOp->getIn(1-slot));
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if (otherBase != base) continue;
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data.opSetOpcode(rootOp, CPUI_INT_SREM);
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data.opSetInput(rootOp,base,0);
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data.opSetInput(rootOp,data.newConstant(base->getSize(), 2),1);
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return 1;
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}
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return 0;
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}
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/// \class RuleSignMod2nOpt2
|
||||
/// \brief Convert INT_SREM form: `V - (Vadj & ~(2^n-1)) => V s% 2^n`
|
||||
///
|
||||
/// Note: `Vadj = (V<0) ? V + 2^n-1 : V`
|
||||
void RuleSignMod2nOpt2::getOpList(vector<uint4> &oplist) const
|
||||
|
||||
{
|
||||
oplist.push_back(CPUI_INT_MULT);
|
||||
}
|
||||
|
||||
int4 RuleSignMod2nOpt2::applyOp(PcodeOp *op,Funcdata &data)
|
||||
|
||||
{
|
||||
Varnode *constVn = op->getIn(1);
|
||||
if (!constVn->isConstant()) return 0;
|
||||
uintb mask = calc_mask(constVn->getSize());
|
||||
if (constVn->getOffset() != mask) return 0; // Must be INT_MULT by -1
|
||||
Varnode *andOut = op->getIn(0);
|
||||
if (!andOut->isWritten()) return 0;
|
||||
PcodeOp *andOp = andOut->getDef();
|
||||
if (andOp->code() != CPUI_INT_AND) return 0;
|
||||
constVn = andOp->getIn(1);
|
||||
if (!constVn->isConstant()) return 0;
|
||||
uintb npow = (~constVn->getOffset() + 1) & mask;
|
||||
if (popcount(npow) != 1) return 0; // constVn must be of form 11111..000..
|
||||
if (npow == 1) return 0;
|
||||
Varnode *adjVn = andOp->getIn(0);
|
||||
if (!adjVn->isWritten()) return 0;
|
||||
PcodeOp *adjOp = adjVn->getDef();
|
||||
Varnode *base;
|
||||
if (adjOp->code() == CPUI_INT_ADD) {
|
||||
if (npow != 2) return 0; // Special mod 2 form
|
||||
base = checkSignExtForm(adjOp);
|
||||
}
|
||||
else if (adjOp->code() == CPUI_MULTIEQUAL) {
|
||||
base = checkMultiequalForm(adjOp, npow);
|
||||
}
|
||||
else
|
||||
return 0;
|
||||
if (base == (Varnode *)0) return 0;
|
||||
if (base->isFree()) return 0;
|
||||
Varnode *multOut = op->getOut();
|
||||
list<PcodeOp *>::const_iterator iter;
|
||||
for(iter=multOut->beginDescend();iter!=multOut->endDescend();++iter) {
|
||||
PcodeOp *rootOp = *iter;
|
||||
if (rootOp->code() != CPUI_INT_ADD) continue;
|
||||
int4 slot = rootOp->getSlot(multOut);
|
||||
if (rootOp->getIn(1-slot) != base) continue;
|
||||
if (slot == 0)
|
||||
data.opSetInput(rootOp,base,0);
|
||||
data.opSetInput(rootOp, data.newConstant(base->getSize(),npow), 1);
|
||||
data.opSetOpcode(rootOp, CPUI_INT_SREM);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/// \brief Verify a form of `V - (V s>> 0x3f)`
|
||||
///
|
||||
/// \param op is the possible root INT_ADD of the form
|
||||
/// \return the Varnode V in the form, or null if the form doesn't match
|
||||
Varnode *RuleSignMod2nOpt2::checkSignExtForm(PcodeOp *op)
|
||||
|
||||
{
|
||||
int4 slot;
|
||||
for(slot=0;slot<2;++slot) {
|
||||
Varnode *minusVn = op->getIn(slot);
|
||||
if (!minusVn->isWritten()) continue;
|
||||
PcodeOp *multOp = minusVn->getDef();
|
||||
if (multOp->code() != CPUI_INT_MULT) continue;
|
||||
Varnode *constVn = multOp->getIn(1);
|
||||
if (!constVn->isConstant()) continue;
|
||||
if (constVn->getOffset() != calc_mask(constVn->getSize())) continue;
|
||||
Varnode *base = op->getIn(1-slot);
|
||||
Varnode *signExt = multOp->getIn(0);
|
||||
if (!signExt->isWritten()) continue;
|
||||
PcodeOp *shiftOp = signExt->getDef();
|
||||
if (shiftOp->code() != CPUI_INT_SRIGHT) continue;
|
||||
if (shiftOp->getIn(0) != base) continue;
|
||||
constVn = shiftOp->getIn(1);
|
||||
if (!constVn->isConstant()) continue;
|
||||
if ((int4)constVn->getOffset() != 8*base->getSize() - 1) continue;
|
||||
return base;
|
||||
}
|
||||
return (Varnode *)0;
|
||||
}
|
||||
|
||||
/// \brief Verify an \e if block like `V = (V s< 0) ? V + 2^n-1 : V`
|
||||
///
|
||||
/// \param op is the MULTIEQUAL
|
||||
/// \param npos is the constant 2^n
|
||||
/// \return the Varnode V in the form, or null if the form doesn't match
|
||||
Varnode *RuleSignMod2nOpt2::checkMultiequalForm(PcodeOp *op,uintb npow)
|
||||
|
||||
{
|
||||
if (op->numInput() != 2) return (Varnode *)0;
|
||||
npow -= 1; // 2^n - 1
|
||||
int4 slot;
|
||||
Varnode *base;
|
||||
for(slot=0;slot<op->numInput();++slot) {
|
||||
Varnode *addOut = op->getIn(slot);
|
||||
if (!addOut->isWritten()) continue;
|
||||
PcodeOp *addOp = addOut->getDef();
|
||||
if (addOp->code() != CPUI_INT_ADD) continue;
|
||||
Varnode *constVn = addOp->getIn(1);
|
||||
if (!constVn->isConstant()) continue;
|
||||
if (constVn->getOffset() != npow) continue;
|
||||
base = addOp->getIn(0);
|
||||
Varnode *otherBase = op->getIn(1-slot);
|
||||
if (otherBase == base)
|
||||
break;
|
||||
}
|
||||
if (slot > 1) return (Varnode *)0;
|
||||
BlockBasic *bl = op->getParent();
|
||||
int4 innerSlot = 0;
|
||||
BlockBasic *inner = (BlockBasic*)bl->getIn(innerSlot);
|
||||
if (inner->sizeOut() != 1 || inner->sizeIn() != 1) {
|
||||
innerSlot = 1;
|
||||
inner = (BlockBasic*)bl->getIn(innerSlot);
|
||||
if (inner->sizeOut() != 1 || inner->sizeIn() != 1)
|
||||
return (Varnode *)0;
|
||||
}
|
||||
BlockBasic *decision = (BlockBasic*)inner->getIn(0);
|
||||
if (bl->getIn(1 - innerSlot) != decision) return (Varnode *)0;
|
||||
PcodeOp *cbranch = decision->lastOp();
|
||||
if (cbranch == (PcodeOp*)0 || cbranch->code() != CPUI_CBRANCH) return (Varnode *)0;
|
||||
Varnode *boolVn = cbranch->getIn(1);
|
||||
if (!boolVn->isWritten()) return (Varnode *)0;
|
||||
PcodeOp *lessOp = boolVn->getDef();
|
||||
if (lessOp->code() != CPUI_INT_SLESS) return (Varnode *)0;
|
||||
if (!lessOp->getIn(1)->isConstant()) return (Varnode *)0;
|
||||
if (lessOp->getIn(1)->getOffset() != 0) return (Varnode *)0;
|
||||
FlowBlock *negBlock = cbranch->isBooleanFlip() ? decision->getFalseOut() : decision->getTrueOut();
|
||||
int4 negSlot = (negBlock == inner) ? innerSlot : (1-innerSlot);
|
||||
if (negSlot != slot) return (Varnode *)0;
|
||||
return base;
|
||||
}
|
||||
|
||||
/// \class RuleSegment
|
||||
/// \brief Propagate constants through a SEGMENTOP
|
||||
void RuleSegment::getOpList(vector<uint4> &oplist) const
|
||||
|
|
|
|||
|
|
@ -1237,6 +1237,17 @@ public:
|
|||
virtual int4 applyOp(PcodeOp *op,Funcdata &data);
|
||||
};
|
||||
|
||||
class RuleDivChain : public Rule {
|
||||
public:
|
||||
RuleDivChain(const string &g) : Rule( g, 0, "divchain") {} ///< Constructor
|
||||
virtual Rule *clone(const ActionGroupList &grouplist) const {
|
||||
if (!grouplist.contains(getGroup())) return (Rule *)0;
|
||||
return new RuleDivChain(getGroup());
|
||||
}
|
||||
virtual void getOpList(vector<uint4> &oplist) const;
|
||||
virtual int4 applyOp(PcodeOp *op,Funcdata &data);
|
||||
};
|
||||
|
||||
class RuleSignForm : public Rule {
|
||||
public:
|
||||
RuleSignForm(const string &g) : Rule( g, 0, "signform") {} ///< Constructor
|
||||
|
|
@ -1248,6 +1259,17 @@ public:
|
|||
virtual int4 applyOp(PcodeOp *op,Funcdata &data);
|
||||
};
|
||||
|
||||
class RuleSignForm2 : public Rule {
|
||||
public:
|
||||
RuleSignForm2(const string &g) : Rule( g, 0, "signform2") {} ///< Constructor
|
||||
virtual Rule *clone(const ActionGroupList &grouplist) const {
|
||||
if (!grouplist.contains(getGroup())) return (Rule *)0;
|
||||
return new RuleSignForm2(getGroup());
|
||||
}
|
||||
virtual void getOpList(vector<uint4> &oplist) const;
|
||||
virtual int4 applyOp(PcodeOp *op,Funcdata &data);
|
||||
};
|
||||
|
||||
class RuleSignNearMult : public Rule {
|
||||
public:
|
||||
RuleSignNearMult(const string &g) : Rule( g, 0, "signnearmult") {} ///< Constructor
|
||||
|
|
@ -1270,6 +1292,42 @@ public:
|
|||
virtual int4 applyOp(PcodeOp *op,Funcdata &data);
|
||||
};
|
||||
|
||||
class RuleSignMod2nOpt : public Rule {
|
||||
public:
|
||||
RuleSignMod2nOpt(const string &g) : Rule( g, 0, "signmod2nopt") {} ///< Constructor
|
||||
virtual Rule *clone(const ActionGroupList &grouplist) const {
|
||||
if (!grouplist.contains(getGroup())) return (Rule *)0;
|
||||
return new RuleSignMod2nOpt(getGroup());
|
||||
}
|
||||
virtual void getOpList(vector<uint4> &oplist) const;
|
||||
virtual int4 applyOp(PcodeOp *op,Funcdata &data);
|
||||
static Varnode *checkSignExtraction(Varnode *outVn);
|
||||
};
|
||||
|
||||
class RuleSignMod2Opt : public Rule {
|
||||
public:
|
||||
RuleSignMod2Opt(const string &g) : Rule( g, 0, "signmod2opt") {} ///< Constructor
|
||||
virtual Rule *clone(const ActionGroupList &grouplist) const {
|
||||
if (!grouplist.contains(getGroup())) return (Rule *)0;
|
||||
return new RuleSignMod2Opt(getGroup());
|
||||
}
|
||||
virtual void getOpList(vector<uint4> &oplist) const;
|
||||
virtual int4 applyOp(PcodeOp *op,Funcdata &data);
|
||||
};
|
||||
|
||||
class RuleSignMod2nOpt2 : public Rule {
|
||||
static Varnode *checkMultiequalForm(PcodeOp *op,uintb npow);
|
||||
static Varnode *checkSignExtForm(PcodeOp *op);
|
||||
public:
|
||||
RuleSignMod2nOpt2(const string &g) : Rule( g, 0, "signmod2nopt2") {} ///< Constructor
|
||||
virtual Rule *clone(const ActionGroupList &grouplist) const {
|
||||
if (!grouplist.contains(getGroup())) return (Rule *)0;
|
||||
return new RuleSignMod2nOpt2(getGroup());
|
||||
}
|
||||
virtual void getOpList(vector<uint4> &oplist) const;
|
||||
virtual int4 applyOp(PcodeOp *op,Funcdata &data);
|
||||
};
|
||||
|
||||
class RuleSegment : public Rule {
|
||||
public:
|
||||
RuleSegment(const string &g) : Rule( g, 0, "segment") {} ///< Constructor
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue