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Simpler LanedRegister collection scheme
This commit is contained in:
caheckman
parent
dddcf4c715
commit
93471fb3ea
9 changed files with 136 additions and 243 deletions
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@ -220,6 +220,42 @@ AddrSpace *Architecture::getSpaceBySpacebase(const Address &loc,int4 size) const
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return (AddrSpace *)0;
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}
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/// Look-up the laned register record associated with a specific storage location. Currently, the
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/// record is only associated with the \e size of the storage, not its address. If there is no
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/// associated record, null is returned.
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/// \param loc is the starting address of the storage location
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/// \param size is the size of the storage in bytes
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/// \return the matching LanedRegister record or null
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const LanedRegister *Architecture::getLanedRegister(const Address &loc,int4 size) const
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{
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int4 min = 0;
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int4 max = lanerecords.size() - 1;
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while(min <= max) {
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int4 mid = (min + max) / 2;
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int4 sz = lanerecords[mid].getWholeSize();
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if (sz < size)
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min = mid + 1;
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else if (size < sz)
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max = mid - 1;
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else
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return &lanerecords[mid];
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}
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return (const LanedRegister *)0;
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}
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/// Return a size intended for comparison with a Varnode size to immediately determine if
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/// the Varnode is a potential laned register. If there are no laned registers for the architecture,
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/// -1 is returned.
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/// \return the size in bytes of the smallest laned register or -1.
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int4 Architecture::getMinimumLanedRegisterSize(void) const
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{
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if (lanerecords.empty())
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return -1;
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return lanerecords[0].getWholeSize();
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}
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/// The default model is used whenever an explicit model is not known
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/// or can't be determined.
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/// \param nm is the name of the model to set
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@ -817,32 +853,23 @@ void Architecture::parseIncidentalCopy(const Element *el)
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void Architecture::parseLaneSizes(const Element *el)
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{
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vector<uint4> maskList;
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const List &childList(el->getChildren());
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List::const_iterator iter;
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LanedRegister lanedRegister; // Only allocate once
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for(iter=childList.begin();iter!=childList.end();++iter) {
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if (lanedRegister.restoreXml(*iter, this)) {
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lanerecords.push_back(lanedRegister);
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int4 sizeIndex = lanedRegister.getWholeSize();
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while (maskList.size() <= sizeIndex)
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maskList.push_back(0);
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maskList[sizeIndex] |= lanedRegister.getSizeBitMask();
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}
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}
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if (lanerecords.empty()) return;
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lanerecords.sort();
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// Dedup records that are contained by (the following) records
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list<LanedRegister>::iterator viter = lanerecords.begin();
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list<LanedRegister>::iterator nextiter = viter;
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++nextiter;
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while(nextiter != lanerecords.end()) {
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if ((*viter).contains(*nextiter)) {
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lanerecords.erase(nextiter);
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nextiter = viter;
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++nextiter;
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}
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else {
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++viter;
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++nextiter;
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}
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lanerecords.clear();
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for(int4 i=0;i<maskList.size();++i) {
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if (maskList[i] == 0) continue;
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lanerecords.push_back(LanedRegister(i,maskList[i]));
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}
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}
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@ -152,7 +152,7 @@ public:
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vector<TypeOp *> inst; ///< Registered p-code instructions
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UserOpManage userops; ///< Specifically registered user-defined p-code ops
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vector<PreferSplitRecord> splitrecords; ///< registers that we would prefer to see split for this processor
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list<LanedRegister> lanerecords; ///< Vector registers that have preferred lane sizes
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vector<LanedRegister> lanerecords; ///< Vector registers that have preferred lane sizes
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ActionDatabase allacts; ///< Actions that can be applied in this architecture
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bool loadersymbols_parsed; ///< True if loader symbols have been read
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#ifdef CPUI_STATISTICS
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@ -167,6 +167,8 @@ public:
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bool hasModel(const string &nm) const; ///< Does this Architecture have a specific PrototypeModel
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bool highPtrPossible(const Address &loc,int4 size) const; ///< Are pointers possible to the given location?
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AddrSpace *getSpaceBySpacebase(const Address &loc,int4 size) const; ///< Get space associated with a \e spacebase register
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const LanedRegister *getLanedRegister(const Address &loc,int4 size) const; ///< Get LanedRegister associated with storage
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int4 getMinimumLanedRegisterSize(void) const; ///< Get the minimum size of a laned register in bytes
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void setDefaultModel(const string &nm); ///< Set the default PrototypeModel
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void clearAnalysis(Funcdata *fd); ///< Clear analysis specific to a function
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void readLoaderSymbols(void); ///< Read any symbols from loader into database
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@ -495,127 +495,6 @@ int4 ActionStackPtrFlow::apply(Funcdata &data)
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return 0;
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}
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/// Mark every PcodeOp that is reachable from the given Varnode and create a LanedAccess record.
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/// \param data is the function to trace through
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/// \param base is the description of the laned register being traced from
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/// \param vn is the Varnode to trace
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/// \param pos is the significance position of the Varnode within the laned register
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void ActionCollectLanedAccess::traceVarnode(Funcdata &data,const LanedRegister *base,Varnode *vn,int4 pos)
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{
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list<PcodeOp *>::const_iterator iter = vn->beginDescend();
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int4 step = 0;
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while(step < 2) {
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PcodeOp *op;
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if (step == 0) {
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op = *iter;
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++iter;
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if (iter == vn->endDescend())
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step = 1;
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}
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else {
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step = 2;
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if (!vn->isWritten()) continue;
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op = vn->getDef();
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}
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if (op->isMark()) continue;
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// Make sure op is associated with a lane access records describing its biggest Varnode
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switch(op->code()) {
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case CPUI_LOAD:
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case CPUI_PIECE:
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case CPUI_INT_ZEXT:
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case CPUI_INT_SEXT:
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if (vn != op->getOut()) continue; // Biggest Varnode is the output
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break;
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case CPUI_SUBPIECE:
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if (vn != op->getIn(0)) continue; // Biggest Varnode is first input
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break;
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case CPUI_STORE:
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if (vn != op->getIn(2)) continue;
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break;
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default:
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break;
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}
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op->setMark();
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data.opMarkLanedAccess(base, op, vn->getSize(), pos);
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}
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}
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/// \brief Search for Varnodes that match the given laned vector register
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///
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/// All varnodes (bigger than 8 bytes) that are contained in the vector register are processed,
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/// looking for a working lane scheme. Data-flow from these Varnodes is traces and LanedAccess
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/// records are created for each PcodeOp flowed through.
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/// \param data is the function being traced
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/// \param lanedRegister is the given register and acceptable lane schemes
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/// \param iter is an iterator to the first Varnode that matches the vector register
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void ActionCollectLanedAccess::processLane(Funcdata &data,const LanedRegister &lanedRegister,
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VarnodeLocSet::const_iterator iter)
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{
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int4 fullSize = lanedRegister.getStorage().size;
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Address startAddress(lanedRegister.getStorage().getAddr());
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Address lastAddress(startAddress + (fullSize-1));
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VarnodeLocSet::const_iterator enditer = data.endLoc();
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while(iter != enditer) {
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Varnode *vn = *iter;
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++iter;
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if (lastAddress < vn->getAddr())
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break;
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if (vn->getSize() <= 8) // Varnode not big enough to be vector register
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continue;
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int4 diff = (int4)(vn->getOffset() - startAddress.getOffset());
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if (diff + vn->getSize() > fullSize) // Must be contained by full register
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continue;
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if (vn->getSpace()->isBigEndian())
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diff = fullSize - (diff + vn->getSize());
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traceVarnode(data, &lanedRegister, vn, diff);
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}
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}
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/// Give each PcodeOp in the laned access list a chance to propagate to new PcodeOps,
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/// which will have new records added to the list.
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/// \param data is the function being traced
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void ActionCollectLanedAccess::propagate(Funcdata &data)
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{
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list<LanedAccess>::const_iterator iter = data.beginLaneAccess();
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while(iter != data.endLaneAccess()) {
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const LanedAccess lanedAccess( *iter );
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PcodeOp *op = lanedAccess.getOp();
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int4 sz = lanedAccess.getSize();
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for(int4 i=0;i<op->numInput();++i) {
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Varnode *vn = op->getIn(i);
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if (vn->getSize() != sz) continue; // Size must match exactly
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if (vn->isConstant() || vn->isAnnotation()) continue;
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traceVarnode(data, lanedAccess.getBase(), vn, lanedAccess.getBytePos());
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}
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++iter;
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}
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}
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int4 ActionCollectLanedAccess::apply(Funcdata &data)
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{
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if (data.getArch()->lanerecords.empty())
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return 0;
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const LanedRegister &lastRecord( data.getArch()->lanerecords.back() );
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Address lastAddress( lastRecord.getStorage().getAddr() + lastRecord.getStorage().size - 1);
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list<LanedRegister>::const_iterator iter;
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for(iter=data.getArch()->lanerecords.begin();iter!=data.getArch()->lanerecords.end();++iter) {
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const LanedRegister &lanedRegister( *iter );
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VarnodeLocSet::const_iterator viter = data.beginLoc(lanedRegister.getStorage().getAddr());
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if (viter == data.endLoc()) break;
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Varnode *vn = *viter;
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if (lastAddress < vn->getAddr()) break;
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processLane(data,lanedRegister,viter);
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}
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propagate(data);
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list<LanedAccess>::const_iterator aiter;
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for(aiter=data.beginLaneAccess();aiter!=data.endLaneAccess();++aiter)
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(*aiter).getOp()->clearMark();
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return 0;
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}
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/// \brief Try to divide a single Varnode into lanes
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///
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/// Look for a CPUI_SUBPIECE op that takes the given Varnode as the input or a
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@ -626,15 +505,17 @@ int4 ActionCollectLanedAccess::apply(Funcdata &data)
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/// \param data is the function being transformed
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/// \param vn is the given single Varnode
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/// \param lanedRegister is acceptable set of lane sizes for the Varnode
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/// \param bytePos is the significance position of the Varnode within the laned register
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/// \param allowDowncast is \b true if we allow lane systems with SUBPIECE terminators
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bool ActionLaneDivide::processVarnode(Funcdata &data,Varnode *vn,const LanedRegister &lanedRegister,int4 bytePos,
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bool allowDowncast)
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/// \return \b true if the Varnode (and its data-flow) was successfully split
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bool ActionLaneDivide::processVarnode(Funcdata &data,Varnode *vn,const LanedRegister &lanedRegister,bool allowDowncast)
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{
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list<PcodeOp *>::const_iterator iter = vn->beginDescend();
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LanedRegister checkedLanes;
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int4 step = 0; // 0 = descendants, 1 = def, 2 = done
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if (iter == vn->endDescend()) {
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step = 1;
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}
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while(step < 2) {
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int4 curSize; // Putative lane size
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if (step == 0) {
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@ -657,10 +538,8 @@ bool ActionLaneDivide::processVarnode(Funcdata &data,Varnode *vn,const LanedRegi
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}
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if (lanedRegister.allowedLane(curSize)) {
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if (checkedLanes.allowedLane(curSize)) continue;
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checkedLanes.addSize(curSize); // Only check this scheme once
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LaneDescription description(lanedRegister.getStorage().size,curSize); // Lane scheme dictated by curSize
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if (!description.subset(bytePos,vn->getSize())) // Try to restrict lane scheme to actual Varnode
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continue;
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checkedLanes.addLaneSize(curSize); // Only check this scheme once
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LaneDescription description(lanedRegister.getWholeSize(),curSize); // Lane scheme dictated by curSize
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LaneDivide laneDivide(&data,vn,description,allowDowncast);
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if (laneDivide.doTrace()) {
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laneDivide.apply();
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@ -675,31 +554,28 @@ bool ActionLaneDivide::processVarnode(Funcdata &data,Varnode *vn,const LanedRegi
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int4 ActionLaneDivide::apply(Funcdata &data)
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{
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list<LanedAccess>::const_iterator iter;
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map<VarnodeData,const LanedRegister *>::const_iterator iter;
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bool allowDowncast = false;
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for(int4 i=0;i<2;++i) {
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for(iter=data.beginLaneAccess();iter!=data.endLaneAccess();++iter) {
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const LanedAccess &lanedAccess(*iter);
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PcodeOp *op = lanedAccess.getOp();
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if (op->isDead()) continue;
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Varnode *vn = op->getOut();
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if (vn != (Varnode *)0 && vn->getSize() == lanedAccess.getSize())
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processVarnode(data, vn, *lanedAccess.getBase(), lanedAccess.getBytePos(), allowDowncast);
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else {
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for(int4 j=0;j<op->numInput();++j) {
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vn = op->getIn(j);
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if (vn->getSize() == lanedAccess.getSize()) {
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if (!vn->isConstant() && !vn->isAnnotation() && !vn->isWritten()) {
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processVarnode(data, vn, *lanedAccess.getBase(), lanedAccess.getBytePos(), allowDowncast);
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break;
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}
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}
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const LanedRegister *lanedReg = (*iter).second;
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Address addr = (*iter).first.getAddr();
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int4 sz = (*iter).first.size;
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VarnodeLocSet::const_iterator viter = data.beginLoc(sz,addr);
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VarnodeLocSet::const_iterator venditer = data.endLoc(sz,addr);
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while(viter != venditer) {
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Varnode *vn = *viter;
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if (processVarnode(data, vn, *lanedReg, allowDowncast)) {
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viter = data.beginLoc(sz,addr);
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venditer = data.endLoc(sz, addr); // Recalculate bounds
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}
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else
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++viter;
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}
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}
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allowDowncast = true;
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}
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data.clearLanedAccessList();
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data.clearLanedAccessMap();
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return 0;
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}
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@ -1238,14 +1114,30 @@ int4 ActionDeindirect::apply(Funcdata &data)
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return 0;
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}
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/// Check if the given Varnode has a matching LanedRegister record. If so, add its
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/// storage location to the given function's laned access list.
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/// \param data is the given function
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/// \param vn is the given Varnode
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void ActionVarnodeProps::markLanedVarnode(Funcdata &data,Varnode *vn)
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{
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if (vn->isConstant()) return;
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Architecture *glb = data.getArch();
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const LanedRegister *lanedRegister = glb->getLanedRegister(vn->getAddr(),vn->getSize());
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if (lanedRegister != (const LanedRegister *)0)
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data.markLanedVarnode(vn,lanedRegister);
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}
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int4 ActionVarnodeProps::apply(Funcdata &data)
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{
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Architecture *glb = data.getArch();
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bool cachereadonly = glb->readonlypropagate;
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if (glb->userops.getVolatileRead() == (VolatileReadOp *)0) {
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if (!cachereadonly)
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return 0; // Nothing to do to special properties
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int4 minLanedSize = 1000000; // Default size meant to filter no Varnodes
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if (!data.isLanedRegComplete()) {
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int4 sz = glb->getMinimumLanedRegisterSize();
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if (sz > 0)
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minLanedSize = sz;
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}
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VarnodeLocSet::const_iterator iter;
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Varnode *vn;
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@ -1254,6 +1146,9 @@ int4 ActionVarnodeProps::apply(Funcdata &data)
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while(iter != data.endLoc()) {
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vn = *iter++; // Advance iterator in case vn is deleted
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if (vn->isAnnotation()) continue;
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int4 vnSize = vn->getSize();
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if (vnSize >= minLanedSize)
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markLanedVarnode(data, vn);
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if (vn->hasActionProperty()) {
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if (cachereadonly&&vn->isReadOnly()) {
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if (data.fillinReadOnly(vn)) // Try to replace vn with its lookup in LoadImage
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@ -1263,7 +1158,7 @@ int4 ActionVarnodeProps::apply(Funcdata &data)
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if (data.replaceVolatile(vn))
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count += 1; // Try to replace vn with pcode op
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}
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else if (((vn->getNZMask() & vn->getConsume())==0)&&(vn->getSize()<=sizeof(uintb))) {
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else if (((vn->getNZMask() & vn->getConsume())==0)&&(vnSize<=sizeof(uintb))) {
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// FIXME: uintb should be arbitrary precision
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if (vn->isConstant()) continue; // Don't replace a constant
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if (vn->isWritten()) {
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@ -1283,6 +1178,7 @@ int4 ActionVarnodeProps::apply(Funcdata &data)
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}
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}
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}
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data.setLanedRegGenerated();
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return 0;
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}
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@ -4714,7 +4610,6 @@ void universal_action(Architecture *conf)
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// actmainloop->addAction( new ActionParamShiftStop("paramshift") );
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actmainloop->addAction( new ActionRestrictLocal("localrecovery") ); // Do before dead code removed
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actmainloop->addAction( new ActionDeadCode("deadcode") );
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actmainloop->addAction( new ActionCollectLanedAccess("base") );
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actmainloop->addAction( new ActionDynamicMapping("dynamic") ); // Must come before restructurevarnode and infertypes
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actmainloop->addAction( new ActionRestructureVarnode("localrecovery") );
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actmainloop->addAction( new ActionSpacebase("base") ); // Must come before infertypes and nonzeromask
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@ -97,26 +97,6 @@ public:
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virtual int4 apply(Funcdata &data);
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};
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/// \brief Find PcodeOps that are accessing values from laned registers
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///
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/// This looks for Varnodes that match any of the LanedRegister records associated with
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/// the architecture. A record is created in the function's LanedAccess list for every
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/// PcodeOp that accesses one of these Varnodes. These are later examined by ActionLaneDivide.
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/// The LanedRegister is the key for finding the Varnode, but the \e big property can propagate
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/// through data-flow to other Varnodes that are not necessarily using the same storage (i.e. uniques).
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class ActionCollectLanedAccess : public Action {
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void traceVarnode(Funcdata &data,const LanedRegister *base,Varnode *vn,int4 pos); ///< Trace a big Varnode instance to other big Varnodes
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void processLane(Funcdata &data,const LanedRegister &lanedRegister,VarnodeLocSet::const_iterator iter);
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void propagate(Funcdata &data); ///< Discover other PcodeOps that use laned values
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public:
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ActionCollectLanedAccess(const string &g) : Action(rule_onceperfunc,"collectlanedaccess",g) {} ///< Constructor
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||||
virtual Action *clone(const ActionGroupList &grouplist) const {
|
||||
if (!grouplist.contains(getGroup())) return (Action *)0;
|
||||
return new ActionCollectLanedAccess(getGroup());
|
||||
}
|
||||
virtual int4 apply(Funcdata &data);
|
||||
};
|
||||
|
||||
/// \brief Find Varnodes with a vectorized lane scheme and attempt to split the lanes
|
||||
///
|
||||
/// The Architecture lists (vector) registers that may be used to perform parallelized operations
|
||||
|
|
@ -124,7 +104,7 @@ public:
|
|||
/// if a particular lane scheme makes sense in terms of the function's data-flow, and then
|
||||
/// rewrites the data-flow so that the lanes become explicit Varnodes.
|
||||
class ActionLaneDivide : public Action {
|
||||
bool processVarnode(Funcdata &data,Varnode *vn,const LanedRegister &lanedRegister,int4 bytePos,bool allowDowncast);
|
||||
bool processVarnode(Funcdata &data,Varnode *vn,const LanedRegister &lanedRegister,bool allowDowncast);
|
||||
public:
|
||||
ActionLaneDivide(const string &g) : Action(rule_onceperfunc,"lanedivide",g) {} ///< Constructor
|
||||
virtual Action *clone(const ActionGroupList &grouplist) const {
|
||||
|
|
@ -222,8 +202,15 @@ public:
|
|||
virtual int4 apply(Funcdata &data);
|
||||
};
|
||||
|
||||
/// \brief Transform read-only variables to constants
|
||||
/// \brief Transform based on Varnode properties, such as \e read-only and \e volatile
|
||||
///
|
||||
/// This performs various transforms that are based on Varnode properties.
|
||||
/// - Read-only Varnodes are converted to the underlying constant
|
||||
/// - Volatile Varnodes are converted read/write functions
|
||||
/// - Varnodes whose values are not consumed are replaced with constant 0 Varnodes
|
||||
/// - Large Varnodes are flagged for lane analysis
|
||||
class ActionVarnodeProps : public Action {
|
||||
void markLanedVarnode(Funcdata &data,Varnode *vn); ///< Mark possible laned register storage
|
||||
public:
|
||||
ActionVarnodeProps(const string &g) : Action(0,"varnodeprops",g) {} ///< Constructor
|
||||
virtual Action *clone(const ActionGroupList &grouplist) const {
|
||||
|
|
|
|||
|
|
@ -56,7 +56,8 @@ class Funcdata {
|
|||
restart_pending = 0x200, ///< Analysis must be restarted (because of new override info)
|
||||
unimplemented_present = 0x400, ///< Set if function contains unimplemented instructions
|
||||
baddata_present = 0x800, ///< Set if function flowed into bad data
|
||||
double_precis_on = 0x1000 ///< Set if we are performing double precision recovery
|
||||
double_precis_on = 0x1000, ///< Set if we are performing double precision recovery
|
||||
big_varnodes_generated = 0x2000 ///< Set when search for laned registers is complete
|
||||
};
|
||||
uint4 flags; ///< Boolean properties associated with \b this function
|
||||
uint4 clean_up_index; ///< Creation index of first Varnode created after start of cleanup
|
||||
|
|
@ -80,7 +81,7 @@ class Funcdata {
|
|||
Merge covermerge; ///< Variable range intersection algorithms
|
||||
ParamActive *activeoutput; ///< Data for assessing which parameters are passed to \b this function
|
||||
Override localoverride; ///< Overrides of data-flow, prototypes, etc. that are local to \b this function
|
||||
list<LanedAccess> lanedList; ///< List of ops that are accessing potentially laned registers
|
||||
map<VarnodeData,const LanedRegister *> lanedMap; ///< Current storage locations which may be laned registers
|
||||
|
||||
// Low level Varnode functions
|
||||
void setVarnodeProperties(Varnode *vn) const; ///< Look-up boolean properties and data-type information
|
||||
|
|
@ -131,6 +132,8 @@ public:
|
|||
bool isTypeRecoveryOn(void) const { return ((flags&typerecovery_on)!=0); } ///< Has data-type recovery processes started
|
||||
bool hasNoCode(void) const { return ((flags & no_code)!=0); } ///< Return \b true if \b this function has no code body
|
||||
void setNoCode(bool val) { if (val) flags |= no_code; else flags &= ~no_code; } ///< Toggle whether \b this has a body
|
||||
bool isLanedRegComplete(void) const { return ((flags&big_varnodes_generated)!=0); } ///< Have potential laned registers been generated
|
||||
void setLanedRegGenerated(void) { flags |= big_varnodes_generated; } ///< Mark that laned registers have been collected
|
||||
|
||||
/// \brief Toggle whether \b this is being used for jump-table recovery
|
||||
///
|
||||
|
|
@ -347,6 +350,11 @@ public:
|
|||
/// \brief End of (input or free) Varnodes at a given storage address
|
||||
VarnodeDefSet::const_iterator endDef(uint4 fl,const Address &addr) const { return vbank.endDef(fl,addr); }
|
||||
|
||||
void markLanedVarnode(Varnode *vn,const LanedRegister *lanedReg); ///< Mark Varnode as potential laned register
|
||||
map<VarnodeData,const LanedRegister *>::const_iterator beginLaneAccess(void) const { return lanedMap.begin(); } ///< Beginning iterator over laned accesses
|
||||
map<VarnodeData,const LanedRegister *>::const_iterator endLaneAccess(void) const { return lanedMap.end(); } ///< Ending iterator over laned accesses
|
||||
void clearLanedAccessMap(void) { lanedMap.clear(); } ///< Clear records from the laned access list
|
||||
|
||||
HighVariable *findHigh(const string &name) const; ///< Find a high-level variable by name
|
||||
void mapGlobals(void); ///< Make sure there is a Symbol entry for all global Varnodes
|
||||
bool checkCallDoubleUse(const PcodeOp *opmatch,const PcodeOp *op,const Varnode *vn,const ParamTrial &trial) const;
|
||||
|
|
@ -429,10 +437,6 @@ public:
|
|||
Varnode *opStackLoad(AddrSpace *spc,uintb off,uint4 sz,PcodeOp *op,Varnode *stackptr,bool insertafter);
|
||||
PcodeOp *opStackStore(AddrSpace *spc,uintb off,PcodeOp *op,bool insertafter);
|
||||
void opUndoPtradd(PcodeOp *op,bool finalize); ///< Convert a CPUI_PTRADD back into a CPUI_INT_ADD
|
||||
void opMarkLanedAccess(const LanedRegister *base,PcodeOp *op,int4 sz,int4 pos); ///< Mark op as using laned register
|
||||
list<LanedAccess>::const_iterator beginLaneAccess(void) const { return lanedList.begin(); } ///< Beginning iterator over laned accesses
|
||||
list<LanedAccess>::const_iterator endLaneAccess(void) const { return lanedList.end(); } ///< Ending iterator over laned accesses
|
||||
void clearLanedAccessList(void) { lanedList.clear(); } ///< Clear records from the laned access list
|
||||
|
||||
/// \brief Start of PcodeOp objects with the given op-code
|
||||
list<PcodeOp *>::const_iterator beginOp(OpCode opc) const { return obank.begin(opc); }
|
||||
|
|
|
|||
|
|
@ -557,19 +557,6 @@ void Funcdata::opUndoPtradd(PcodeOp *op,bool finalize)
|
|||
opInsertBefore(multOp,op);
|
||||
}
|
||||
|
||||
/// Store a record indicating a potential use of a large laned register. Generally, the output
|
||||
/// of the op is the use, except in the case of SUBPIECE or STORE, where getIn(0) and getIn(2)
|
||||
/// respectively are the Varnodes being used.
|
||||
/// \param base is the description of the laned register that is triggering this record
|
||||
/// \param op is the PcodeOp using the large Varnode
|
||||
/// \param sz is the size of the large Varnode in bytes
|
||||
/// \param pos is the significance position of the Varnode, relative to the LanedRegister description
|
||||
void Funcdata::opMarkLanedAccess(const LanedRegister *base,PcodeOp *op,int4 sz,int4 pos)
|
||||
|
||||
{
|
||||
lanedList.push_back(LanedAccess(base,op,sz,pos));
|
||||
}
|
||||
|
||||
/// Make a clone of the given PcodeOp, copying control-flow properties as well. The data-type
|
||||
/// is \e not cloned.
|
||||
/// \param op is the PcodeOp to clone
|
||||
|
|
|
|||
|
|
@ -286,6 +286,21 @@ void Funcdata::destroyVarnode(Varnode *vn)
|
|||
vbank.destroy(vn);
|
||||
}
|
||||
|
||||
/// Record the given Varnode as a potential laned register access.
|
||||
/// The address and size of the Varnode is recorded, anticipating that new
|
||||
/// Varnodes at the same storage location may be created
|
||||
/// \param vn is the given Varnode to mark
|
||||
/// \param lanedReg is the laned register record to associate with the Varnode
|
||||
void Funcdata::markLanedVarnode(Varnode *vn,const LanedRegister *lanedReg)
|
||||
|
||||
{
|
||||
VarnodeData storage;
|
||||
storage.space = vn->getSpace();
|
||||
storage.offset = vn->getOffset();
|
||||
storage.size = vn->getSize();
|
||||
lanedMap[storage] = lanedReg;
|
||||
}
|
||||
|
||||
/// Look up the Symbol visible in \b this function's Scope and return the HighVariable
|
||||
/// associated with it. If the Symbol doesn't exist or there is no Varnode holding at least
|
||||
/// part of the value of the Symbol, NULL is returned.
|
||||
|
|
|
|||
|
|
@ -276,8 +276,10 @@ bool LanedRegister::restoreXml(const Element *el,const AddrSpaceManager *manage)
|
|||
}
|
||||
}
|
||||
if (laneSizes.empty()) return false;
|
||||
VarnodeData storage;
|
||||
storage.space = (AddrSpace *)0;
|
||||
storage.restoreXml(el, manage);
|
||||
wholeSize = storage.size;
|
||||
sizeBitMask = 0;
|
||||
string::size_type pos = 0;
|
||||
while(pos != string::npos) {
|
||||
|
|
@ -299,23 +301,11 @@ bool LanedRegister::restoreXml(const Element *el,const AddrSpaceManager *manage)
|
|||
s >> sz;
|
||||
if (sz < 0 || sz > 16)
|
||||
throw LowlevelError("Bad lane size: " + value);
|
||||
addSize(sz);
|
||||
addLaneSize(sz);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/// In order to return \b true, the storage for \b this must contain the storage for the other
|
||||
/// LanedRegister, and every lane scheme of the other LanedRegister must also be a lane scheme
|
||||
/// for \b this.
|
||||
/// \param op2 is the other LanedRegister to check for containment
|
||||
/// \return \b true if \b this contains the other register
|
||||
bool LanedRegister::contains(const LanedRegister &op2) const
|
||||
|
||||
{
|
||||
if (!storage.contains(op2.storage)) return false;
|
||||
return ((sizeBitMask & op2.sizeBitMask) == op2.sizeBitMask); // Check for containment of lane size sets
|
||||
}
|
||||
|
||||
TransformManager::~TransformManager(void)
|
||||
|
||||
{
|
||||
|
|
|
|||
|
|
@ -86,30 +86,16 @@ public:
|
|||
|
||||
/// \brief Describes a (register) storage location and the ways it might be split into lanes
|
||||
class LanedRegister {
|
||||
VarnodeData storage; ///< Defining characteristics of the register
|
||||
int4 wholeSize; ///< Size of the whole register
|
||||
uint4 sizeBitMask; ///< A 1-bit for every permissible lane size
|
||||
public:
|
||||
LanedRegister(void) { sizeBitMask = 0; } ///< Constructor
|
||||
LanedRegister(void) { wholeSize = 0; sizeBitMask = 0; } ///< Constructor for use with restoreXml
|
||||
LanedRegister(int4 sz,uint4 mask) { wholeSize = sz; sizeBitMask = mask; } ///< Constructor
|
||||
bool restoreXml(const Element *el,const AddrSpaceManager *manage); ///< Restore object from XML stream
|
||||
const VarnodeData &getStorage(void) const { return storage; } ///< Get VarnodeData for storage
|
||||
void addSize(int4 size) { sizeBitMask |= ((uint4)1 << size); } ///< Add a new \e size to the allowed list
|
||||
int4 getWholeSize(void) const { return wholeSize; } ///< Get the size in bytes of the whole laned register
|
||||
uint4 getSizeBitMask(void) const { return sizeBitMask; } ///< Get the bit mask of possible lane sizes
|
||||
void addLaneSize(int4 size) { sizeBitMask |= ((uint4)1 << size); } ///< Add a new \e size to the allowed list
|
||||
bool allowedLane(int4 size) const { return (((sizeBitMask >> size) & 1) != 0); } ///< Is \e size among the allowed lane sizes
|
||||
bool contains(const LanedRegister &op2) const; ///< Does \b this contain the given register and its possible lanes
|
||||
bool operator<(const LanedRegister &op2) const { return (storage < op2.storage); } ///< Compare based on VarnodeData
|
||||
};
|
||||
|
||||
/// \brief Record describing the access of a large Varnode that can be traced to a LanedRegister
|
||||
class LanedAccess {
|
||||
const LanedRegister *base; ///< Base register dictating the lane scheme
|
||||
PcodeOp *op; ///< Operation using the big register
|
||||
int4 size; ///< Size of the register in bytes
|
||||
int4 bytePos; ///< Significance position relative to the laned register
|
||||
public:
|
||||
LanedAccess(const LanedRegister *b,PcodeOp *o,int4 sz,int4 pos) { base=b; op=o; size=sz; bytePos=pos; } ///< Constructor
|
||||
const LanedRegister *getBase(void) const { return base; } ///< Get the base LanedRegister being traced
|
||||
PcodeOp *getOp(void) const { return op; } ///< Get the PcodeOp using the large Varnode
|
||||
int4 getSize(void) const { return size; } ///< Get the size of the Varnode being accessed
|
||||
int4 getBytePos(void) const { return bytePos; } ///< Get the significance position relative to the laned register
|
||||
};
|
||||
|
||||
/// \brief Description of logical lanes within a \b big Varnode
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue