diff --git a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
index fa6def6f41..f52bbfb41c 100644
--- a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
+++ b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
@@ -3173,26 +3173,26 @@ define pcodeop FloatVectorNeg;
 	Sd = zext(product);
 }
 
-:vnmul.f64 Dd,Dn,Dm		is COND & ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=11 & c0606=1 & c0404=0) |
-                                    ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dn & Dd 
+:vnmul^COND^".f64" Dd,Dn,Dm is ( ($(AMODE) & COND & c2327=0x1c & c2021=2 & c0811=11 & c0606=1 & c0404=0) |
+                                 ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0) ) & Dm & Dn & Dd
 {
-	product:8 = Dn f* Dm;
-	Dd = 0 f- product;
+    product:8 = Dn f* Dm;
+    Dd = 0 f- product;
 }
 
-:vnmul.f32 Sd,Sn,Sm		is COND & ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=10 & c0606=1 & c0404=0) |
-                                    ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd 
+:vnmul^COND^".f32" Sd,Sn,Sm is ( ($(AMODE) & COND & c2327=0x1c & c2021=2 & c0811=10 & c0606=1 & c0404=0) |
+                                 ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd
 {
-	product:4 = Sn f* Sm;
-	Sd = 0 f- product;
+    product:4 = Sn f* Sm;
+    Sd = 0 f- product;
 }
 
-:vnmul.f16 Sd,Sn,Sm		is COND & ( ($(AMODE) & cond=15 & c2327=0x1c & c2021=2 & c0811=9 & c0606=1 & c0404=0) |
-                                    ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd 
+:vnmul.f16 Sd,Sn,Sm         is ( ($(AMODE) & cond=0xe & c2327=0x1c & c2021=2 & c0811=9 & c0606=1 & c0404=0) |
+                                 ($(TMODE_E) & thv_c2327=0x1c & thv_c2021=2 & thv_c0811=9 & thv_c0606=1 & thv_c0404=0) ) & Sm & Sn & Sd
 {
-	product:2 = Sn:2 f* Sm:2;
-	product = 0 f- product;
-	Sd = zext(product);
+    product:2 = Sn:2 f* Sm:2;
+    product = 0 f- product;
+    Sd = zext(product);
 }
 
 :vneg^COND^".f32" Sd,Sm		is ( ( $(AMODE) & COND &     c2327=0x1d &     c1621=0x31 &     c0611=0x29 &     c0404=0 ) |