yetangitu/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2025-10-04 18:29:37 +02:00
Code Issues Releases Wiki Activity

Corrected processor ordering for movups pcode

Browse source
This commit is contained in:
ghidorahrex 2021-03-03 07:55:44 -05:00
parent 0ffb30b113
commit 9a37a3a19a
1 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

8
Ghidra/Processors/x86/data/languages/ia.sinc
View file

@ -5712,10 +5712,10 @@ define pcodeop movmskps;
:MOVUPS XmmReg2, XmmReg1 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2 :MOVUPS XmmReg2, XmmReg1 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x11; xmmmod = 3 & XmmReg1 & XmmReg2
{ {
XmmReg1[0,32] = XmmReg2[0,32]; XmmReg2[0,32] = XmmReg1[0,32];
XmmReg1[32,32] = XmmReg2[32,32]; XmmReg2[32,32] = XmmReg1[32,32];
XmmReg1[64,32] = XmmReg2[64,32]; XmmReg2[64,32] = XmmReg1[64,32];
XmmReg1[96,32] = XmmReg2[96,32]; XmmReg2[96,32] = XmmReg1[96,32];
} }
:MULPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x59; m128 & XmmReg ... :MULPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x59; m128 & XmmReg ...