From a487f77918e4f795a30f218cdae9ca274bf29d3c Mon Sep 17 00:00:00 2001
From: mumbel <22204578+mumbel@users.noreply.github.com>
Date: Wed, 28 Oct 2020 21:46:09 -0500
Subject: [PATCH] Opinion fix

Does not handle all the cases it can, add in size IMAFC and
generic cases for GC.
---
 .../RISCV/data/languages/riscv.opinion        | 21 +++++++++++--------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.opinion b/Ghidra/Processors/RISCV/data/languages/riscv.opinion
index 08eefb35d3..4f550dedbc 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.opinion
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.opinion
@@ -11,15 +11,18 @@
       <!-- EF_RISCV_ABI_QUAD          0x0006  -->
       <!-- EF_RISCV_RVE               0x0008  -->
       <!-- EF_RISCV_TSO               0x0010  -->
-      <constraint primary="243" secondary="0" processor="RISCV" endian="little" variant="RV32I"/>
-      <constraint primary="243" secondary="0" processor="RISCV" endian="little" variant="RV64I"/>
-      <constraint primary="243" secondary="1" processor="RISCV" endian="little" variant="RV32IMC"/>
-      <constraint primary="243" secondary="1" processor="RISCV" endian="little" variant="RV64IC"/>
-      <constraint primary="243" secondary="2" processor="RISCV" endian="little" variant="RV32IF"/>
-      <constraint primary="243" secondary="4" processor="RISCV" endian="little" variant="RV32G"/>
-      <constraint primary="243" secondary="4" processor="RISCV" endian="little" variant="RV64G"/>
-      <constraint primary="243" secondary="5" processor="RISCV" endian="little" variant="RV32GC"/>
-      <constraint primary="243" secondary="5" processor="RISCV" endian="little" variant="RV64GC"/>
+      <constraint primary="243" secondary="0" processor="RISCV" endian="little" size="32" variant="RV32I"/>
+      <constraint primary="243" secondary="0" processor="RISCV" endian="little" size="64" variant="RV64I"/>
+      <constraint primary="243" secondary="1" processor="RISCV" endian="little" size="32" variant="RV32IMC"/>
+      <constraint primary="243" secondary="1" processor="RISCV" endian="little" size="64" variant="RV64IC"/>
+      <constraint primary="243" secondary="2" processor="RISCV" endian="little" size="32" variant="RV32IF"/>
+      <constraint primary="243" secondary="3" processor="RISCV" endian="little" size="32" variant="RV32GC"/> <!-- RV32IMAFC -->
+      <constraint primary="243" secondary="4" processor="RISCV" endian="little" size="32" variant="RV32G"/>
+      <constraint primary="243" secondary="4" processor="RISCV" endian="little" size="64" variant="RV64G"/>
+      <constraint primary="243" secondary="5" processor="RISCV" endian="little" size="32" variant="RV32GC"/>
+      <constraint primary="243" secondary="5" processor="RISCV" endian="little" size="64" variant="RV64GC"/>
+      <constraint primary="243" processor="RISCV" endian="little" size="32" variant="RV32GC"/>
+      <constraint primary="243" processor="RISCV" endian="little" size="64" variant="RV64GC"/>
     </constraint>
   </constraint>
 </opinions>