mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2025-10-04 18:29:37 +02:00
GT-3202: SparcV9 sleigh corrections
- Correctly implemented register windowing function for save/restore - Corrected floating point instructions which used the wrong operands - Corrected .cspec issues for 32- and 64-bit - Implemented pcodetests for 64-bit.
This commit is contained in:
ghidorahrex
parent
b5d772d98d
commit
a61ea576cf
7 changed files with 214 additions and 118 deletions
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@ -53,20 +53,20 @@ define register offset=0x6000 size=$(SIZE) [ HPSTATE1 HPSTATE2 HPSTATE3 HPSTATE4
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HSTICK_CMPR1 HSTICK_CMPR2 HSTICK_CMPR3 HSTICK_CMPR4
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];
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# A window is 24 registers (96 or 192 bytes), must processors have 7 or 8. (g0->g7,o0->o7,l0->o7,i0->i7)
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# A window is 24 registers (96 or 192 bytes), most processors have 7 or 8. (g0->g7,o0->o7,l0->o7,i0->i7)
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# When the window is overflowed the data must be purged to some backup memory, via user
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# suppied function attached to a signal handler.
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# supplied function attached to a signal handler.
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# When the window is underflowed the data must be read from some backup memory, via user
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# suppied function attached to a signal handler.
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# supplied function attached to a signal handler.
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# There are 2 basic strategies we figured for this.
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# One, create a bank of register space and read and write to it in a way that simulates
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# how the sparc would really work, but the symboic names become indexes.
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# how the sparc would really work, but the symbolic names become indexes.
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# Two, save and restore logic does all the work.
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# window index is ((CWP+1)%NWINDOWS)
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# CWP is an index from 0 to N of the wondows.
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# Size of CWP is implimination depedent (must be > 5 bits).
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# CWP is an index from 0 to N of the windows.
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# Size of CWP is implementation dependent (must be > 5 bits).
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# inputs i0 i1 i2 i3 i4 i5 fp i7
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# locals l0 l1 l2 l3 l4 l5 l6 l7
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@ -245,26 +245,26 @@ attach variables [ rs1_3 ] [ Y _ CCR _ TICK PC _
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# CWP++
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macro save() {
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@if SIZE=="4"
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# # Save inputs
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+0)*$(SIZE)) = i0;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+1)*$(SIZE)) = i1;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+2)*$(SIZE)) = i2;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+3)*$(SIZE)) = i3;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+4)*$(SIZE)) = i4;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+5)*$(SIZE)) = i5;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+6)*$(SIZE)) = fp;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+7)*$(SIZE)) = i7;
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#
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# # Save local
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+0+$(LOCALOFF))*$(SIZE)) = l0;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+1+$(LOCALOFF))*$(SIZE)) = l1;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+2+$(LOCALOFF))*$(SIZE)) = l3;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+3+$(LOCALOFF))*$(SIZE)) = l3;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+4+$(LOCALOFF))*$(SIZE)) = l4;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+5+$(LOCALOFF))*$(SIZE)) = l5;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)) = l6;
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# *[register]:$(SIZE) (&w010 + (CWP*$(REGWINSZ)+7+$(LOCALOFF))*$(SIZE)) = l7;
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@if SIZE=="4" || SIZE == "8"
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# Save inputs
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+0)*$(SIZE)) = i0;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+1)*$(SIZE)) = i1;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+2)*$(SIZE)) = i2;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+3)*$(SIZE)) = i3;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+4)*$(SIZE)) = i4;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+5)*$(SIZE)) = i5;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+6)*$(SIZE)) = fp;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+7)*$(SIZE)) = i7;
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# Save local
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+0+$(LOCALOFF))*$(SIZE)) = l0;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+1+$(LOCALOFF))*$(SIZE)) = l1;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+2+$(LOCALOFF))*$(SIZE)) = l3;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+3+$(LOCALOFF))*$(SIZE)) = l3;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+4+$(LOCALOFF))*$(SIZE)) = l4;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+5+$(LOCALOFF))*$(SIZE)) = l5;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)) = l6;
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*[register]:$(SIZE) (&w010 + (CWP:4*$(REGWINSZ)+7+$(LOCALOFF))*$(SIZE)) = l7;
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# what was outputs become inputs
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i0 = o0;
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@ -332,7 +332,7 @@ macro save() {
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macro restore() {
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CWP = CWP - 1;
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@if SIZE=="4"
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@if SIZE=="4" || SIZE == "8"
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# inputs once again become outputs
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o0 = i0; # API return value
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o1 = i1;
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@ -343,25 +343,25 @@ macro restore() {
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sp = fp;
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o7 = i7; # address of CALLer address
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# # restore original inputs
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# i0 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+0)*$(SIZE)));
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# i1 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+1)*$(SIZE)));
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# i2 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+2)*$(SIZE)));
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# i3 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+3)*$(SIZE)));
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# i4 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+4)*$(SIZE)));
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# i5 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+5)*$(SIZE)));
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# fp = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+6)*$(SIZE)));
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# i7 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+7)*$(SIZE))); # address of CALLer address
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#
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# # restore original locals
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# l0 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+0+$(LOCALOFF))*$(SIZE)));
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# l1 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+1+$(LOCALOFF))*$(SIZE)));
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# l2 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+2+$(LOCALOFF))*$(SIZE)));
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# l3 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+3+$(LOCALOFF))*$(SIZE)));
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# l4 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+4+$(LOCALOFF))*$(SIZE)));
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# l5 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+5+$(LOCALOFF))*$(SIZE)));
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# l6 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)));
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# l7 = *[register]:$(SIZE) ((&:$(SIZE) w010) + ((CWP*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)));
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# restore original inputs
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i0 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+0)*$(SIZE)));
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i1 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+1)*$(SIZE)));
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i2 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+2)*$(SIZE)));
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i3 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+3)*$(SIZE)));
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i4 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+4)*$(SIZE)));
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i5 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+5)*$(SIZE)));
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fp = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6)*$(SIZE)));
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i7 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+7)*$(SIZE))); # address of CALLer address
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# restore original locals
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l0 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+0+$(LOCALOFF))*$(SIZE)));
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l1 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+1+$(LOCALOFF))*$(SIZE)));
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l2 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+2+$(LOCALOFF))*$(SIZE)));
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l3 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+3+$(LOCALOFF))*$(SIZE)));
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l4 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+4+$(LOCALOFF))*$(SIZE)));
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l5 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+5+$(LOCALOFF))*$(SIZE)));
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l6 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)));
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l7 = *[register]:$(SIZE) ((&w010) + ((CWP:4*$(REGWINSZ)+6+$(LOCALOFF))*$(SIZE)));
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@else
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o0 = i0;
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o1 = i1;
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@ -1067,28 +1067,12 @@ define pcodeop stqa;
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:fabsq fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & opf=0xb & fqrs2 { fqrd = abs(fqrs2); }
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:fadds fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x41 & fsrs2 { fsrd = fsrs1 f+ fsrs2; }
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:faddd fsrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fsrs1 & opf=0x42 & fdrs2
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{
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tmp1:8 = float2float(fsrs1);
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fdrd = tmp1 f+ fdrs2;
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}
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:faddq fsrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fsrs1 & opf=0x43 & fqrs2
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{
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tmp1:16 = float2float(fsrs1);
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fqrd = tmp1 f+ fqrs2;
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}
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:faddd fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x42 & fdrs2 { fdrd = fdrs1 f+ fdrs2; }
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:faddq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x43 & fqrs2 { fqrd = fqrs1 f+ fqrs2; }
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:fdivs fsrs1,fsrs2,fsrd is op=0x2 & fsrd & op3=0x34 & fsrs1 & opf=0x4d & fsrs2 { fsrd = fsrs1 f/ fsrs2; }
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:fdivd fsrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fsrs1 & opf=0x4e & fdrs2
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{
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tmp1:8 = float2float(fsrs1);
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fdrd = tmp1 f/ fdrs2;
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}
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:fdivq fsrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fsrs1 & opf=0x4f & fqrs2
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{
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tmp1:16 = float2float(fsrs1);
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fqrd = tmp1 f/ fqrs2;
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}
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:fdivd fdrs1,fdrs2,fdrd is op=0x2 & fdrd & op3=0x34 & fdrs1 & opf=0x4e & fdrs2 { fdrd = fdrs1 f/ fdrs2; }
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:fdivq fqrs1,fqrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fqrs1 & opf=0x4f & fqrs2 { fqrd = fqrs1 f/ fqrs2; }
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:fdmulq fdrs1,fdrs2,fqrd is op=0x2 & fqrd & op3=0x34 & fdrs1 & opf=0x6e & fdrs2
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{
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@ -8,42 +8,6 @@
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<default_proto>
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<prototype name="__stdcall" extrapop="0" stackshift="0">
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<input>
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<pentry minsize="16" maxsize="16" metatype="float">
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<register name="fq0"/>
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</pentry>
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<pentry minsize="16" maxsize="16" metatype="float">
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<register name="fq4"/>
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</pentry>
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<pentry minsize="16" maxsize="16" metatype="float">
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<register name="fq8"/>
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</pentry>
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<pentry minsize="16" maxsize="16" metatype="float">
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<register name="fq12"/>
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</pentry>
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<pentry minsize="8" maxsize="8" metatype="float">
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<register name="fd0"/>
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</pentry>
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<pentry minsize="8" maxsize="8" metatype="float">
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<register name="fd2"/>
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</pentry>
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<pentry minsize="8" maxsize="8" metatype="float">
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<register name="fd4"/>
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</pentry>
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<pentry minsize="8" maxsize="8" metatype="float">
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<register name="fd6"/>
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</pentry>
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<pentry minsize="4" maxsize="4" metatype="float">
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<register name="fs0"/>
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</pentry>
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<pentry minsize="4" maxsize="4" metatype="float">
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<register name="fs1"/>
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</pentry>
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<pentry minsize="4" maxsize="4" metatype="float">
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<register name="fs2"/>
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</pentry>
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<pentry minsize="4" maxsize="4" metatype="float">
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<register name="fs3"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<register name="o0"/>
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</pentry>
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@ -20,30 +20,18 @@
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<pentry minsize="16" maxsize="16" metatype="float">
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<register name="fq12"/>
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</pentry>
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<pentry minsize="8" maxsize="8" metatype="float">
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<pentry minsize="4" maxsize="8" metatype="float">
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<register name="fd0"/>
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</pentry>
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<pentry minsize="8" maxsize="8" metatype="float">
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<pentry minsize="4" maxsize="8" metatype="float">
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<register name="fd2"/>
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</pentry>
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<pentry minsize="8" maxsize="8" metatype="float">
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<pentry minsize="4" maxsize="8" metatype="float">
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<register name="fd4"/>
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</pentry>
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<pentry minsize="8" maxsize="8" metatype="float">
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<pentry minsize="4" maxsize="8" metatype="float">
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<register name="fd6"/>
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</pentry>
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<pentry minsize="4" maxsize="4" metatype="float">
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<register name="fs0"/>
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</pentry>
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<pentry minsize="4" maxsize="4" metatype="float">
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<register name="fs1"/>
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</pentry>
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<pentry minsize="4" maxsize="4" metatype="float">
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<register name="fs2"/>
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</pentry>
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<pentry minsize="4" maxsize="4" metatype="float">
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<register name="fs3"/>
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</pentry>
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<pentry minsize="1" maxsize="8">
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<register name="o0"/>
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</pentry>
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@ -0,0 +1,40 @@
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/* ###
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* IP: GHIDRA
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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package ghidra.test.processors;
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import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
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import junit.framework.Test;
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public class SparcV9_32_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
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private static final String LANGUAGE_ID = "sparc:BE:32:default";
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private static final String COMPILER_SPEC_ID = "default";
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private static final String[] REG_DUMP_SET = new String[] {};
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public SparcV9_32_O0_EmulatorTest(String name) throws Exception {
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super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
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}
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@Override
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protected String getProcessorDesignator() {
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return "sparcV9_32_GCC_O0";
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}
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public static Test suite() {
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return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(SparcV9_32_O0_EmulatorTest.class);
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}
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}
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@ -0,0 +1,40 @@
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/* ###
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* IP: GHIDRA
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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package ghidra.test.processors;
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import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
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import junit.framework.Test;
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public class SparcV9_32_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
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private static final String LANGUAGE_ID = "sparc:BE:32:default";
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private static final String COMPILER_SPEC_ID = "default";
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private static final String[] REG_DUMP_SET = new String[] {};
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public SparcV9_32_O3_EmulatorTest(String name) throws Exception {
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super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
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}
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@Override
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protected String getProcessorDesignator() {
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return "sparcV9_32_GCC_O3";
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}
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public static Test suite() {
|
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return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(SparcV9_32_O3_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/* ###
|
||||
* IP: GHIDRA
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
package ghidra.test.processors;
|
||||
|
||||
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
|
||||
import junit.framework.Test;
|
||||
|
||||
public class SparcV9_64_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
|
||||
|
||||
private static final String LANGUAGE_ID = "sparc:BE:64:default";
|
||||
private static final String COMPILER_SPEC_ID = "default";
|
||||
|
||||
private static final String[] REG_DUMP_SET = new String[] {};
|
||||
|
||||
public SparcV9_64_O0_EmulatorTest(String name) throws Exception {
|
||||
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
|
||||
}
|
||||
|
||||
@Override
|
||||
protected String getProcessorDesignator() {
|
||||
return "sparcV9_64_GCC_O0";
|
||||
}
|
||||
|
||||
public static Test suite() {
|
||||
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(SparcV9_64_O0_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/* ###
|
||||
* IP: GHIDRA
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
package ghidra.test.processors;
|
||||
|
||||
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
|
||||
import junit.framework.Test;
|
||||
|
||||
public class SparcV9_64_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
|
||||
|
||||
private static final String LANGUAGE_ID = "sparc:BE:64:default";
|
||||
private static final String COMPILER_SPEC_ID = "default";
|
||||
|
||||
private static final String[] REG_DUMP_SET = new String[] {};
|
||||
|
||||
public SparcV9_64_O3_EmulatorTest(String name) throws Exception {
|
||||
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
|
||||
}
|
||||
|
||||
@Override
|
||||
protected String getProcessorDesignator() {
|
||||
return "sparcV9_64_GCC_O3";
|
||||
}
|
||||
|
||||
public static Test suite() {
|
||||
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(SparcV9_64_O3_EmulatorTest.class);
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue