From a7cc025eb969123391d1018878c3f6de395f35f2 Mon Sep 17 00:00:00 2001 From: marcus hall Date: Fri, 12 Jan 2024 10:05:58 -0700 Subject: [PATCH 1/4] Fix branch sense in "bany" instruction. Add special cases for "sext" of bytes. --- .../Xtensa/data/languages/xtensaInstructions.sinc | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc b/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc index 1aa19cb0de..44c303fb7d 100644 --- a/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc +++ b/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc @@ -122,7 +122,7 @@ # BANY - Branch if Any Bit Set, pg. 265. :bany srel_16_23, as, at, is srel_16_23 & ar = 0b1000 & as & at & op0 = 0b0111 { local test:4 = as & at; - if (test == 0) goto srel_16_23; + if (test != 0) goto srel_16_23; } macro extract_bit(bit, result) { @@ -1166,6 +1166,15 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist local tmp:4 = as << shift; ar = tmp s>> shift; } +:sext ar, as, 7 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 0 & op0 = 0 { + ar = sext(as:1); +} +:sext ar, as, 15 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 8 & op0 = 0 { + ar = sext(as:2); +} +:sext ar, as, 23 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 12 & op0 = 0 { + ar = sext(as:3); +} # SICT - Store Instruction Cache Tag, pg. 519. :sict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0001 & as & at & op0 = 0 { From df3726dec748aaddff68b61a8ac52515d5cf4b66 Mon Sep 17 00:00:00 2001 From: marcus hall Date: Fri, 12 Jan 2024 10:39:17 -0700 Subject: [PATCH 2/4] clamps instruction should put result in ar, not just a temporary. --- Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc b/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc index 44c303fb7d..9e7ed1e2b1 100644 --- a/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc +++ b/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc @@ -399,7 +399,7 @@ macro extract_bit(bit, result) { local mt:1 = (x s> (-clamp)); local max:4 = (zext(mt) * x) + (zext(!mt) * (-clamp)); mt = (x s< (clamp-1)); - local y = (zext(mt) * max) + (zext(!mt) * (clamp-1)); + ar = (zext(mt) * max) + (zext(!mt) * (clamp-1)); } # DHI - Data Cache Hit Invalidate, pg. 313. From cb1e1762015a548a06c786f4d7c5c26b7f4a0a47 Mon Sep 17 00:00:00 2001 From: marcus hall Date: Tue, 23 Jan 2024 09:40:19 -0700 Subject: [PATCH 3/4] Remove 3-byte sext special case which isn't really possible. --- .../Processors/Xtensa/data/languages/xtensaInstructions.sinc | 3 --- 1 file changed, 3 deletions(-) diff --git a/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc b/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc index 9e7ed1e2b1..71e23ce294 100644 --- a/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc +++ b/Ghidra/Processors/Xtensa/data/languages/xtensaInstructions.sinc @@ -1172,9 +1172,6 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist :sext ar, as, 15 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 8 & op0 = 0 { ar = sext(as:2); } -:sext ar, as, 23 is op2 = 0b0010 & op1 = 0b0011 & ar & as & u4_4_7 = 12 & op0 = 0 { - ar = sext(as:3); -} # SICT - Store Instruction Cache Tag, pg. 519. :sict at, as is op2 = 0b1111 & op1 = 0b0001 & ar = 0b0001 & as & at & op0 = 0 { From d1f017f92d6ab819903b70e66b53950304b1c044 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Thu, 25 Jan 2024 14:56:43 +0000 Subject: [PATCH 4/4] GP-4254: Updated Xtensa languages to version 4.1 --- Ghidra/Processors/Xtensa/data/languages/xtensa.ldefs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/Xtensa/data/languages/xtensa.ldefs b/Ghidra/Processors/Xtensa/data/languages/xtensa.ldefs index 295fea8ef0..45830597eb 100644 --- a/Ghidra/Processors/Xtensa/data/languages/xtensa.ldefs +++ b/Ghidra/Processors/Xtensa/data/languages/xtensa.ldefs @@ -5,7 +5,7 @@ endian="little" size="32" variant="default" - version="4.0" + version="4.1" slafile="xtensa_le.sla" processorspec="xtensa.pspec" manualindexfile="../manuals/xtensa.idx" @@ -19,7 +19,7 @@ endian="big" size="32" variant="default" - version="4.0" + version="4.1" slafile="xtensa_be.sla" processorspec="xtensa.pspec" manualindexfile="../manuals/xtensa.idx"