diff --git a/Ghidra/Processors/MC6800/data/languages/6x09.sinc b/Ghidra/Processors/MC6800/data/languages/6x09.sinc
index c3ae65406f..4748408cc3 100644
--- a/Ghidra/Processors/MC6800/data/languages/6x09.sinc
+++ b/Ghidra/Processors/MC6800/data/languages/6x09.sinc
@@ -1268,7 +1268,7 @@ macro PushEntireState()
 
 :STU OP2    is (op=0xDF | op=0xEF | op=0xFF) ... & OP2
 {
-        storeRegister(X, OP2);
+        storeRegister(U, OP2);
 }
 
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