diff --git a/Ghidra/Features/Decompiler/certification.manifest b/Ghidra/Features/Decompiler/certification.manifest index e78fc73dc1..1d94dfc743 100644 --- a/Ghidra/Features/Decompiler/certification.manifest +++ b/Ghidra/Features/Decompiler/certification.manifest @@ -41,6 +41,7 @@ src/decompile/datatests/pointersub.xml||GHIDRA||||END| src/decompile/datatests/promotecompare.xml||GHIDRA||||END| src/decompile/datatests/readvolatile.xml||GHIDRA||||END| src/decompile/datatests/sbyte.xml||GHIDRA||||END| +src/decompile/datatests/skipnext2.xml||GHIDRA||||END| src/decompile/datatests/statuscmp.xml||GHIDRA||||END| src/decompile/datatests/threedim.xml||GHIDRA||||END| src/decompile/datatests/twodim.xml||GHIDRA||||END| diff --git a/Ghidra/Features/Decompiler/src/decompile/cpp/context.cc b/Ghidra/Features/Decompiler/src/decompile/cpp/context.cc index d1acbb1649..51157f3a7c 100644 --- a/Ghidra/Features/Decompiler/src/decompile/cpp/context.cc +++ b/Ghidra/Features/Decompiler/src/decompile/cpp/context.cc @@ -17,11 +17,12 @@ #include "slghsymbol.hh" #include "translate.hh" -ParserContext::ParserContext(ContextCache *ccache) +ParserContext::ParserContext(ContextCache *ccache,Translate *trans) { - parsestate = 0; + parsestate = uninitialized; contcache = ccache; + translate = trans; if (ccache != (ContextCache *)0) { contextsize = ccache->getDatabase()->getContextSize(); context = new uintm[ contextsize ]; @@ -43,6 +44,18 @@ void ParserContext::initialize(int4 maxstate,int4 maxparam,AddrSpace *spc) base_state = &state[0]; } +const Address &ParserContext::getN2addr(void) const + +{ + if (n2addr.isInvalid()) { + if (translate == (Translate *)0 || parsestate == uninitialized) + throw LowlevelError("inst_next2 not available in this context"); + int4 length = translate->instructionLength(naddr); + n2addr = naddr + length; + } + return n2addr; +} + uintm ParserContext::getInstructionBytes(int4 bytestart,int4 size,uint4 off) const { // Get bytes from the instruction stream into a intm diff --git a/Ghidra/Features/Decompiler/src/decompile/cpp/context.hh b/Ghidra/Features/Decompiler/src/decompile/cpp/context.hh index 650e1e78dc..8ae7012a69 100644 --- a/Ghidra/Features/Decompiler/src/decompile/cpp/context.hh +++ b/Ghidra/Features/Decompiler/src/decompile/cpp/context.hh @@ -64,6 +64,7 @@ struct ContextSet { // Instructions for setting a global context value class ParserWalker; // Forward declaration class ParserWalkerChange; +class Translate; class ParserContext { friend class ParserWalker; @@ -75,6 +76,7 @@ public: pcode = 2 // Instruction is parsed in preparation for generating p-code }; private: + Translate *translate; // Instruction parser int4 parsestate; AddrSpace *const_space; uint1 buf[16]; // Buffer of bytes in the instruction stream @@ -84,13 +86,14 @@ private: vector contextcommit; Address addr; // Address of start of instruction Address naddr; // Address of next instruction + mutable Address n2addr; // Address of instruction after the next Address calladdr; // For injections, this is the address of the call being overridden vector state; // Current resolved instruction ConstructState *base_state; int4 alloc; // Number of ConstructState's allocated int4 delayslot; // delayslot depth public: - ParserContext(ContextCache *ccache); + ParserContext(ContextCache *ccache,Translate *trans); ~ParserContext(void) { if (context != (uintm *)0) delete [] context; } uint1 *getBuffer(void) { return buf; } void initialize(int4 maxstate,int4 maxparam,AddrSpace *spc); @@ -98,7 +101,7 @@ public: void setParserState(int4 st) { parsestate = st; } void deallocateState(ParserWalkerChange &walker); void allocateOperand(int4 i,ParserWalkerChange &walker); - void setAddr(const Address &ad) { addr = ad; } + void setAddr(const Address &ad) { addr = ad; n2addr = Address(); } void setNaddr(const Address &ad) { naddr = ad; } void setCalladdr(const Address &ad) { calladdr = ad; } void addCommit(TripleSymbol *sym,int4 num,uintm mask,bool flow,ConstructState *point); @@ -106,7 +109,7 @@ public: void applyCommits(void); const Address &getAddr(void) const { return addr; } const Address &getNaddr(void) const { return naddr; } - const Address &getN2addr(void) const { return naddr; /* inst_next2 not supported */ } + const Address &getN2addr(void) const; const Address &getDestAddr(void) const { return calladdr; } const Address &getRefAddr(void) const { return calladdr; } AddrSpace *getCurSpace(void) const { return addr.getSpace(); } diff --git a/Ghidra/Features/Decompiler/src/decompile/cpp/inject_sleigh.cc b/Ghidra/Features/Decompiler/src/decompile/cpp/inject_sleigh.cc index 0229f4ba9b..e37e3f4695 100644 --- a/Ghidra/Features/Decompiler/src/decompile/cpp/inject_sleigh.cc +++ b/Ghidra/Features/Decompiler/src/decompile/cpp/inject_sleigh.cc @@ -333,7 +333,7 @@ void PcodeInjectLibrarySleigh::parseInject(InjectPayload *payload) throw LowlevelError("Registering pcode snippet before language is instantiated"); } if (contextCache.pos == (ParserContext *)0) { // Make sure we have a context - contextCache.pos = new ParserContext((ContextCache *)0); + contextCache.pos = new ParserContext((ContextCache *)0,(Translate *)0); contextCache.pos->initialize(8,8,slgh->getConstantSpace()); } PcodeSnippet compiler(slgh); diff --git a/Ghidra/Features/Decompiler/src/decompile/cpp/sleigh.cc b/Ghidra/Features/Decompiler/src/decompile/cpp/sleigh.cc index 4c06eb5462..0fd86e645b 100644 --- a/Ghidra/Features/Decompiler/src/decompile/cpp/sleigh.cc +++ b/Ghidra/Features/Decompiler/src/decompile/cpp/sleigh.cc @@ -444,7 +444,7 @@ void DisassemblyCache::initialize(int4 min,int4 hashsize) nextfree = 0; hashtable = new ParserContext *[hashsize]; for(int4 i=0;iinitialize(75,20,constspace); list[i] = pos; } @@ -462,13 +462,15 @@ void DisassemblyCache::free(void) delete [] hashtable; } +/// \param trans is the Translate object instantiating this cache (for inst_next2 callbacks) /// \param ccache is the ContextCache front-end shared across all the parser contexts /// \param cspace is the constant address space used for minting constant Varnodes /// \param cachesize is the number of distinct ParserContext objects in this cache /// \param windowsize is the size of the ParserContext hash-table -DisassemblyCache::DisassemblyCache(ContextCache *ccache,AddrSpace *cspace,int4 cachesize,int4 windowsize) +DisassemblyCache::DisassemblyCache(Translate *trans,ContextCache *ccache,AddrSpace *cspace,int4 cachesize,int4 windowsize) { + translate = trans; contextcache = ccache; constspace = cspace; initialize(cachesize,windowsize); // Set default settings for the cache @@ -559,7 +561,7 @@ void Sleigh::initialize(DocumentStorage &store) parser_cachesize = 8; parser_windowsize = 256; } - discache = new DisassemblyCache(cache,getConstantSpace(),parser_cachesize,parser_windowsize); + discache = new DisassemblyCache(this,cache,getConstantSpace(),parser_cachesize,parser_windowsize); } /// \brief Obtain a parse tree for the instruction at the given address diff --git a/Ghidra/Features/Decompiler/src/decompile/cpp/sleigh.hh b/Ghidra/Features/Decompiler/src/decompile/cpp/sleigh.hh index 4a66e77606..74fc5cbf8d 100644 --- a/Ghidra/Features/Decompiler/src/decompile/cpp/sleigh.hh +++ b/Ghidra/Features/Decompiler/src/decompile/cpp/sleigh.hh @@ -103,6 +103,7 @@ public: /// accessing the ContextDatabase and resolving context variables from the SLEIGH spec. /// ParserContext objects are stored in a hash-table keyed by the address of the instruction. class DisassemblyCache { + Translate *translate; ///< The Translate object that owns this cache ContextCache *contextcache; ///< Cached values from the ContextDatabase AddrSpace *constspace; ///< The constant address space int4 minimumreuse; ///< Can call getParserContext this many times, before a ParserContext is reused @@ -113,7 +114,7 @@ class DisassemblyCache { void initialize(int4 min,int4 hashsize); ///< Initialize the hash-table of ParserContexts void free(void); ///< Free the hash-table of ParserContexts public: - DisassemblyCache(ContextCache *ccache,AddrSpace *cspace,int4 cachesize,int4 windowsize); ///< Constructor + DisassemblyCache(Translate *trans,ContextCache *ccache,AddrSpace *cspace,int4 cachesize,int4 windowsize); ///< Constructor ~DisassemblyCache(void) { free(); } ///< Destructor ParserContext *getParserContext(const Address &addr); ///< Get the parser for a particular Address }; diff --git a/Ghidra/Features/Decompiler/src/decompile/datatests/skipnext2.xml b/Ghidra/Features/Decompiler/src/decompile/datatests/skipnext2.xml new file mode 100644 index 0000000000..e152c1e642 --- /dev/null +++ b/Ghidra/Features/Decompiler/src/decompile/datatests/skipnext2.xml @@ -0,0 +1,19 @@ + + + + +0a0acec58000c0abdfcaf400 + + + + +if \(param_1 != 5\) +iVar1 = param_2 \+ 10; + diff --git a/Ghidra/Features/Decompiler/src/main/doc/pcoderef.xml b/Ghidra/Features/Decompiler/src/main/doc/pcoderef.xml index 4921d8d051..52cd43a88b 100644 --- a/Ghidra/Features/Decompiler/src/main/doc/pcoderef.xml +++ b/Ghidra/Features/Decompiler/src/main/doc/pcoderef.xml @@ -1,5 +1,5 @@ -
+
P-Code Reference Manual Last updated September 5, 2019 @@ -184,7 +184,7 @@ longer match their raw p-code form. The core concepts of p-code are: - + Address Space The address space for p-code is a generalization @@ -224,7 +224,7 @@ right byte offset when dereferencing the pointer. The wordsize attribute has no any of the other p-code operations. - + Varnode A varnode is a generalization of @@ -270,7 +270,7 @@ of the constant. As with other varnodes, constants only have a type forced on them by the p-code operations that use them. - + P-code Operation A p-code operation is the analog of a diff --git a/Ghidra/Features/Decompiler/src/main/doc/sleigh.xml b/Ghidra/Features/Decompiler/src/main/doc/sleigh.xml index 03a8753ff3..e9fc067f91 100644 --- a/Ghidra/Features/Decompiler/src/main/doc/sleigh.xml +++ b/Ghidra/Features/Decompiler/src/main/doc/sleigh.xml @@ -1,12 +1,12 @@ -
+
SLEIGH A Language for Rapid Processor Specification Originally published December 16, 2005 - Last updated October 28, 2020 + Last updated August 24, 2022 - + History @@ -36,7 +36,7 @@ - + Overview @@ -70,7 +70,7 @@ will always refer to this target of the specification. Italics are used when defining terms and for named entities. Bold is used for SLEIGH keywords. - + Introduction to P-Code Although p-code is a distinct language from SLEIGH, because a major @@ -128,7 +128,7 @@ the operation. These are generalizations of the computing concepts of RAM, registers, and machine instructions respectively. - + Address Spaces An address space for p-code is a generalization of @@ -227,7 +227,7 @@ different way. Any consistent meaning assigned to a particular varnode must be provided and enforced by the specification designer. - + Operations P-code is intended to emulate a target processor by substituting a @@ -331,7 +331,7 @@ follow a specific format as parsed by the SLEIGH compiler. In this section, we list the basic formatting rules for this file as enforced by the compiler. - + Comments Comments start with the ‘#’ character and continue to the end of the @@ -340,7 +340,7 @@ constructor (see ) where the ‘#’ cha interpreted as something that should be printed in disassembly. - + Identifiers Identifiers are made up of letters a-z, capitals A-Z, digits 0-9 and @@ -348,7 +348,7 @@ the characters ‘.’ and ‘_’. An identifier can use these characters in any order and for any length, but it must not start with a digit. - + Strings String literals can be used, when specifying names and when specifying @@ -358,7 +358,7 @@ character ‘”’ and all characters in between lose their special meaning. - + Integers Integers are specified either in a decimal format or in a standard @@ -383,7 +383,7 @@ be thought of as having arbitrary precision. Currently, SLEIGH stores integers internally with 64 bits of precision. - + White Space White space characters include space, tab, line-feed, vertical @@ -419,7 +419,7 @@ included files can have their own @include directives. - + Preprocessor Macros SLEIGH allows simple (unparameterized) macro definitions and @@ -449,7 +449,7 @@ definition of a macro from that point on in the file. - + Conditional Compilation SLEIGH supports several directives that allow conditional inclusion of @@ -466,7 +466,7 @@ second @if... @endif@if and @endif. - + @ifdef and @ifndef The @ifdef directive is followed by a @@ -491,7 +491,7 @@ an @if or @elif directive (See below). - + @if The @if directive is followed by a @@ -519,7 +519,7 @@ is defined. - + @else and @elif An @else directive splits the lines @@ -583,7 +583,7 @@ endianess when labeling instruction fields and when defining overlapping registe otherwise the specification language hides endianess issues. - + Alignment Definition An alignment definition looks like @@ -599,7 +599,7 @@ the address against this value and can opt to flag an unaligned instruction as an error. - + Space Definitions The definition of an address space looks like @@ -752,7 +752,7 @@ define register offset=0 size=1 - + Bit Range Registers Many processors define registers that either consist of a single bit @@ -822,7 +822,7 @@ the define bitrange statement can be used as an alternate syntax for defining overlapping registers. - + User-Defined Operations The specification designer can define new p-code operations using @@ -933,7 +933,7 @@ can be used in the definition of other table symbols until the root symbol is fully described. The root symbol has the predefined identifier instruction. - + Notes on Namespaces Almost all identifiers live in the same global "scope". The global scope includes @@ -1093,7 +1093,7 @@ manner of repeats and overlaps in the fields so long as they all have different names. - + Fields as Family Symbols Fields are the most basic form of family symbol; they define a natural @@ -1117,7 +1117,7 @@ representation. The default is hexadecimal. [Currently the dec attribute is not supported] - + Attaching Alternate Meanings to Fields The default interpretation of a field is probably the most natural but @@ -1127,7 +1127,7 @@ is used to alter either the display or semantic meaning of fields into the most common (and basic) interpretations. More complex interpretations must be built up out of tables. - + Attaching Registers Probably the most common processor interpretation @@ -1165,7 +1165,7 @@ display meaning. Instead this encoding is flagged as an invalid form of the instruction. - + Attaching Other Integers Sometimes a processor interprets a field as an integer but not the @@ -1186,7 +1186,7 @@ the fieldlist. [Currently SLEIGH does not support unspecified positions in the list using a ‘_’] - + Attaching Names It is possible to just modify the display characteristics of a field @@ -1298,7 +1298,7 @@ associated with it. Most of this chapter is devoted to describing how to define a single constructor. The issues involved in combining multiple constructors into a single table are addressed in . - + The Five Sections of a Constructor A single complex statement in the specification file describes a @@ -1329,7 +1329,7 @@ the syntax typically fits on a single line. We describe each section in turn. - + The Table Header Every constructor must be part of a table, which is the element with @@ -1464,7 +1464,7 @@ assure uniqueness, but for reverse engineering applications there is no such requirement. - + The '^' character The ‘^’ character in the display section is used to separate @@ -1510,7 +1510,7 @@ constructor’s pattern, the subset of possible instruction encodings that the designer wants to match the constructor being defined. - + Constraints The patterns required for processor specifications can almost always @@ -1567,7 +1567,7 @@ all possible. The logical or operator usually requires two or more mask/value style checks to correctly implement. - + Defining Operands and Invoking Subtables The principle way of defining a constructor operand, left undefined @@ -1627,7 +1627,7 @@ grammar’s start symbol. So this link from local to global is simply a statement of the grouping of old symbols into the new constructor. - + Variable Length Instructions There are some additional complexities to designing a specification @@ -1649,7 +1649,7 @@ final length of the instruction. SLEIGH has two operators that are specific to variable length instruction sets and that give the designer control over how tokens fit together. - + The ';' Operator The most important operator for patterns defining variable length @@ -1710,7 +1710,7 @@ order. Also these operators have higher precedence than the ‘;’ operator, so parentheses may be necessary to get the intended meaning. - + The '...' Operator The ellipsis operator ‘...’ is used to satisfy the token matching @@ -1784,7 +1784,7 @@ you need to break up the parsing of an instruction along lines that don’t quite match the assembly. - + Empty Patterns Occasionally there is a need for an empty pattern when building @@ -1793,7 +1793,7 @@ symbol epsilon which has been traditionally used to indicate an empty pattern. - + Advanced Constraints A constraint does not have to be of the form “field = constant”, @@ -2157,7 +2157,7 @@ operation, INT_ADD, where the input varnodes are r1 and r2 and the output varnode is r1. - + Expressions Expressions are built out of symbols and the binary and unary @@ -2171,7 +2171,7 @@ have a precedence, which is used by the SLEIGH compiler to determine the ordering of the final p-code operations. Parentheses can be used within expressions to affect this order. - + Arithmetic, Logical and Boolean Operators For the most part these operators should be familiar to software @@ -2232,7 +2232,7 @@ address if the wordsize attribute is set to something other than one. - + Extension Most processors have instructions that extend small values into big @@ -2253,7 +2253,7 @@ the INT_SEXT operation is invoked with the sext operator. - + Truncation There are two forms of syntax indicating a truncation of the input @@ -2377,7 +2377,7 @@ the offset portion of the address, and to copy the desired value, the ‘*’ operator must have a register space override. - + Managed Code Operations SLEIGH provides basic support for instructions where encoding and context @@ -2437,7 +2437,7 @@ define pcodeop arctan; - + Statements We describe the types of semantic statements that are allowed in SLEIGH. @@ -2506,7 +2506,7 @@ Use of the local keyword is preferred and may be enforced in future compiler versions. - + Storage Statements SLEIGH supports fairly standard storage statement @@ -2536,7 +2536,7 @@ not a byte address if the wordsize attribute is set to something other than one. - + Exports The semantic section doesn’t just specify how to generate p-code for a @@ -2587,7 +2587,7 @@ would in a normal expression (see varnode being modified to be exported as an integer constant. - + Dynamic References The only other operator allowed as part of @@ -2645,7 +2645,7 @@ addressing mode implementations from instruction semantics at higher levels. - + Branching Statements This section discusses statements that generate p-code branching @@ -2875,7 +2875,7 @@ or CALL operation. Skip Instruction Branching -> + Many processors have a conditional-skip-instruction which must branch over the next instruction based upon some condition. The inst_next2 symbol has been provided for this purpose. @@ -3016,7 +3016,7 @@ each followed by a variation which corrects the error. - + Unimplemented Semantics The semantic section must be present for every constructor in the @@ -3173,7 +3173,7 @@ checking, can be used for various tricks in the specification but should generally be avoided. - + Specific Symbol Trees When the SLEIGH parser analyzes an instruction, it starts with the @@ -3259,7 +3259,7 @@ determined by the matching constructor for the op2 table. SLEIGH generates the disassembly and p-code for these encodings by walking the trees. - + Disassembly Trees If the nodes of each tree are replaced with the display information of @@ -3285,7 +3285,7 @@ walking the tree, SLEIGH obtains the final illustrated assembly statements corresponding to the original instruction encodings. - + P-code Trees A similar procedure produces the resulting p-code translation of the @@ -3366,7 +3366,7 @@ calls to other macros. A build directive however should not be used in a macro. - + Build Directives Because the nodes of a specific symbol tree are traversed in a @@ -3420,7 +3420,7 @@ a build directive, followed by the normal action of the instruction. - + Delay Slot Directives For processors with a pipe-lined architecture, multiple instructions @@ -3464,7 +3464,7 @@ by the condition. Because the delayslot directive combines two or more instructions into one, the meaning of the -symbol inst_next and inst_next2 +symbols inst_next and inst_next2 become ambiguous. It is not clear anymore what exactly the “next instruction” is. SLEIGH uses the following conventions for interpreting @@ -3473,11 +3473,12 @@ semantic section, the symbol refers to the address of the instruction after any instructions in the delay slot. However, if it is used in a disassembly action, the inst_next symbol refers to the address of the instruction immediately after the first -instruction, even if there is a delay slot. The use of -the inst_next2 symbol may be inappropriate in -conjunction with delayslot use. While the next instruction address -is identified by inst_next, the length of the -next instruction ignores any delayslots it may have. +instruction, even if there is a delay slot. The use of the +inst_next2 symbol may be inappropriate in conjunction +with delayslot use. While its use of the +next instruction address is identified by inst_next, +the length of the next instruction ignores any delay slots it may have +when computing the value of inst_next2. @@ -3539,7 +3540,7 @@ just another field to use in our bit patterns. It gives us the extra information we need to distinguish between different instructions whose encodings are otherwise the same. - + Basic Use of Context Variables Suppose a processor supports the use of two different sets of @@ -3555,6 +3556,7 @@ define space ram type=ram_space size=4 default; define space register type=register_space size=4; define register offset=0 size=4 [ r0 r1 r2 r3 r4 r5 r6 r7 ]; define register offset=0x100 size=4 [ s0 s1 s2 s3 s4 s5 s6 s7 ]; +define register offset=0x200 size=4 [ statusreg ]; # define context bits (if defined, size must be multiple of 4-bytes) define token instr(16) op=(10,15) rreg1=(7,9) sreg1=(7,9) imm=(0,6) diff --git a/GhidraDocs/languages/html/additionalpcode.html b/GhidraDocs/languages/html/additionalpcode.html index a822ce92c4..cf80077a56 100644 --- a/GhidraDocs/languages/html/additionalpcode.html +++ b/GhidraDocs/languages/html/additionalpcode.html @@ -3,7 +3,7 @@ Additional P-CODE Operations - + @@ -36,7 +36,7 @@ introduced at a later stage by various analysis algorithms.

MULTIEQUAL

- +
@@ -91,7 +91,7 @@ was last executed. All inputs and outputs must be the same size.

INDIRECT

-
+
@@ -152,7 +152,7 @@ to the operation was used or preserved.

PTRADD

-
+
@@ -210,7 +210,7 @@ and stores it in output.

PTRSUB

-
+
@@ -261,7 +261,7 @@ pointer to the subcomponent and stores it in output.

CAST

-
+
@@ -305,7 +305,7 @@ interpretation as a data-type changes at this point.

INSERT

-
+
@@ -373,7 +373,7 @@ to SLEIGH bitrange syntax such as inp

EXTRACT

-
+
diff --git a/GhidraDocs/languages/html/pcodedescription.html b/GhidraDocs/languages/html/pcodedescription.html index 72f367c268..368b4c2178 100644 --- a/GhidraDocs/languages/html/pcodedescription.html +++ b/GhidraDocs/languages/html/pcodedescription.html @@ -4,7 +4,7 @@ P-Code Operation Reference - + @@ -37,7 +37,7 @@ describing semantics in a processor specification file.

COPY

-
+
@@ -78,7 +78,7 @@ input0 and output must be the same.

LOAD

-
+
@@ -149,7 +149,7 @@ correct byte offset into the space.

STORE

-
+
@@ -212,7 +212,7 @@ correct byte offset into the space.

BRANCH

-
+
@@ -272,7 +272,7 @@ with index 8 by specifying a constant destination “address” of

CBRANCH

-
+
@@ -322,7 +322,7 @@ relative branching. See the discussion for the

BRANCHIND

-
+
@@ -364,7 +364,7 @@ relative branching is not possible with BRANCHIND

CALL

-
+
@@ -428,7 +428,7 @@ into the call.

CALLIND

-
+
@@ -482,7 +482,7 @@ the parameters being passed to the logical call.

RETURN

-
+
@@ -534,7 +534,7 @@ subroutine.

PIECE

-
+
@@ -583,7 +583,7 @@ makes up the most significant part of the output.

SUBPIECE

-
+
@@ -634,7 +634,7 @@ truncated.

POPCOUNT

-
+
@@ -678,7 +678,7 @@ count is zero extended into the output varnode.

INT_EQUAL

-
+
@@ -727,7 +727,7 @@ must have a size of 1.

INT_NOTEQUAL

-
+
@@ -776,7 +776,7 @@ and the output must have a size of 1.

INT_LESS

-
+
@@ -824,7 +824,7 @@ same size, and the output must have a size of 1.

INT_SLESS

-
+
@@ -872,7 +872,7 @@ the output must have a size of 1.

INT_LESSEQUAL

-
+
@@ -920,7 +920,7 @@ same size, and the output must have a size of 1.

INT_SLESSEQUAL

-
+
@@ -968,7 +968,7 @@ and the output must have a size of 1.

INT_ZEXT

-
+
@@ -1012,7 +1012,7 @@ size of input.

INT_SEXT

-
+
@@ -1057,7 +1057,7 @@ than the size of input0.

INT_ADD

-
+
@@ -1108,7 +1108,7 @@ and INT_SCARRY.

INT_SUB

-
+
@@ -1159,7 +1159,7 @@ and INT_LESS.

INT_CARRY

-
+
@@ -1208,7 +1208,7 @@ and output must be size 1.

INT_SCARRY

-
+
@@ -1257,7 +1257,7 @@ and output must be size 1.

INT_SBORROW

-
+
@@ -1308,7 +1308,7 @@ is INT_LESS.

INT_2COMP

-
+
@@ -1351,7 +1351,7 @@ be the same size.

INT_NEGATE

-
+
@@ -1393,7 +1393,7 @@ the same size.

INT_XOR

-
+
@@ -1439,7 +1439,7 @@ and input1. Both inputs and output must be the same size.

INT_AND

-
+
@@ -1485,7 +1485,7 @@ output must be the same size.

INT_OR

-
+
@@ -1531,7 +1531,7 @@ output must be the same size.

INT_LEFT

-
+
@@ -1582,7 +1582,7 @@ size. Input1 can be any size.

INT_RIGHT

-
+
@@ -1633,7 +1633,7 @@ the same size. Input1 can be any size.

INT_SRIGHT

-
+
@@ -1686,7 +1686,7 @@ any size.

INT_MULT

-
+
@@ -1737,7 +1737,7 @@ sign-extended to the desired size.

INT_DIV

-
+
@@ -1787,7 +1787,7 @@ the INT_DIV.

INT_REM

-
+
@@ -1838,7 +1838,7 @@ and INT_ADD operations.

INT_SDIV

-
+
@@ -1888,7 +1888,7 @@ be used before the INT_SDIV.

INT_SREM

-
+
@@ -1939,7 +1939,7 @@ and INT_ADD operations.

BOOL_NEGATE

-
+
@@ -1984,7 +1984,7 @@ or false.

BOOL_XOR

-
+
@@ -2034,7 +2034,7 @@ or false.

BOOL_AND

-
+
@@ -2084,7 +2084,7 @@ or false.

BOOL_OR

-
+
@@ -2134,7 +2134,7 @@ or false.

FLOAT_EQUAL

-
+
@@ -2184,7 +2184,7 @@ to false.

FLOAT_NOTEQUAL

-
+
@@ -2234,7 +2234,7 @@ to false.

FLOAT_LESS

-
+
@@ -2284,7 +2284,7 @@ to false.

FLOAT_LESSEQUAL

-
+
@@ -2334,7 +2334,7 @@ to false.

FLOAT_ADD

-
+
@@ -2384,7 +2384,7 @@ occurs, output is set to NaN.

FLOAT_SUB

-
+
@@ -2434,7 +2434,7 @@ occurs, output is set to NaN.

FLOAT_MULT

-
+
@@ -2484,7 +2484,7 @@ occurs, output is set to NaN.

FLOAT_DIV

-
+
@@ -2534,7 +2534,7 @@ occurs, output is set to NaN.

FLOAT_NEG

-
+
@@ -2578,7 +2578,7 @@ to NaN.

FLOAT_ABS

-
+
@@ -2621,7 +2621,7 @@ to NaN.

FLOAT_SQRT

-
+
@@ -2664,7 +2664,7 @@ to NaN.

FLOAT_CEIL

-
+
@@ -2709,7 +2709,7 @@ to NaN.

FLOAT_FLOOR

-
+
@@ -2756,7 +2756,7 @@ to NaN.

FLOAT_ROUND

-
+
@@ -2803,7 +2803,7 @@ to NaN.

FLOAT_NAN

-
+
@@ -2845,7 +2845,7 @@ size 1, and input0 can be any size.

INT2FLOAT

-
+
@@ -2889,7 +2889,7 @@ precision.

FLOAT2FLOAT

-
+
@@ -2935,7 +2935,7 @@ to NaN.

TRUNC

-
+
diff --git a/GhidraDocs/languages/html/pcoderef.html b/GhidraDocs/languages/html/pcoderef.html index 6942d50778..255621d35b 100644 --- a/GhidraDocs/languages/html/pcoderef.html +++ b/GhidraDocs/languages/html/pcoderef.html @@ -4,7 +4,7 @@ P-Code Reference Manual - + @@ -25,13 +25,13 @@

-P-Code Reference Manual

+P-Code Reference Manual

Last updated September 5, 2019

-
+
@@ -215,7 +215,7 @@ The core concepts of p-code are:

-Address Space

+Address Space

The address space for p-code is a generalization of RAM. It is defined simply as an indexed sequence of bytes that can @@ -256,7 +256,7 @@ any of the other p-code operations.

-Varnode

+Varnode

A varnode is a generalization of either a register or a memory location. It is represented by the formal triple: @@ -303,7 +303,7 @@ on them by the p-code operations that use them.

-P-code Operation

+P-code Operation

A p-code operation is the analog of a machine instruction. All p-code operations have the same basic format diff --git a/GhidraDocs/languages/html/pseudo-ops.html b/GhidraDocs/languages/html/pseudo-ops.html index ed99250faa..a95c6d6716 100644 --- a/GhidraDocs/languages/html/pseudo-ops.html +++ b/GhidraDocs/languages/html/pseudo-ops.html @@ -4,7 +4,7 @@ Pseudo P-CODE Operations - + @@ -40,7 +40,7 @@ placed on other p-code operations that all effects must be explicit.

USERDEFINED

-
+
@@ -112,7 +112,7 @@ still have normal data-flow and can be manipulated symbolically.

CPOOLREF

-
+
@@ -174,7 +174,7 @@ of emulation and analysis, are necessarily architecture dependent.

NEW

-
+
diff --git a/GhidraDocs/languages/html/reference.html b/GhidraDocs/languages/html/reference.html index 4711150020..9b694c1549 100644 --- a/GhidraDocs/languages/html/reference.html +++ b/GhidraDocs/languages/html/reference.html @@ -4,7 +4,7 @@ Syntax Reference - + @@ -26,7 +26,7 @@

Syntax Reference

-
+
@@ -45,7 +45,7 @@
LOAD
- +
@@ -68,7 +68,7 @@
* v1
STORE
- +
@@ -153,7 +153,7 @@
*v0 = v1;
INT_LESS
- +
@@ -169,7 +169,7 @@
v0 < v1
INT_SLESS
- +
@@ -185,7 +185,7 @@
v0 s< v1
INT_LESSEQUAL
- +
@@ -201,7 +201,7 @@
v0 <= v1
INT_SLESSEQUAL
- +
@@ -347,7 +347,7 @@
v0 s<= v1
FLOAT_LESS
- +
@@ -363,7 +363,7 @@
v0 f< v1
FLOAT_LESSEQUAL
- +
@@ -454,7 +454,7 @@
v0 f<= v1
NEW
- +
diff --git a/GhidraDocs/languages/html/sleigh.html b/GhidraDocs/languages/html/sleigh.html index a02b507fe4..aede7a2eb4 100644 --- a/GhidraDocs/languages/html/sleigh.html +++ b/GhidraDocs/languages/html/sleigh.html @@ -4,7 +4,7 @@ SLEIGH - + @@ -25,9 +25,9 @@

-SLEIGH

+SLEIGH

A Language for Rapid Processor Specification

-

Last updated October 28, 2020

+

Last updated August 24, 2022

Originally published December 16, 2005

@@ -35,51 +35,51 @@

Table of Contents

-
1. Introduction to P-Code
+
1. Introduction to P-Code
-
1.1. Address Spaces
+
1.1. Address Spaces
1.2. Varnodes
-
1.3. Operations
+
1.3. Operations
2. Basic Specification Layout
-
2.1. Comments
-
2.2. Identifiers
-
2.3. Strings
-
2.4. Integers
-
2.5. White Space
+
2.1. Comments
+
2.2. Identifiers
+
2.3. Strings
+
2.4. Integers
+
2.5. White Space
3. Preprocessing
3.1. Including Files
-
3.2. Preprocessor Macros
-
3.3. Conditional Compilation
+
3.2. Preprocessor Macros
+
3.3. Conditional Compilation
4. Basic Definitions
4.1. Endianess Definition
-
4.2. Alignment Definition
-
4.3. Space Definitions
+
4.2. Alignment Definition
+
4.3. Space Definitions
4.4. Naming Registers
-
4.5. Bit Range Registers
-
4.6. User-Defined Operations
+
4.5. Bit Range Registers
+
4.6. User-Defined Operations
5. Introduction to Symbols
-
5.1. Notes on Namespaces
+
5.1. Notes on Namespaces
5.2. Predefined Symbols
6. Tokens and Fields
6.1. Defining Tokens and Fields
-
6.2. Fields as Family Symbols
-
6.3. Attaching Alternate Meanings to Fields
+
6.2. Fields as Family Symbols
+
6.3. Attaching Alternate Meanings to Fields
6.4. Context Variables
7. Constructors
-
7.1. The Five Sections of a Constructor
-
7.2. The Table Header
+
7.1. The Five Sections of a Constructor
+
7.2. The Table Header
7.3. The Display Section
7.4. The Bit Pattern Section
7.5. Disassembly Actions Section
@@ -87,12 +87,12 @@
7.7. The Semantic Section
7.8. Tables
7.9. P-code Macros
-
7.10. Build Directives
-
7.11. Delay Slot Directives
+
7.10. Build Directives
+
7.11. Delay Slot Directives
8. Using Context
-
8.1. Basic Use of Context Variables
+
8.1. Basic Use of Context Variables
8.2. Local Context Change
8.3. Global Context Change
@@ -101,7 +101,7 @@

-History

+History

This document describes the syntax for the SLEIGH processor specification language, which was developed for the GHIDRA @@ -129,7 +129,7 @@

-Overview

+Overview

SLEIGH is a language for describing the instruction sets of general purpose microprocessors, in order to facilitate the reverse @@ -162,7 +162,7 @@ Italics are used when defining terms and for named entities. Bold is used for SL

-1.Introduction to P-Code

+1.Introduction to P-Code

Although p-code is a distinct language from SLEIGH, because a major purpose of SLEIGH is to specify the translation from machine code to @@ -221,7 +221,7 @@ respectively.

-1.1.Address Spaces

+1.1.Address Spaces

An address space for p-code is a generalization of the indexed memory (RAM) that a typical processor has access to, and @@ -322,7 +322,7 @@ must be provided and enforced by the specification designer.

-1.3.Operations

+1.3.Operations

P-code is intended to emulate a target processor by substituting a sequence of p-code operations for each machine instruction. Thus every @@ -353,7 +353,7 @@ general purpose processor instruction sets. They break up into groups.

Table1.P-code Operations

-
newobject(v0)
+
diff --git a/GhidraDocs/languages/html/sleigh_constructors.html b/GhidraDocs/languages/html/sleigh_constructors.html index 21c175f0fd..a0b5172687 100644 --- a/GhidraDocs/languages/html/sleigh_constructors.html +++ b/GhidraDocs/languages/html/sleigh_constructors.html @@ -4,7 +4,7 @@ 7.Constructors - + @@ -60,7 +60,7 @@ multiple constructors into a single table are addressed in

-7.1.The Five Sections of a Constructor

+7.1.The Five Sections of a Constructor

A single complex statement in the specification file describes a constructor. This statement is always made up of five distinct @@ -92,7 +92,7 @@ in turn.

-7.2.The Table Header

+7.2.The Table Header

Every constructor must be part of a table, which is the element with an actual family symbol identifier associated with it. So each @@ -230,7 +230,7 @@ no such requirement.

-7.3.2.The '^' character

+7.3.2.The '^' character

The ‘^’ character in the display section is used to separate identifiers from other characters where there shouldn’t be white space @@ -278,7 +278,7 @@ to match the constructor being defined.

-7.4.1.Constraints

+7.4.1.Constraints

The patterns required for processor specifications can almost always be described as a mask and value pair. Given a specific instruction @@ -337,7 +337,7 @@ requires two or more mask/value style checks to correctly implement.

-7.4.3.Defining Operands and Invoking Subtables

+7.4.3.Defining Operands and Invoking Subtables

The principle way of defining a constructor operand, left undefined from the display section, is done in the bit pattern section. If an @@ -396,7 +396,7 @@ statement of the grouping of old symbols into the new constructor.

-7.4.4.Variable Length Instructions

+7.4.4.Variable Length Instructions

There are some additional complexities to designing a specification for a processor with variable length instructions. Some initial @@ -419,7 +419,7 @@ designer control over how tokens fit together.

-7.4.4.1.The ';' Operator
+7.4.4.1.The ';' Operator

The most important operator for patterns defining variable length instructions is the concatenation operator ‘;’. When building a @@ -481,7 +481,7 @@ operator, so parentheses may be necessary to get the intended meaning.

-7.4.4.2.The '...' Operator
+7.4.4.2.The '...' Operator

The ellipsis operator ‘...’ is used to satisfy the token matching requirements of the ‘&’ and ‘|’ operators (described in the previous @@ -557,7 +557,7 @@ don’t quite match the assembly.

-7.4.6.Empty Patterns

+7.4.6.Empty Patterns

Occasionally there is a need for an empty pattern when building tables. An empty pattern matches everything. There is a predefined @@ -567,7 +567,7 @@ to indicate an empty pattern.

-7.4.7.Advanced Constraints

+7.4.7.Advanced Constraints

A constraint does not have to be of the form “field = constant”, although this is almost always what is needed. In certain situations, @@ -593,7 +593,7 @@ the following:

Table3.Constraint Operators

-
+
@@ -720,7 +720,7 @@ is built up out of the following typical operators:

Table4.Pattern Expression Operators

-
+
@@ -756,7 +756,7 @@ is built up out of the following typical operators:
Bitwise and
- +
@@ -771,7 +771,7 @@ is built up out of the following typical operators:
$and
Bitwise or
- +
@@ -786,7 +786,7 @@ is built up out of the following typical operators:
$or
Bitwise xor
- +
@@ -939,7 +939,7 @@ varnode is r1.

-7.7.1.Expressions

+7.7.1.Expressions

Expressions are built out of symbols and the binary and unary operators listed in Table5, “Semantic Expression Operators and Syntax” in the @@ -954,7 +954,7 @@ within expressions to affect this order.

-7.7.1.1.Arithmetic, Logical and Boolean Operators
+7.7.1.1.Arithmetic, Logical and Boolean Operators

For the most part these operators should be familiar to software developers. The only real differences arise from the fact that @@ -1017,7 +1017,7 @@ set to something other than one.

-7.7.1.3.Extension
+7.7.1.3.Extension

Most processors have instructions that extend small values into big values, and many instructions do these minor data manipulations @@ -1039,7 +1039,7 @@ the sext operator.

-7.7.1.4.Truncation
+7.7.1.4.Truncation

There are two forms of syntax indicating a truncation of the input varnode. In one the varnode is followed by a colon ‘:’ and an integer @@ -1119,7 +1119,7 @@ these are automatically set to zero.

This operator can also be used on the left-hand side of assignments -with similar behavior and caveats (see Section7.7.2.7, “Bit Range Assignments”). +with similar behavior and caveats (see Section7.7.2.8, “Bit Range Assignments”).

@@ -1169,7 +1169,7 @@ the offset portion of the address, and to copy the desired value, the
-7.7.1.7.Managed Code Operations
+7.7.1.7.Managed Code Operations

SLEIGH provides basic support for instructions where encoding and context don't provide a complete description of the semantics. This is the case @@ -1231,7 +1231,7 @@ define pcodeop arctan;

-7.7.2.Statements

+7.7.2.Statements

We describe the types of semantic statements that are allowed in SLEIGH.

@@ -1305,7 +1305,7 @@ and may be enforced in future compiler versions.
-7.7.2.2.Storage Statements
+7.7.2.2.Storage Statements

SLEIGH supports fairly standard storage statement syntax to complement the load operator. The left-hand side of an @@ -1336,7 +1336,7 @@ attribute is set to something other than one.

-7.7.2.3.Exports
+7.7.2.3.Exports

The semantic section doesn’t just specify how to generate p-code for a constructor. Except for those constructors in the root table, this @@ -1388,7 +1388,7 @@ varnode being modified to be exported as an integer constant.

-7.7.2.4.Dynamic References
+7.7.2.4.Dynamic References

The only other operator allowed as part of an export statement, is the ‘*’ @@ -1447,7 +1447,7 @@ levels.

-7.7.2.5.Branching Statements
+7.7.2.5.Branching Statements

This section discusses statements that generate p-code branching operations. These are listed in Table7, “Branching Statements”, in the Appendix. @@ -1677,7 +1677,28 @@ or CALL operation.

-7.7.2.7.Bit Range Assignments
+7.7.2.7.Skip Instruction Branching
+

+Many processors have a conditional-skip-instruction which must branch over the next instruction +based upon some condition. The inst_next2 symbol has been provided for +this purpose. +

+
+:skip.eq is opcode=10 {
+    if (zeroflag!=0) goto inst_next2;
+}
+
+

+

+

+In the example above, the branch address will be determined by adding the parsed-length of the next +instruction to the value of inst_next causing a branch over the next +instruction when the condition is satisfied. +

+ +
+
+7.7.2.8.Bit Range Assignments

The bit range operator can appear on the left-hand side of an assignment. But as with the ‘*’ operator, its meaning is slightly @@ -1802,7 +1823,7 @@ each followed by a variation which corrects the error.

-7.7.4.Unimplemented Semantics

+7.7.4.Unimplemented Semantics

The semantic section must be present for every constructor in the specification. But the designer can leave the semantics explicitly @@ -1962,7 +1983,7 @@ should generally be avoided.

-7.8.2.Specific Symbol Trees

+7.8.2.Specific Symbol Trees

When the SLEIGH parser analyzes an instruction, it starts with the root symbol instruction, and decides which of the @@ -2045,7 +2066,7 @@ and p-code for these encodings by walking the trees.

-7.8.2.1.Disassembly Trees
+7.8.2.1.Disassembly Trees

If the nodes of each tree are replaced with the display information of the corresponding specific symbol, we see how the disassembly @@ -2068,7 +2089,7 @@ statements corresponding to the original instruction encodings.

-7.8.2.2.P-code Trees
+7.8.2.2.P-code Trees

A similar procedure produces the resulting p-code translation of the instruction. If each node in the specific symbol tree is replaced with @@ -2147,7 +2168,7 @@ directive however should not be used in a macro.

-7.10.Build Directives

+7.10.Build Directives

Because the nodes of a specific symbol tree are traversed in a depth-first order, the p-code for a child node in general comes before @@ -2202,7 +2223,7 @@ normal action of the instruction.

-7.11.Delay Slot Directives

+7.11.Delay Slot Directives

For processors with a pipe-lined architecture, multiple instructions are typically executing simultaneously. This can lead to processor @@ -2245,7 +2266,8 @@ by the condition.

Because the delayslot directive combines two or more instructions into one, the meaning of the -symbol inst_next becomes ambiguous. It is not +symbols inst_next and inst_next2 +become ambiguous. It is not clear anymore what exactly the “next instruction” is. SLEIGH uses the following conventions for interpreting an inst_next symbol. If it is used in the @@ -2253,7 +2275,12 @@ semantic section, the symbol refers to the address of the instruction after any instructions in the delay slot. However, if it is used in a disassembly action, the inst_next symbol refers to the address of the instruction immediately after the first -instruction, even if there is a delay slot. +instruction, even if there is a delay slot. The use of the +inst_next2 symbol may be inappropriate in conjunction +with delayslot use. While its use of the +next instruction address is identified by inst_next, +the length of the next instruction ignores any delay slots it may have +when computing the value of inst_next2.

diff --git a/GhidraDocs/languages/html/sleigh_context.html b/GhidraDocs/languages/html/sleigh_context.html index ec56ddae6f..f81ef1e33c 100644 --- a/GhidraDocs/languages/html/sleigh_context.html +++ b/GhidraDocs/languages/html/sleigh_context.html @@ -4,7 +4,7 @@ 8.Using Context - + @@ -85,7 +85,7 @@ whose encodings are otherwise the same.

-8.1.Basic Use of Context Variables

+8.1.Basic Use of Context Variables

Suppose a processor supports the use of two different sets of registers in its main addressing mode, based on the setting of a @@ -100,7 +100,7 @@ define space ram type=ram_space size=4 default; define space register type=register_space size=4; define register offset=0 size=4 [ r0 r1 r2 r3 r4 r5 r6 r7 ]; define register offset=0x100 size=4 [ s0 s1 s2 s3 s4 s5 s6 s7 ]; -define register offset=0x200 size=4 [ contextreg ]; # define context bits (if defined, size must be multiple of 4-bytes) +define register offset=0x200 size=4 [ statusreg ]; # define context bits (if defined, size must be multiple of 4-bytes) define token instr(16) op=(10,15) rreg1=(7,9) sreg1=(7,9) imm=(0,6) diff --git a/GhidraDocs/languages/html/sleigh_definitions.html b/GhidraDocs/languages/html/sleigh_definitions.html index 96265a83e0..35518b8016 100644 --- a/GhidraDocs/languages/html/sleigh_definitions.html +++ b/GhidraDocs/languages/html/sleigh_definitions.html @@ -4,7 +4,7 @@ 4.Basic Definitions - + @@ -56,7 +56,7 @@ otherwise the specification language hides endianess issues.

-4.2.Alignment Definition

+4.2.Alignment Definition

An alignment definition looks like

@@ -73,7 +73,7 @@ instruction as an error.

-4.3.Space Definitions

+4.3.Space Definitions

The definition of an address space looks like

@@ -228,7 +228,7 @@ define register offset=0 size=1

-4.5.Bit Range Registers

+4.5.Bit Range Registers

Many processors define registers that either consist of a single bit or otherwise don't use an integral number of bytes. A recurring @@ -299,7 +299,7 @@ used as an alternate syntax for defining overlapping registers.

-4.6.User-Defined Operations

+4.6.User-Defined Operations

The specification designer can define new p-code operations using a define pcodeop statement. This diff --git a/GhidraDocs/languages/html/sleigh_layout.html b/GhidraDocs/languages/html/sleigh_layout.html index 8b641bacdf..56a4acb225 100644 --- a/GhidraDocs/languages/html/sleigh_layout.html +++ b/GhidraDocs/languages/html/sleigh_layout.html @@ -4,7 +4,7 @@ 2.Basic Specification Layout - + @@ -36,7 +36,7 @@ by the compiler.

-2.1.Comments

+2.1.Comments

Comments start with the ‘#’ character and continue to the end of the line. Comments can appear anywhere except the display section of a @@ -46,7 +46,7 @@ interpreted as something that should be printed in disassembly.

-2.2.Identifiers

+2.2.Identifiers

Identifiers are made up of letters a-z, capitals A-Z, digits 0-9 and the characters ‘.’ and ‘_’. An identifier can use these characters in @@ -55,7 +55,7 @@ any order and for any length, but it must not start with a digit.

-2.3.Strings

+2.3.Strings

String literals can be used, when specifying names and when specifying how disassembly should be printed, so that special characters are @@ -66,7 +66,7 @@ meaning.

-2.4.Integers

+2.4.Integers

Integers are specified either in a decimal format or in a standard C-style hexadecimal format by prepending the @@ -92,7 +92,7 @@ integers internally with 64 bits of precision.

-2.5.White Space

+2.5.White Space

White space characters include space, tab, line-feed, vertical line-feed, and carriage-return (‘ ‘, ‘\t’, ‘\r’, ‘\v’, diff --git a/GhidraDocs/languages/html/sleigh_preprocessing.html b/GhidraDocs/languages/html/sleigh_preprocessing.html index 5f47bc64bc..23ecfe588d 100644 --- a/GhidraDocs/languages/html/sleigh_preprocessing.html +++ b/GhidraDocs/languages/html/sleigh_preprocessing.html @@ -4,7 +4,7 @@ 3.Preprocessing - + @@ -54,7 +54,7 @@ own @include directives.

-3.2.Preprocessor Macros

+3.2.Preprocessor Macros

SLEIGH allows simple (unparameterized) macro definitions and expansions. A macro definition occurs on one line and starts with @@ -85,7 +85,7 @@ definition of a macro from that point on in the file.

-3.3.Conditional Compilation

+3.3.Conditional Compilation

SLEIGH supports several directives that allow conditional inclusion of parts of a specification, based on the existence of a macro, or its @@ -103,7 +103,7 @@ and @endif.

-3.3.1.@ifdef and @ifndef

+3.3.1.@ifdef and @ifndef

The @ifdef directive is followed by a macro identifier and evaluates to true if the macro is defined. @@ -129,7 +129,7 @@ or @elif directive (See below).

-3.3.2.@if

+3.3.2.@if

The @if directive is followed by a boolean expression with macros as the variables and strings as the @@ -158,7 +158,7 @@ is defined.

-3.3.3.@else and @elif

+3.3.3.@else and @elif

An @else directive splits the lines bounded by an @if directive and diff --git a/GhidraDocs/languages/html/sleigh_ref.html b/GhidraDocs/languages/html/sleigh_ref.html index d2a54cd534..4914495b49 100644 --- a/GhidraDocs/languages/html/sleigh_ref.html +++ b/GhidraDocs/languages/html/sleigh_ref.html @@ -4,7 +4,7 @@ 9.P-code Tables - + @@ -47,7 +47,7 @@ to lowest.

Table5.Semantic Expression Operators and Syntax

-
$xor
+
@@ -61,7 +61,7 @@ to lowest.
SUBPIECE
- +
@@ -98,7 +98,7 @@ to lowest.
v0:2
LOAD
- +
@@ -214,7 +214,7 @@ to lowest.
* v1
INT_SLESS
- +
@@ -230,7 +230,7 @@ to lowest.
v0 s< v1
INT_SLESSEQUAL
- +
@@ -246,7 +246,7 @@ to lowest.
v0 s<= v1
INT_LESS
- +
@@ -262,7 +262,7 @@ to lowest.
v0 < v1
INT_LESSEQUAL
- +
@@ -278,7 +278,7 @@ to lowest.
v0 <= v1
FLOAT_LESS
- +
@@ -294,7 +294,7 @@ to lowest.
v0 f< v1
FLOAT_LESSEQUAL
- +
@@ -454,7 +454,7 @@ The following table lists the basic forms of a semantic statement.

Table6.Basic Statements and Associated Operators

-
v0 f<= v1
+
@@ -473,7 +473,7 @@ The following table lists the basic forms of a semantic statement.
STORE
- +
@@ -533,7 +533,7 @@ The following table lists the branching operations and the statements which invo

Table7.Branching Statements

-
*v0 = v1
+
diff --git a/GhidraDocs/languages/html/sleigh_symbols.html b/GhidraDocs/languages/html/sleigh_symbols.html index a3ab15203c..f1915438ba 100644 --- a/GhidraDocs/languages/html/sleigh_symbols.html +++ b/GhidraDocs/languages/html/sleigh_symbols.html @@ -4,7 +4,7 @@ 5.Introduction to Symbols - + @@ -105,7 +105,7 @@ the predefined identifier instruction.

-5.1.Notes on Namespaces

+5.1.Notes on Namespaces

Almost all identifiers live in the same global "scope". The global scope includes

@@ -150,7 +150,7 @@ We list all of the symbols that are predefined by SLEIGH.

Table2.Predefined Symbols

-
+
@@ -178,6 +178,10 @@ We list all of the symbols that are predefined by SLEIGH. + + + + @@ -194,7 +198,8 @@ and inst_next. These are family symbols w in the context of particular instruction to the integer offset of either the address of the instruction or the address of the next instruction respectively. These are used in any relative branching -situation. The other symbols are rarely +situation. The inst_next2 is intended for conditional +skip instruction situations. The remaining symbols are rarely used. The const and unique identifiers are address spaces. The epsilon identifier is inherited from SLED and is a specific symbol equivalent diff --git a/GhidraDocs/languages/html/sleigh_tokens.html b/GhidraDocs/languages/html/sleigh_tokens.html index dc572dfdb4..1ba4902e6e 100644 --- a/GhidraDocs/languages/html/sleigh_tokens.html +++ b/GhidraDocs/languages/html/sleigh_tokens.html @@ -4,7 +4,7 @@ 6.Tokens and Fields - + @@ -88,7 +88,7 @@ different names.

-6.2.Fields as Family Symbols

+6.2.Fields as Family Symbols

Fields are the most basic form of family symbol; they define a natural map from instruction bits to a specific symbol as follows. We take the @@ -113,7 +113,7 @@ the dec attribute is not supported]

-6.3.Attaching Alternate Meanings to Fields

+6.3.Attaching Alternate Meanings to Fields

The default interpretation of a field is probably the most natural but of course processors interpret fields within an instruction in a wide @@ -124,7 +124,7 @@ interpretations must be built up out of tables.

-6.3.1.Attaching Registers

+6.3.1.Attaching Registers

Probably the most common processor interpretation of a field is as an encoding of a particular register. In SLEIGH this @@ -163,7 +163,7 @@ of the instruction.

-6.3.2.Attaching Other Integers

+6.3.2.Attaching Other Integers

Sometimes a processor interprets a field as an integer but not the integer given by the default interpretation. A different integer @@ -185,7 +185,7 @@ unspecified positions in the list using a ‘_’]

-6.3.3.Attaching Names

+6.3.3.Attaching Names

It is possible to just modify the display characteristics of a field without changing the semantic meaning. The need for this is rare, but

inst_next Offset of the address of the next instruction.
inst_next2Offset of the address of the instruction after the next instruction.
epsilon A special identifier indicating an empty bit pattern.