From d4093681909e15ece3b8f45ef367dc013b09a5a6 Mon Sep 17 00:00:00 2001 From: Andrew Strelsky Date: Wed, 19 Jan 2022 18:06:14 -0500 Subject: [PATCH] added missing x86 ffreep instruction --- Ghidra/Processors/x86/data/languages/ia.sinc | 1 + 1 file changed, 1 insertion(+) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index a04ddb97bf..1de3e13630 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -4123,6 +4123,7 @@ define pcodeop fcos; :FIDIVR spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=7 ... & spec_m16 { ST0 = int2float(spec_m16) f/ ST0; } :FFREE freg is vexMode=0 & byte=0xDD; frow=12 & fpage=0 & freg { } # Set freg to invalid value +:FFREEP freg is vexMode=0 & byte=0xDF; frow=12 & fpage=0 & freg { fpop(); } # FFREE and pop :FICOM spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=2 ... & spec_m16 { local tmp = int2float(spec_m16); fcom(tmp); } :FICOM spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=2 ... & spec_m32 { local tmp = int2float(spec_m32); fcom(tmp); }