From 6581ff6230cc76b311f3a572e8e443af83b93e2a Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Tue, 7 Jun 2022 18:21:20 +0000 Subject: [PATCH] GP-2112: Fix issue with MSP430 RPT using correct operands --- Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc b/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc index f0b34c2313..bcfb538249 100644 --- a/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc +++ b/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc @@ -5,7 +5,7 @@ # The original way of using sub-tables to breakout the addressing modes does not # work for these instructions -:^instruction is opext_11_5=0x3 & ctx_haveext=0 & dest_0_4 & src_ext & al & zc; instruction [ ctx_haveext=1; ctx_ctregdest=dest_0_4; ctx_regsrc=src_ext; ctx_al=al;] {$(CARRY)=$(CARRY) * (zc:1 == 0); build instruction;} +:^instruction is opext_11_5=0x3 & ctx_haveext=0 & dest_0_4 & src_ext & al & zc & ad; instruction [ ctx_haveext=1; ctx_ctregdest=dest_0_4; ctx_regsrc=src_ext; ctx_al=al; ctx_num=ad; ] {$(CARRY)=$(CARRY) * (zc:1 == 0); build instruction;} #:^instruction is ctx_haveext=1 & instruction & as=1 & src_8_4=3 [ctx_haveext=2;] {build instruction;}