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Code Issues Releases Wiki Activity

Move segmentop tag into the pspec

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This commit is contained in:
caheckman 2019-08-23 15:09:07 -04:00
parent 8240d3c8db
commit d9ad00e9ca
8 changed files with 91 additions and 67 deletions
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29
Ghidra/Features/Decompiler/src/decompile/cpp/architecture.cc
View file

@ -962,32 +962,35 @@ void Architecture::parseProcessorConfig(DocumentStorage &store)
List::const_iterator iter;
for(iter=list.begin();iter!=list.end();++iter) {
if ((*iter)->getName() == "programcounter") {
const string &elname( (*iter)->getName() );
if (elname == "programcounter") {
}
else if ((*iter)->getName() == "volatile")
else if (elname == "volatile")
parseVolatile(*iter);
else if ((*iter)->getName() == "incidentalcopy")
else if (elname == "incidentalcopy")
parseIncidentalCopy(*iter);
else if ((*iter)->getName() == "context_data")
else if (elname == "context_data")
context->restoreFromSpec(*iter,this);
else if ((*iter)->getName() == "jumpassist")
else if (elname == "jumpassist")
userops.parseJumpAssist(*iter, this);
else if ((*iter)->getName() == "register_data") {
else if (elname == "segmentop")
userops.parseSegmentOp(*iter,this);
else if (elname == "register_data") {
}
else if ((*iter)->getName() == "segmented_address") {
else if (elname == "segmented_address") {
}
else if ((*iter)->getName() == "default_symbols") {
else if (elname == "default_symbols") {
}
else if ((*iter)->getName() == "default_memory_blocks") {
else if (elname == "default_memory_blocks") {
}
else if ((*iter)->getName() == "address_shift_amount") {
else if (elname == "address_shift_amount") {
}
else if ((*iter)->getName() == "properties") {
else if (elname == "properties") {
}
else if ((*iter)->getName() == "data_space") {
else if (elname == "data_space") {
}
else
throw LowlevelError("Unknown element in <processor_spec>: "+(*iter)->getName());
throw LowlevelError("Unknown element in <processor_spec>: "+elname);
}
}

46
Ghidra/Framework/SoftwareModeling/data/languages/compiler_spec.rxg
View file

@ -229,35 +229,7 @@
</zeroOrMore>
<zeroOrMore>
<element name="segmentop">
<attribute name="space"/>
<optional> <attribute name="userop"/> </optional>
<optional> <attribute name="baseinsize"/> </optional>
<optional> <attribute name="innerinsize"/> </optional>
<optional> <attribute name="farpointer"/> </optional>
<optional>
<attribute name="force">
<ref name="boolean_type"/>
</attribute>
</optional>
<interleave>
<zeroOrMore>
<element name="baseop">
<ref name="segment_op_type"/>
</element>
</zeroOrMore>
<zeroOrMore>
<element name="innerop">
<ref name="segment_op_type"/>
</element>
</zeroOrMore>
<optional>
<element name="constresolve">
<ref name="varnode_tags_type"/>
</element>
</optional>
</interleave>
</element>
<ref name="segmentop_type"/>
</zeroOrMore>
<element name="default_proto">
@ -299,22 +271,6 @@
</element>
</start>
<define name="segment_op_type">
<attribute name="code">
<choice>
<value type="string">INT_ZEXT</value>
<value type="string">INT_LEFT</value>
<value type="string">INT_AND</value>
</choice>
</attribute>
<optional>
<attribute name="value"/>
</optional>
<optional>
<attribute name="slot"/>
</optional>
</define>
<define name="pentry_type">
<optional> <attribute name="maxsize"/> </optional>
<optional> <attribute name="minsize"/> </optional>

48
Ghidra/Framework/SoftwareModeling/data/languages/language_common.rxg
View file

@ -226,6 +226,54 @@
</element>
</optional>
</define>
<define name="segment_op_type">
<attribute name="code">
<choice>
<value type="string">INT_ZEXT</value>
<value type="string">INT_LEFT</value>
<value type="string">INT_AND</value>
</choice>
</attribute>
<optional>
<attribute name="value"/>
</optional>
<optional>
<attribute name="slot"/>
</optional>
</define>
<define name="segmentop_type">
<element name="segmentop">
<attribute name="space"/>
<optional> <attribute name="userop"/> </optional>
<optional> <attribute name="baseinsize"/> </optional>
<optional> <attribute name="innerinsize"/> </optional>
<optional> <attribute name="farpointer"/> </optional>
<optional>
<attribute name="force">
<ref name="boolean_type"/>
</attribute>
</optional>
<interleave>
<zeroOrMore>
<element name="baseop">
<ref name="segment_op_type"/>
</element>
</zeroOrMore>
<zeroOrMore>
<element name="innerop">
<ref name="segment_op_type"/>
</element>
</zeroOrMore>
<optional>
<element name="constresolve">
<ref name="varnode_tags_type"/>
</element>
</optional>
</interleave>
</element>
</define>
<define name="jumpassist_type">
<attribute name="name"/>

4
Ghidra/Framework/SoftwareModeling/data/languages/processor_spec.rxg
View file

@ -49,6 +49,10 @@
</element>
</optional>
<zeroOrMore>
<ref name="segmentop_type"/>
</zeroOrMore>
<!-- see language_common.rxg -->
<optional>
<element name="context_data">

7
Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/app/plugin/processors/sleigh/SleighLanguage.java
View file

@ -604,7 +604,7 @@ public class SleighLanguage implements Language {
XmlElement element = parser.start("processor_spec");
while (!parser.peek().isEnd()) {
element = parser.start("properties", "segmented_address", "programcounter",
element = parser.start("properties", "segmented_address", "segmentop", "programcounter",
"data_space", "context_data", "volatile", "jumpassist", "incidentalcopy",
"register_data", "default_symbols", "default_memory_blocks");
if (element.getName().equals("properties")) {
@ -774,6 +774,11 @@ public class SleighLanguage implements Language {
parser.discardSubTree();
}
}
else if (element.getName().equals("segmentop")) {
while (parser.peek().isStart()) {
parser.discardSubTree();
}
}
// get rid of the end tag of whatever we started with at the top of the while
parser.end(element);
}

8
Ghidra/Processors/x86/data/languages/x86-16-real.pspec
View file

@ -7,6 +7,14 @@
</properties>
<programcounter register="EIP"/>
<segmented_address space="ram" type="real" />
<segmentop space="ram" userop="segment" baseinsize="2" innerinsize="2" farpointer="yes">
<baseop code="INT_ZEXT"/>
<baseop code="INT_LEFT" value="4"/>
<innerop code="INT_ZEXT"/>
<constresolve>
<register name="DS"/>
</constresolve>
</segmentop>
<context_data>
<context_set space="ram">
<set name="addrsize" val="0"/>

8
Ghidra/Processors/x86/data/languages/x86-16.cspec
View file

@ -31,14 +31,6 @@
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram"/>
<segmentop space="ram" userop="segment" baseinsize="2" innerinsize="2" farpointer="yes">
<baseop code="INT_ZEXT"/>
<baseop code="INT_LEFT" value="4"/>
<innerop code="INT_ZEXT"/>
<constresolve>
<register name="DS"/>
</constresolve>
</segmentop>
<default_proto>
<prototype name="__stdcall16near" extrapop="unknown" stackshift="2">
<input>

8
Ghidra/Processors/x86/data/languages/x86-16.pspec
View file

@ -8,6 +8,14 @@
</properties>
<programcounter register="EIP"/>
<segmented_address space="ram" type="protected"/>
<segmentop space="ram" userop="segment" baseinsize="2" innerinsize="2" farpointer="yes">
<baseop code="INT_ZEXT"/>
<baseop code="INT_LEFT" value="16"/>
<innerop code="INT_ZEXT"/>
<constresolve>
<register name="DS"/>
</constresolve>
</segmentop>
<context_data>
<context_set space="ram">
<set name="addrsize" val="0"/>