From f555d0dcb7b12f2c026ffa48f5bcc6901c1a4a54 Mon Sep 17 00:00:00 2001 From: Antonio Flores Montoya Date: Thu, 15 Jul 2021 14:15:03 -0400 Subject: [PATCH] fix vfnma 32 bits and make all part of vfpv4 --- .../ARM/data/languages/ARM7_be.slaspec | 1 + .../ARM/data/languages/ARM7_le.slaspec | 1 + .../ARM/data/languages/ARM8_be.slaspec | 1 + .../ARM/data/languages/ARM8_le.slaspec | 1 + .../ARM/data/languages/ARMneon.sinc | 20 +++++++++---------- 5 files changed, 14 insertions(+), 10 deletions(-) diff --git a/Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec b/Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec index 896066e764..768216ad68 100644 --- a/Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec +++ b/Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec @@ -10,6 +10,7 @@ @define VERSION_7M "" @define SIMD "" @define VFPv3 "" +@define VFPv4 "" @include "ARM.sinc" diff --git a/Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec b/Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec index e2df6c39bf..965278c343 100644 --- a/Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec +++ b/Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec @@ -10,6 +10,7 @@ @define VERSION_7M "" @define SIMD "" @define VFPv3 "" +@define VFPv4 "" @include "ARM.sinc" diff --git a/Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec b/Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec index 7153663498..62d990b1a6 100644 --- a/Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec +++ b/Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec @@ -11,6 +11,7 @@ @define VERSION_8 "" @define SIMD "" @define VFPv3 "" +@define VFPv4 "" @include "ARM.sinc" diff --git a/Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec b/Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec index 6eda33d98a..8765268389 100644 --- a/Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec +++ b/Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec @@ -11,6 +11,7 @@ @define VERSION_8 "" @define SIMD "" @define VFPv3 "" +@define VFPv4 "" @include "ARM.sinc" diff --git a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc index fe3c42ae3e..7040a82a1f 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc @@ -1818,7 +1818,7 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; } # VFMA VFMS VFNMA and VFNMS # -@if defined(VFPv2) || defined(VFPv3) +@if defined(VFPv4) :vfma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c0811=10 & c0606=0 & c0404=0 ) | ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd @@ -1844,31 +1844,31 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; } Dd = Dd f- (Dn f* Dm); } -:vfnma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=10 & c0606=0 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd +:vfnma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=10 & c0606=1 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=10 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd { Sd = Sd f+ ((0 f- Sn) f* Sm); } -:vfnma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=11 & c0606=0 & c0404=0) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd +:vfnma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=11 & c0606=1 & c0404=0) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd { Dd = Dd f+ ((0 f- Dn) f* Dm); } -:vfnms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=10 & c0606=1 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd +:vfnms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=10 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=10 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd { Sd = Sd f- ((0 f- Sn) f* Sm); } -:vfnms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=11 & c0606=1 & c0404=0 ) | - ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=11 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd +:vfnms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c0811=11 & c0606=0 & c0404=0 ) | + ($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c0811=11 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd { Dd = Dd f- ((0 f- Dn) f* Dm); } -@endif # VFPv2 || VFPv3 +@endif # VFPv4 ####### # VLD1 (multiple single elements)