yetangitu/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2025-10-03 09:49:23 +02:00
Code Issues Releases Wiki Activity

GP-4794 Add lanes sizes for ZMM registers

Browse source
This commit is contained in:
caheckman 2024-07-26 19:20:11 +00:00
parent 82b3831529
commit fb13a1ca41
3 changed files with 195 additions and 63 deletions
Download patch file Download diff file Expand all files Collapse all files

34
Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/lang/Register.java
View file

@ -4,9 +4,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* http://www.apache.org/licenses/LICENSE-2.0 * http://www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, * distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -64,8 +64,8 @@ public class Register implements java.io.Serializable, Comparable<Register> {
private Register baseRegister; private Register baseRegister;
private String group; private String group;
/** Set of valid lane sizes **/ /** Bit vector of valid lane sizes **/
private TreeSet<Integer> laneSizes; private long laneSizes;
/** /**
* Constructs a new Register object. * Constructs a new Register object.
@ -101,6 +101,7 @@ public class Register implements java.io.Serializable, Comparable<Register> {
this.typeFlags = typeFlags; this.typeFlags = typeFlags;
this.bigEndian = bigEndian; this.bigEndian = bigEndian;
this.bitLength = bitLength; this.bitLength = bitLength;
this.laneSizes = 0;
int leastSigByte = leastSignificantBit / 8; int leastSigByte = leastSignificantBit / 8;
int mostSigByte = (leastSignificantBit + bitLength - 1) / 8; int mostSigByte = (leastSignificantBit + bitLength - 1) / 8;
@ -509,10 +510,10 @@ public class Register implements java.io.Serializable, Comparable<Register> {
if (!isVectorRegister()) { if (!isVectorRegister()) {
return false; return false;
} }
if (laneSizes == null) { if (laneSizeInBytes > 64 || laneSizeInBytes < 1) {
return false; return false;
} }
return laneSizes.contains(laneSizeInBytes); return (((1L << (laneSizeInBytes - 1)) & laneSizes) != 0);
} }
/** /**
@ -522,13 +523,19 @@ public class Register implements java.io.Serializable, Comparable<Register> {
* lane sizes have been set. * lane sizes have been set.
*/ */
public int[] getLaneSizes() { public int[] getLaneSizes() {
if (laneSizes == null) { if (laneSizes == 0) {
return null; return null;
} }
int[] sizes = new int[laneSizes.size()]; int[] sizes = new int[Long.bitCount(laneSizes)];
int index = 0; int index = 0;
for (int size : laneSizes) { int size = 1;
sizes[index++] = size; long tmp = laneSizes;
while (tmp != 0) {
if ((tmp & 1) != 0) {
sizes[index++] = size;
}
tmp >>= 1;
size += 1;
} }
return sizes; return sizes;
} }
@ -546,16 +553,13 @@ public class Register implements java.io.Serializable, Comparable<Register> {
throw new UnsupportedOperationException( throw new UnsupportedOperationException(
"Register " + getName() + " does not support lanes"); "Register " + getName() + " does not support lanes");
} }
if (laneSizeInBytes <= 0 || laneSizeInBytes >= numBytes || if (laneSizeInBytes <= 0 || laneSizeInBytes >= numBytes || laneSizeInBytes > 64 ||
(numBytes % laneSizeInBytes) != 0) { (numBytes % laneSizeInBytes) != 0) {
throw new IllegalArgumentException( throw new IllegalArgumentException(
"Invalid lane size: " + laneSizeInBytes + " for register " + getName()); "Invalid lane size: " + laneSizeInBytes + " for register " + getName());
} }
if (laneSizes == null) {
laneSizes = new TreeSet<>();
}
typeFlags |= TYPE_VECTOR; typeFlags |= TYPE_VECTOR;
laneSizes.add(laneSizeInBytes); laneSizes |= (1L << (laneSizeInBytes - 1));
} }
} }

96
Ghidra/Processors/x86/data/languages/x86-64.pspec
View file

@ -76,6 +76,38 @@
<register name="MM5" group="MMX"/> <register name="MM5" group="MMX"/>
<register name="MM6" group="MMX"/> <register name="MM6" group="MMX"/>
<register name="MM7" group="MMX"/> <register name="MM7" group="MMX"/>
<register name="ZMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="ZMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
@ -92,22 +124,54 @@
<register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" vector_lane_sizes="1,2,4,8"/> <register name="YMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" vector_lane_sizes="1,2,4,8"/> <register name="YMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" vector_lane_sizes="1,2,4,8"/> <register name="YMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" vector_lane_sizes="1,2,4,8"/> <register name="YMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" vector_lane_sizes="1,2,4,8"/> <register name="YMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" vector_lane_sizes="1,2,4,8"/> <register name="YMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" vector_lane_sizes="1,2,4,8"/> <register name="YMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" vector_lane_sizes="1,2,4,8"/> <register name="YMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" vector_lane_sizes="1,2,4,8"/> <register name="YMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" vector_lane_sizes="1,2,4,8"/> <register name="YMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" vector_lane_sizes="1,2,4,8"/> <register name="YMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" vector_lane_sizes="1,2,4,8"/> <register name="YMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" vector_lane_sizes="1,2,4,8"/> <register name="YMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" vector_lane_sizes="1,2,4,8"/> <register name="YMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" vector_lane_sizes="1,2,4,8"/> <register name="YMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" vector_lane_sizes="1,2,4,8"/> <register name="YMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="CF" group="FLAGS"/> <register name="CF" group="FLAGS"/>
<register name="F1" group="FLAGS"/> <register name="F1" group="FLAGS"/>
<register name="PF" group="FLAGS"/> <register name="PF" group="FLAGS"/>

128
Ghidra/Processors/x86/data/languages/x86.pspec
View file

@ -60,38 +60,102 @@
<register name="MM5" group="MMX"/> <register name="MM5" group="MMX"/>
<register name="MM6" group="MMX"/> <register name="MM6" group="MMX"/>
<register name="MM7" group="MMX"/> <register name="MM7" group="MMX"/>
<register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM3" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM4" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM5" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM6" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM7" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM8" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM9" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM10" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM11" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM12" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/> <register name="ZMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" vector_lane_sizes="1,2,4,8"/> <register name="ZMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" vector_lane_sizes="1,2,4,8"/> <register name="ZMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" vector_lane_sizes="1,2,4,8"/> <register name="ZMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" vector_lane_sizes="1,2,4,8"/> <register name="ZMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" vector_lane_sizes="1,2,4,8"/> <register name="ZMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" vector_lane_sizes="1,2,4,8"/> <register name="ZMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" vector_lane_sizes="1,2,4,8"/> <register name="ZMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" vector_lane_sizes="1,2,4,8"/> <register name="ZMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" vector_lane_sizes="1,2,4,8"/> <register name="ZMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" vector_lane_sizes="1,2,4,8"/> <register name="ZMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" vector_lane_sizes="1,2,4,8"/> <register name="ZMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" vector_lane_sizes="1,2,4,8"/> <register name="ZMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" vector_lane_sizes="1,2,4,8"/> <register name="ZMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" vector_lane_sizes="1,2,4,8"/> <register name="ZMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" vector_lane_sizes="1,2,4,8"/> <register name="ZMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" vector_lane_sizes="1,2,4,8"/> <register name="ZMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="YMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM0" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM1" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM2" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM3" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM4" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM5" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM6" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM7" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM8" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM9" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM10" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM11" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM12" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM13" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM14" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM15" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM16" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM17" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM18" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM19" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM20" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM21" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM22" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM23" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM24" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM25" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM26" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM27" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM28" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM29" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM30" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="XMM31" group="AVX" vector_lane_sizes="1,2,4,8"/>
<register name="CF" group="FLAGS"/> <register name="CF" group="FLAGS"/>
<register name="F1" group="FLAGS"/> <register name="F1" group="FLAGS"/>
<register name="PF" group="FLAGS"/> <register name="PF" group="FLAGS"/>