[riscv] Added context register for extensions
[riscv] missed a define in refactor
[riscv] got 100% on RV32IMC
[riscv] Add throw away script to generate SLEIGH
[riscv]
Fixes from SleighDevTools
- R4-type were using a bad bit pattern that broke the rs3 operand
- mul had a copy/paste typo that ignored the rs2 operand
- bad define guard for compressesed instruction
