13 commits

Author	SHA1	Message	Date
James	ef78846212	GP-1409 implemented code review suggestion ... GP-1409 minor improvements to RISCV spec	2021-11-05 09:36:43 -04:00
emteere	b1e75e0d6f	GP-358_emteere Minor RISV code review changes	2020-11-03 16:41:29 -05:00
mumbel	5fe0f16e10	c.fsw broken under double-precision ... if FP is 64, should still handle single precision	2020-11-03 16:41:28 -05:00
mumbel	a487f77918	Opinion fix ... Does not handle all the cases it can, add in size IMAFC and generic cases for GC.	2020-11-03 16:41:27 -05:00
mumbel	c9ae8bdd8d	Update to RISCV processor module	2020-11-03 16:41:26 -05:00
ghidra1	4ecf402341	Merge remote-tracking branch 'origin/GP-58_caheckman_RiscvDecodeStates'	2020-09-18 16:27:43 -04:00
caheckman	2e9fdb7de8	Adjustment to RISCV decode states	2020-08-03 13:44:19 -04:00
Austin Roach	688ed5e00d	RISC-V j/jr semantics: use goto instead of call ... In the RISC-V binaries that I've been looking at, the j and jr instructions have been used exclusively for intraprocedural control flow transfers, where the function-call hinting associated with the CALL p-code op leads to nasty side effects in the control flow reconstruction.	2020-07-20 20:48:37 -04:00
ghidorahrex	b7481d2088	Merge remote-tracking branch ... 'origin/GT-3524_ghidorahrex_PR-1450_mumbel_riscpatt' Fixes #1450	2020-07-16 14:09:41 -04:00
ghidra1	3c99e1063c	Corrected RISCV language files which need blank line at end	2020-02-20 14:17:31 -05:00
ghidorahrex	9faf39baed	Fixed sleighCompiler test failures with riscv.	2020-02-18 14:43:18 -05:00
mumbel	5fc98745bc	initial patterns	2020-01-12 19:16:18 -06:00
mumbel	d7e51ee515	RISC-V processor ... [riscv] Added context register for extensions [riscv] missed a define in refactor [riscv] got 100% on RV32IMC [riscv] Add throw away script to generate SLEIGH [riscv] Fixes from SleighDevTools - R4-type were using a bad bit pattern that broke the rs3 operand - mul had a copy/paste typo that ignored the rs2 operand - bad define guard for compressesed instruction	2019-12-10 14:04:05 -06:00