Imposed default Thumb context setting for PE and MSCoff ARM32 imports
with addition of v8T ARM variant. Corrected ARM pattern alignment
issues. Corrected DBViewer long value rendering.
and ARM resulting in the wrong register being attached/selected.
The U bit was also flipped `unsigned = (U == '1');`
unsigned now has bit set and signed is unset
Note that this doesn't take into account the subtleties of what TEQP
does -- for more information on this, see
https://www.heyrick.co.uk/armwiki/The_Status_register#Legacy_processors_.2826_bit.29
It will, however, stop Ghidra from completely freaking out when it sees
this instruction in old RISC OS 26bit-PC code.
TODO, make this behave (in SLEIGH) like a PSR update (MSR CPSR, ...) but
note that the PSR bit order is different to the 26bit ARM PSR so fudging
will be needed.
ADD (SP plus register, T32) was incorrectly op11=0x1e (1 1 1 1 0),
but is supposed to be 0x1d (1 1 1 0 1)
ARM's CLREX matches THUMB's BL<c> <label>. Added AMODE check to
CLREX
