These Sleigh constructors were acting as constructors for VNMLS, however
the constructors actually describe the bit encoding for VNMLA, which can
result in incorrect disassembly meaning.
This corrects this so that VNMLA instructions are properly disassembled
and also don't show up as generic CDP instructions.
Similarly with VNMUL, VNMLS is also able to execute with a condition
code for single-precision and double-precision floating point variants.
Like with the previous change, we can also amend the Sleigh constructor
so that it decodes properly (the condition code for a predictable
instruction is 0xE, not 0xF).
This fixes VNMLS instructions disassembling as generic CDP instructions,
making disassembly clearer.
The single-precision and double-precision variants of VNMUL support
condition codes on them in ARM mode. We can amend the Sleigh
constructors to reflect this.
We can also amend the half-precision variant to reflect that the
condition code should be 0xE in terms of value. The ARMv8 architecture
reference manual states (at F6.1.148) that if a half-precision
instruction is present and does not have a condition code of 1110, then
the behavior is considered CONSTRAINED UNPREDICTABLE.
This fixes VNMUL instructions disassembling as generic CDP instructions,
making the disassembly much clearer.
Bits 23-27 are defined with a bit encoding of 0b11101, not 0b11011 (See
section F6.1.60 within the ARMv8 reference manual or section A8.8.306
within the ARMv7 reference manual).
This makes conversions from floating-point registers to signed values
disassemble/decompile more properly and not as generic CDP instructions,
making decompilation a little more informative.
Imposed default Thumb context setting for PE and MSCoff ARM32 imports
with addition of v8T ARM variant. Corrected ARM pattern alignment
issues. Corrected DBViewer long value rendering.
and ARM resulting in the wrong register being attached/selected.
The U bit was also flipped `unsigned = (U == '1');`
unsigned now has bit set and signed is unset
Note that this doesn't take into account the subtleties of what TEQP
does -- for more information on this, see
https://www.heyrick.co.uk/armwiki/The_Status_register#Legacy_processors_.2826_bit.29
It will, however, stop Ghidra from completely freaking out when it sees
this instruction in old RISC OS 26bit-PC code.
TODO, make this behave (in SLEIGH) like a PSR update (MSR CPSR, ...) but
note that the PSR bit order is different to the 26bit ARM PSR so fudging
will be needed.
ADD (SP plus register, T32) was incorrectly op11=0x1e (1 1 1 1 0),
but is supposed to be 0x1d (1 1 1 0 1)
ARM's CLREX matches THUMB's BL<c> <label>. Added AMODE check to
CLREX
