Dan
7dd417b6be
GP-5051: Distinct qemu-system launcher.
2024-12-04 08:43:26 -05:00
Dan
289c5c90fa
GP-3838: Add qemu+gdb launcher.
2024-03-01 12:36:13 -05:00
ghidorahrex
21e74c4d42
GP-4047: Fixed RISC-V custom instruction sleigh patterns
2023-11-16 16:53:58 +00:00
emteere
5bf82b8af1
GP-3217 RISCV JAL/JALR goto/call fix for T0 register
2023-03-20 20:44:59 +00:00
emteere
93c291ba72
GP-2905: Fixed regression in handling of spacebase register values that
...
cause a stack trace in the decompiler for RISCV. Removed unnecessary
spacebase settings in tricore, mips, riscv.
2023-02-07 10:51:56 -05:00
emteere
321c3455a3
GP-2878 Adjusted RISCV function start pattern totalbits and postbits and instruction flow / decode changes, don't decode 0x0000 as unimpl
2022-12-01 19:33:53 -05:00
Ryan Kurtz
8d0564f19a
Merge remote-tracking branch 'origin/GP-2161_ghidorahrex_PR-2590_mumbel_riscv_cspec'
2022-07-11 12:40:46 -04:00
Henrik Ferdinand Noelscher
820c1a567d
fix #4002 - fix a typo in RISC-V pattern constraints filename
2022-02-15 18:42:53 +01:00
James
ef78846212
GP-1409 implemented code review suggestion
...
GP-1409 minor improvements to RISCV spec
2021-11-05 09:36:43 -04:00
mumbel
31c466c83e
Bad long size (and alignment)
2020-12-27 22:29:04 -06:00
emteere
b1e75e0d6f
GP-358_emteere Minor RISV code review changes
2020-11-03 16:41:29 -05:00
mumbel
5fe0f16e10
c.fsw broken under double-precision
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if FP is 64, should still handle single precision
2020-11-03 16:41:28 -05:00
mumbel
a487f77918
Opinion fix
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Does not handle all the cases it can, add in size IMAFC and
generic cases for GC.
2020-11-03 16:41:27 -05:00
mumbel
c9ae8bdd8d
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
ghidra1
4ecf402341
Merge remote-tracking branch 'origin/GP-58_caheckman_RiscvDecodeStates'
2020-09-18 16:27:43 -04:00
caheckman
2e9fdb7de8
Adjustment to RISCV decode states
2020-08-03 13:44:19 -04:00
Austin Roach
688ed5e00d
RISC-V j/jr semantics: use goto instead of call
...
In the RISC-V binaries that I've been looking at, the j and jr
instructions have been used exclusively for intraprocedural control flow
transfers, where the function-call hinting associated with the CALL
p-code op leads to nasty side effects in the control flow
reconstruction.
2020-07-20 20:48:37 -04:00
ghidorahrex
b7481d2088
Merge remote-tracking branch
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'origin/GT-3524_ghidorahrex_PR-1450_mumbel_riscpatt'
Fixes #1450
2020-07-16 14:09:41 -04:00
ghidra1
3c99e1063c
Corrected RISCV language files which need blank line at end
2020-02-20 14:17:31 -05:00
ghidorahrex
9faf39baed
Fixed sleighCompiler test failures with riscv.
2020-02-18 14:43:18 -05:00
mumbel
5fc98745bc
initial patterns
2020-01-12 19:16:18 -06:00
mumbel
d7e51ee515
RISC-V processor
...
[riscv] Added context register for extensions
[riscv] missed a define in refactor
[riscv] got 100% on RV32IMC
[riscv] Add throw away script to generate SLEIGH
[riscv]
Fixes from SleighDevTools
- R4-type were using a bad bit pattern that broke the rs3 operand
- mul had a copy/paste typo that ignored the rs2 operand
- bad define guard for compressesed instruction
2019-12-10 14:04:05 -06:00
