2 commits

Author	SHA1	Message	Date
emteere	93c291ba72	GP-2905: Fixed regression in handling of spacebase register values that ... cause a stack trace in the decompiler for RISCV. Removed unnecessary spacebase settings in tricore, mips, riscv.	2023-02-07 10:51:56 -05:00
mumbel	d7e51ee515	RISC-V processor ... [riscv] Added context register for extensions [riscv] missed a define in refactor [riscv] got 100% on RV32IMC [riscv] Add throw away script to generate SLEIGH [riscv] Fixes from SleighDevTools - R4-type were using a bad bit pattern that broke the rs3 operand - mul had a copy/paste typo that ignored the rs2 operand - bad define guard for compressesed instruction	2019-12-10 14:04:05 -06:00