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14607 commits 3 branches 48 tags 430 MiB
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54 commits

Author SHA1 Message Date
ghidorahrex
67631a27ef GT-3524: Certifying riscv pattern files. 2020-02-06 10:40:40 -05:00
mumbel
5fc98745bc initial patterns 2020-01-12 19:16:18 -06:00
ghidorahrex
b628a7e46f GT-3389: Certifying RISCV processor module. 2019-12-10 15:22:25 -05:00
mumbel
d7e51ee515 RISC-V processor 
[riscv] Added context register for extensions

[riscv] missed a define in refactor

[riscv] got 100% on RV32IMC

[riscv] Add throw away script to generate SLEIGH

[riscv]

Fixes from SleighDevTools

- R4-type were using a bad bit pattern that broke the rs3 operand
- mul had a copy/paste typo that ignored the rs2 operand
- bad define guard for compressesed instruction
 2019-12-10 14:04:05 -06:00