mirror of
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573 lines
27 KiB
C++
573 lines
27 KiB
C++
/* ###
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* IP: GHIDRA
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/// \file translate.hh
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/// \brief Classes for disassembly and pcode generation
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///
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/// Classes for keeping track of spaces and registers (for a single architecture).
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#ifndef __CPUI_TRANSLATE__
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#define __CPUI_TRANSLATE__
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#include "pcoderaw.hh"
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#include "float.hh"
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// Some errors specific to the translation unit
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/// \brief Exception for encountering unimplemented pcode
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///
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/// This error is thrown when a particular machine instruction
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/// cannot be translated into pcode. This particular error
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/// means that the particular instruction being decoded was valid,
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/// but the system doesn't know how to represent it in pcode.
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struct UnimplError : public LowlevelError {
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int4 instruction_length; ///< Number of bytes in the unimplemented instruction
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/// \brief Constructor
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///
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/// \param s is a more verbose description of the error
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/// \param l is the length (in bytes) of the unimplemented instruction
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UnimplError(const string &s,int4 l) : LowlevelError(s) { instruction_length = l; }
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};
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/// \brief Exception for bad instruction data
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///
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/// This error is thrown when the system cannot decode data
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/// for a particular instruction. This usually means that the
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/// data is not really a machine instruction, but may indicate
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/// that the system is unaware of the particular instruction.
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struct BadDataError : public LowlevelError {
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/// \brief Constructor
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///
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/// \param s is a more verbose description of the error
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BadDataError(const string &s) : LowlevelError(s) {}
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};
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class Translate;
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/// \brief Object for describing how a space should be truncated
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///
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/// This can turn up in various XML configuration files and essentially acts
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/// as a command to override the size of an address space as defined by the architecture
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class TruncationTag {
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string spaceName; ///< Name of space to be truncated
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uint4 size; ///< Size truncated addresses into the space
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public:
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void restoreXml(const Element *el); ///< Restore \b this from XML
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const string &getName(void) const { return spaceName; } ///< Get name of address space being truncated
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uint4 getSize(void) const { return size; } ///< Size (of pointers) for new truncated space
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};
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/// \brief Abstract class for emitting pcode to an application
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///
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/// Translation engines pass back the generated pcode for an
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/// instruction to the application using this class.
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class PcodeEmit {
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public:
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virtual ~PcodeEmit(void) {} ///< Virtual destructor
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/// \brief The main pcode emit method.
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///
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/// A single pcode instruction is returned to the application
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/// via this method. Particular applications override it
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/// to tailor how the operations are used.
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/// \param addr is the Address of the machine instruction
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/// \param opc is the opcode of the particular pcode instruction
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/// \param outvar if not \e null is a pointer to data about the
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/// output varnode
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/// \param vars is a pointer to an array of VarnodeData for each
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/// input varnode
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/// \param isize is the number of input varnodes
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virtual void dump(const Address &addr,OpCode opc,VarnodeData *outvar,VarnodeData *vars,int4 isize)=0;
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/// Emit pcode directly from an XML tag
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void restoreXmlOp(const Element *el,const AddrSpaceManager *trans);
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enum { // Tags for packed pcode format
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unimpl_tag = 0x20,
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inst_tag = 0x21,
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op_tag = 0x22,
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void_tag = 0x23,
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spaceid_tag = 0x24,
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addrsz_tag = 0x25,
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end_tag = 0x60
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};
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/// Helper function for unpacking an offset from a pcode byte stream
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static const uint1 *unpackOffset(const uint1 *ptr,uintb &off);
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/// Helper function for unpacking a varnode from a pcode byte stream
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static const uint1 *unpackVarnodeData(const uint1 *ptr,VarnodeData &v,const AddrSpaceManager *trans);
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/// Emit pcode directly from a packed byte stream
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const uint1 *restorePackedOp(const Address &addr,const uint1 *ptr,const AddrSpaceManager *trans);
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};
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/// \brief Abstract class for emitting disassembly to an application
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///
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/// Translation engines pass back the disassembly character data
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/// for decoded machine instructions to an application using this class.
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class AssemblyEmit {
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public:
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virtual ~AssemblyEmit(void) {} ///< Virtual destructor
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/// \brief The main disassembly emitting method.
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///
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/// The disassembly strings for a single machine instruction
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/// are passed back to an application through this method.
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/// Particular applications can tailor the use of the disassembly
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/// by overriding this method.
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/// \param addr is the Address of the machine instruction
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/// \param mnem is the decoded instruction mnemonic
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/// \param body is the decode body (or operands) of the instruction
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virtual void dump(const Address &addr,const string &mnem,const string &body)=0;
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};
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/// \brief Abstract class for converting native constants to addresses
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///
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/// This class is used if there is a special calculation to get from a constant embedded
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/// in the code being analyzed to the actual Address being referred to. This is used especially
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/// in the case of a segmented architecture, where "near" pointers must be extended to a full address
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/// with implied segment information.
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class AddressResolver {
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public:
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virtual ~AddressResolver(void) {} ///> Virtual destructor
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/// \brief The main resolver method.
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///
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/// Given a native constant in a specific context, resolve what address is being referred to.
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/// \param val is constant to be resolved to an address
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/// \param sz is the size of \e val in context.
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/// \param point is the address at which this constant is being used
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/// \param fullEncoding is used to hold the full pointer encoding if \b val is a partial encoding
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/// \return the resolved Address
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virtual Address resolve(uintb val,int4 sz,const Address &point,uintb &fullEncoding)=0;
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};
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/// \brief A virtual space \e stack space
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///
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/// In a lot of analysis situations it is convenient to extend
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/// the notion of an address space to mean bytes that are indexed
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/// relative to some base register. The canonical example of this
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/// is the \b stack space, which models the concept of local
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/// variables stored on the stack. An address of (\b stack, 8)
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/// might model the address of a function parameter on the stack
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/// for instance, and (\b stack, 0xfffffff4) might be the address
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/// of a local variable. A space like this is inherently \e virtual
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/// and contained within whatever space is being indexed into.
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class SpacebaseSpace : public AddrSpace {
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friend class AddrSpaceManager;
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AddrSpace *contain; ///< Containing space
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bool hasbaseregister; ///< true if a base register has been attached
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bool isNegativeStack; ///< true if stack grows in negative direction
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VarnodeData baseloc; ///< location data of the base register
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VarnodeData baseOrig; ///< Original base register before any truncation
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void setBaseRegister(const VarnodeData &data,int4 origSize,bool stackGrowth); ///< Set the base register at time space is created
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public:
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SpacebaseSpace(AddrSpaceManager *m,const Translate *t,const string &nm,int4 ind,int4 sz,AddrSpace *base,int4 dl);
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SpacebaseSpace(AddrSpaceManager *m,const Translate *t); ///< For use with restoreXml
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virtual int4 numSpacebase(void) const;
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virtual const VarnodeData &getSpacebase(int4 i) const;
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virtual const VarnodeData &getSpacebaseFull(int4 i) const;
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virtual bool stackGrowsNegative(void) const { return isNegativeStack; }
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virtual AddrSpace *getContain(void) const { return contain; } ///< Return containing space
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virtual void saveXml(ostream &s) const;
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virtual void restoreXml(const Element *el);
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};
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/// \brief A record describing how logical values are split
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///
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/// The decompiler can describe a logical value that is stored split across multiple
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/// physical memory locations. This record describes such a split. The pieces must be listed
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/// from \e most \e significant to \e least \e significant.
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class JoinRecord {
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friend class AddrSpaceManager;
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vector<VarnodeData> pieces; ///< All the physical pieces of the symbol
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VarnodeData unified; ///< Special entry representing entire symbol in one chunk
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public:
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int4 numPieces(void) const { return pieces.size(); } ///< Get number of pieces in this record
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bool isFloatExtension(void) const { return (pieces.size() == 1); } ///< Does this record extend a float varnode
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const VarnodeData &getPiece(int4 i) const { return pieces[i]; } ///< Get the i-th piece
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const VarnodeData &getUnified(void) const { return unified; } ///< Get the Varnode whole
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bool operator<(const JoinRecord &op2) const; ///< Compare records lexigraphically by pieces
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};
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/// \brief Comparator for JoinRecord objects
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struct JoinRecordCompare {
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bool operator()(const JoinRecord *a,const JoinRecord *b) const {
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return *a < *b; } ///< Compare to JoinRecords using their built-in comparison
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};
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/// \brief A manager for different address spaces
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///
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/// Allow creation, lookup by name, lookup by shortcut, lookup by name, and iteration
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/// over address spaces
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class AddrSpaceManager {
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vector<AddrSpace *> baselist; ///< Every space we know about for this architecture
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vector<AddressResolver *> resolvelist; ///< Special constant resolvers
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map<string,AddrSpace *> name2Space; ///< Map from name -> space
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map<int4,AddrSpace *> shortcut2Space; ///< Map from shortcut -> space
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AddrSpace *constantspace; ///< Quick reference to constant space
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AddrSpace *defaultspace; ///< Generally primary RAM, where assembly pointers point to
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AddrSpace *iopspace; ///< Space for internal pcode op pointers
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AddrSpace *fspecspace; ///< Space for internal callspec pointers
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AddrSpace *joinspace; ///< Space for unifying split variables
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AddrSpace *stackspace; ///< Stack space associated with processor
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AddrSpace *uniqspace; ///< Temporary space associated with processor
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uintb joinallocate; ///< Next offset to be allocated in join space
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set<JoinRecord *,JoinRecordCompare> splitset; ///< Different splits that have been defined in join space
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vector<JoinRecord *> splitlist; ///< JoinRecords indexed by join address
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protected:
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AddrSpace *restoreXmlSpace(const Element *el,const Translate *trans); ///< Add a space to the model based an on XML tag
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void restoreXmlSpaces(const Element *el,const Translate *trans); ///< Restore address spaces in the model from an XML tag
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void setDefaultSpace(int4 index); ///< Set the default address space
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void setReverseJustified(AddrSpace *spc); ///< Set reverse justified property on this space
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void assignShortcut(AddrSpace *spc); ///< Select a shortcut character for a new space
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void insertSpace(AddrSpace *spc); ///< Add a new address space to the model
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void copySpaces(const AddrSpaceManager *op2); ///< Copy spaces from another manager
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void addSpacebasePointer(SpacebaseSpace *basespace,const VarnodeData &ptrdata,int4 truncSize,bool stackGrowth); ///< Set the base register of a spacebase space
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void insertResolver(AddrSpace *spc,AddressResolver *rsolv); ///< Override the base resolver for a space
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public:
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AddrSpaceManager(void); ///< Construct an empty address space manager
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virtual ~AddrSpaceManager(void); ///< Destroy the manager
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int4 getDefaultSize(void) const; ///< Get size of addresses for the default space
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AddrSpace *getSpaceByName(const string &nm) const; ///< Get address space by name
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AddrSpace *getSpaceByShortcut(char sc) const; ///< Get address space from its shortcut
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AddrSpace *getIopSpace(void) const; ///< Get the internal pcode op space
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AddrSpace *getFspecSpace(void) const; ///< Get the internal callspec space
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AddrSpace *getJoinSpace(void) const; ///< Get the joining space
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AddrSpace *getStackSpace(void) const; ///< Get the stack space for this processor
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AddrSpace *getUniqueSpace(void) const; ///< Get the temporary register space for this processor
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AddrSpace *getDefaultSpace(void) const; ///< Get the default address space of this processor
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AddrSpace *getConstantSpace(void) const; ///< Get the constant space
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Address getConstant(uintb val) const; ///< Get a constant encoded as an Address
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Address createConstFromSpace(AddrSpace *spc) const; ///< Create a constant address encoding an address space
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Address resolveConstant(AddrSpace *spc,uintb val,int4 sz,const Address &point,uintb &fullEncoding) const;
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int4 numSpaces(void) const; ///< Get the number of address spaces for this processor
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AddrSpace *getSpace(int4 i) const; ///< Get an address space via its index
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AddrSpace *getNextSpaceInOrder(AddrSpace *spc) const; ///< Get the next \e contiguous address space
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JoinRecord *findAddJoin(const vector<VarnodeData> &pieces,uint4 logicalsize); ///< Get (or create) JoinRecord for \e pieces
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JoinRecord *findJoin(uintb offset) const; ///< Find JoinRecord for \e offset in the join space
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void setDeadcodeDelay(AddrSpace *spc,int4 delaydelta); ///< Set the deadcodedelay for a specific space
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void truncateSpace(const TruncationTag &tag); ///< Mark a space as truncated from its original size
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/// \brief Build a logically lower precision storage location for a bigger floating point register
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Address constructFloatExtensionAddress(const Address &realaddr,int4 realsize,int4 logicalsize);
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/// \brief Build a logical whole from register pairs
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Address constructJoinAddress(const Translate *translate,const Address &hiaddr,int4 hisz,const Address &loaddr,int4 losz);
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};
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/// \brief The interface to a translation engine for a processor.
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///
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/// This interface performs translations of instruction data
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/// for a particular processor. It has two main functions
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/// - Disassemble single machine instructions
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/// - %Translate single machine instructions into \e pcode.
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///
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/// It is also the repository for information about the exact
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/// configuration of the reverse engineering model associated
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/// with the processor. In particular, it knows about all the
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/// address spaces, registers, and spacebases for the processor.
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class Translate : public AddrSpaceManager {
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bool target_isbigendian; ///< \b true if the general endianness of the process is big endian
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uintm unique_base; ///< Starting offset into unique space
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protected:
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int4 alignment; ///< Byte modulo on which instructions are aligned
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vector<FloatFormat> floatformats; ///< Floating point formats utilized by the processor
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void setBigEndian(bool val); ///< Set general endianness to \b big if val is \b true
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void setUniqueBase(uintm val); ///< Set the base offset for new temporary registers
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public:
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Translate(void); ///< Constructor for the translator
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void setDefaultFloatFormats(void); ///< If no explicit float formats, set up default formats
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bool isBigEndian(void) const; ///< Is the processor big endian?
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const FloatFormat *getFloatFormat(int4 size) const; ///< Get format for a particular floating point encoding
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int4 getAlignment(void) const; ///< Get the instruction alignment for the processor
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uintm getUniqueBase(void) const; ///< Get the base offset for new temporary registers
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/// \brief Initialize the translator given XML configuration documents
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///
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/// A translator gets initialized once, possibly using XML documents
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/// to configure it.
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/// \param store is a set of configuration documents
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virtual void initialize(DocumentStorage &store)=0;
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/// \brief Add a new context variable to the model for this processor
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///
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/// Add the name of a context register used by the processor and
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/// how that register is packed into the context state. This
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/// information is used by a ContextDatabase to associate names
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/// with context information and to pack context into a single
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/// state variable for the translation engine.
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/// \param name is the name of the new context variable
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/// \param sbit is the first bit of the variable in the packed state
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/// \param ebit is the last bit of the variable in the packed state
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virtual void registerContext(const string &name,int4 sbit,int4 ebit) {}
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/// \brief Set the default value for a particular context variable
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///
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/// Set the value to be returned for a context variable when
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/// there are no explicit address ranges specifying a value
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/// for the variable.
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/// \param name is the name of the context variable
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/// \param val is the value to be considered default
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virtual void setContextDefault(const string &name,uintm val) {}
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/// \brief Toggle whether disassembly is allowed to affect context
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///
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/// By default the disassembly/pcode translation engine can change
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/// the global context, thereby affecting later disassembly. Context
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/// may be getting determined by something other than control flow in,
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/// the disassembly, in which case this function can turn off changes
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/// made by the disassembly
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/// \param val is \b true to allow context changes, \b false prevents changes
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virtual void allowContextSet(bool val) const {}
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/// \brief Add a named register to the model for this processor
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///
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/// \deprecated All registers used to be formally added to the
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/// processor model through this method.
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/// \param nm is the name of the new register
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/// \param base is the address space containing the register
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/// \param offset is the offset of the register
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/// \param size is the number of bytes in the register
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virtual void addRegister(const string &nm,AddrSpace *base,uintb offset,int4 size)=0;
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/// \brief Get a register as VarnodeData given its name
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///
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/// Retrieve the location and size of a register given its name
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/// \param nm is the name of the register
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/// \return the VarnodeData for the register
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virtual const VarnodeData &getRegister(const string &nm) const=0;
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/// \brief Get the name of a register given its location
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///
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/// Generic references to locations in a \e register space can
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/// be translated into the associated register \e name. If the
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/// location doesn't match a register \e exactly, an empty string
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/// is returned.
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/// \param base is the address space containing the location
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/// \param off is the offset of the location
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/// \param size is the size of the location
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/// \return the name of the register, or an empty string
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virtual string getRegisterName(AddrSpace *base,uintb off,int4 size) const=0;
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/// \brief Get a list of all register names and the corresponding location
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///
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/// Most processors have a list of named registers and possibly other memory locations
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/// that are specific to it. This function populates a map from the location information
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/// to the name, for every named location known by the translator
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/// \param reglist is the map which will be populated by the call
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virtual void getAllRegisters(map<VarnodeData,string> ®list) const=0;
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/// \brief Get a list of all \e user-defined pcode ops
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///
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/// The pcode model allows processors to define new pcode
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/// instructions that are specific to that processor. These
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/// \e user-defined instructions are all identified by a name
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/// and an index. This method returns a list of these ops
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/// in index order.
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/// \param res is the resulting vector of user op names
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virtual void getUserOpNames(vector<string> &res) const=0;
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/// \brief Get the length of a machine instruction
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///
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/// This method decodes an instruction at a specific address
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/// just enough to find the number of bytes it uses within the
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/// instruction stream.
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/// \param baseaddr is the Address of the instruction
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/// \return the number of bytes in the instruction
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virtual int4 instructionLength(const Address &baseaddr) const=0;
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/// \brief Transform a single machine instruction into pcode
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///
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/// This is the main interface to the pcode translation engine.
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/// The \e dump method in the \e emit object is invoked exactly
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/// once for each pcode operation in the translation for the
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/// machine instruction at the given address.
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/// This routine can throw either
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/// - UnimplError or
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/// - BadDataError
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///
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/// \param emit is the tailored pcode emitting object
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/// \param baseaddr is the Address of the machine instruction
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/// \return the number of bytes in the machine instruction
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virtual int4 oneInstruction(PcodeEmit &emit,const Address &baseaddr) const=0;
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/// \brief Disassemble a single machine instruction
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///
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/// This is the main interface to the disassembler for the
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/// processor. It disassembles a single instruction and
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/// returns the result to the application via the \e dump
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/// method in the \e emit object.
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/// \param emit is the disassembly emitting object
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/// \param baseaddr is the address of the machine instruction to disassemble
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virtual int4 printAssembly(AssemblyEmit &emit,const Address &baseaddr) const=0;
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};
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/// Return the size of addresses for the processor's official
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/// default space. This space is usually the main RAM databus.
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/// \return the size of an address in bytes
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inline int4 AddrSpaceManager::getDefaultSize(void) const {
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return defaultspace->getAddrSize();
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}
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/// There is a special address space reserved for encoding pointers
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/// to pcode operations as addresses. This allows a direct pointer
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/// to be \e hidden within an operation, when manipulating pcode
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/// internally. (See IopSpace)
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/// \return a pointer to the address space
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inline AddrSpace *AddrSpaceManager::getIopSpace(void) const {
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|
return iopspace;
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|
}
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|
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/// There is a special address space reserved for encoding pointers
|
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/// to the FuncCallSpecs object as addresses. This allows direct
|
|
/// pointers to be \e hidden within an operation, when manipulating
|
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/// pcode internally. (See FspecSpace)
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/// \return a pointer to the address space
|
|
inline AddrSpace *AddrSpaceManager::getFspecSpace(void) const {
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|
return fspecspace;
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|
}
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|
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/// There is a special address space reserved for providing a
|
|
/// logical contiguous memory location for variables that are
|
|
/// really split between two physical locations. This allows the
|
|
/// the decompiler to work with the logical value. (See JoinSpace)
|
|
/// \return a pointer to the address space
|
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inline AddrSpace *AddrSpaceManager::getJoinSpace(void) const {
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|
return joinspace;
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|
}
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|
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/// Most processors have registers and instructions that are
|
|
/// reserved for implementing a stack. In the pcode translation,
|
|
/// these are translated into locations and operations on a
|
|
/// dedicated \b stack address space. (See SpacebaseSpace)
|
|
/// \return a pointer to the \b stack space
|
|
inline AddrSpace *AddrSpaceManager::getStackSpace(void) const {
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|
return stackspace;
|
|
}
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|
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/// Both the pcode translation process and the simplification
|
|
/// process need access to a pool of temporary registers that
|
|
/// can be used for moving data around without affecting the
|
|
/// address spaces used to formally model the processor's RAM
|
|
/// and registers. These temporary locations are all allocated
|
|
/// from a dedicated address space, referred to as the \b unique
|
|
/// space. (See UniqueSpace)
|
|
/// \return a pointer to the \b unique space
|
|
inline AddrSpace *AddrSpaceManager::getUniqueSpace(void) const {
|
|
return uniqspace;
|
|
}
|
|
|
|
/// Most processors have a main address bus, on which the bulk
|
|
/// of the processor's RAM is mapped. Everything referenced
|
|
/// with this address bus should be modeled in pcode with a
|
|
/// single address space, referred to as the \e default space.
|
|
/// \return a pointer to the \e default space
|
|
inline AddrSpace *AddrSpaceManager::getDefaultSpace(void) const {
|
|
return defaultspace;
|
|
}
|
|
|
|
/// Pcode represents constant values within an operation as
|
|
/// offsets within a special \e constant address space.
|
|
/// (See ConstantSpace)
|
|
/// \return a pointer to the \b constant space
|
|
inline AddrSpace *AddrSpaceManager::getConstantSpace(void) const {
|
|
return constantspace;
|
|
}
|
|
|
|
/// This routine encodes a specific value as a \e constant
|
|
/// address. I.e. the address space of the resulting Address
|
|
/// will be the \b constant space, and the offset will be the
|
|
/// value.
|
|
/// \param val is the constant value to encode
|
|
/// \return the \e constant address
|
|
inline Address AddrSpaceManager::getConstant(uintb val) const {
|
|
return Address(constantspace,val);
|
|
}
|
|
|
|
/// This routine is used to encode a pointer to an address space
|
|
/// as a \e constant Address, for use in \b LOAD and \b STORE
|
|
/// operations. This is used internally and is slightly more
|
|
/// efficient than storing the formal index of the space
|
|
/// param spc is the space pointer to be encoded
|
|
/// \return the encoded Address
|
|
inline Address AddrSpaceManager::createConstFromSpace(AddrSpace *spc) const {
|
|
return Address(constantspace,(uintb)(uintp)spc);
|
|
}
|
|
|
|
/// This returns the total number of address spaces used by the
|
|
/// processor, including all special spaces, like the \b constant
|
|
/// space and the \b iop space.
|
|
/// \return the number of spaces
|
|
inline int4 AddrSpaceManager::numSpaces(void) const {
|
|
return baselist.size();
|
|
}
|
|
|
|
/// This retrieves a specific address space via its formal index.
|
|
/// All spaces have an index, and in conjunction with the numSpaces
|
|
/// method, this method can be used to iterate over all spaces.
|
|
/// \param i is the index of the address space
|
|
/// \return a pointer to the desired space
|
|
inline AddrSpace *AddrSpaceManager::getSpace(int4 i) const {
|
|
return baselist[i];
|
|
}
|
|
|
|
/// Although endianness is usually specified on the space, most languages set an endianness
|
|
/// across the entire processor. This routine sets the endianness to \b big if the -val-
|
|
/// is passed in as \b true. Otherwise, the endianness is set to \b small.
|
|
/// \param val is \b true if the endianness should be set to \b big
|
|
inline void Translate::setBigEndian(bool val) {
|
|
target_isbigendian = val;
|
|
}
|
|
|
|
/// The \e unique address space, for allocating temporary registers,
|
|
/// is used for both registers needed by the pcode translation
|
|
/// engine and, later, by the simplification engine. This routine
|
|
/// sets the boundary of the portion of the space allocated
|
|
/// for the pcode engine, and sets the base offset where registers
|
|
/// created by the simplification process can start being allocated.
|
|
/// \param val is the boundary offset
|
|
inline void Translate::setUniqueBase(uintm val) {
|
|
if (val>unique_base) unique_base = val;
|
|
}
|
|
|
|
/// Processors can usually be described as using a big endian
|
|
/// encoding or a little endian encoding. This routine returns
|
|
/// \b true if the processor globally uses big endian encoding.
|
|
/// \return \b true if big endian
|
|
inline bool Translate::isBigEndian(void) const {
|
|
return target_isbigendian;
|
|
}
|
|
|
|
/// If machine instructions need to have a specific alignment
|
|
/// for this processor, this routine returns it. I.e. a return
|
|
/// value of 4, means that the address of all instructions
|
|
/// must be a multiple of 4. If there is no
|
|
/// specific alignment requirement, this routine returns 1.
|
|
/// \return the instruction alignment
|
|
inline int4 Translate::getAlignment(void) const {
|
|
return alignment;
|
|
}
|
|
|
|
/// This routine gets the base offset, within the \e unique
|
|
/// temporary register space, where new registers can be
|
|
/// allocated for the simplification process. Locations before
|
|
/// this offset are reserved registers needed by the pcode
|
|
/// translation engine.
|
|
/// \return the first allocatable offset
|
|
inline uintm Translate::getUniqueBase(void) const {
|
|
return unique_base;
|
|
}
|
|
|
|
#endif
|