mirror of
https://github.com/NationalSecurityAgency/ghidra.git
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496 lines
14 KiB
Text
496 lines
14 KiB
Text
#---------------------------------------------------------------------
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# 8.3.5 Logic Operations
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#---------------------------------------------------------------------
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#---------------------------------------------------------------------
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# AND - Logical AND with optional logical shift
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# I. {d, s} -> {0, 1, ..., 15}
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# II, III. {d, x, y} -> {0, 1, ..., 15}
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# sa -> {0, 1, ..., 31}
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#---------------------------------------------------------------------
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# AND Format I
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# Operation: Rd <- Rd & Rs
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# Syntax: and Rd, Rs
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# 000s sss0 0110 dddd
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:AND rd0, RS9A is op13_3=0x0 & op4_5=0x6 & rd0 & RS9A {
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rd0 = rd0 & RS9A;
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NZSTATUS(rd0);
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}
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:AND rd0, RS9A is op13_3=0x0 & op4_5=0x6 & rd0 & RS9A & rd0=0xf {
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PC = inst_start & RS9A;
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NZSTATUS(PC);
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goto [PC];
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}
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# AND Format II
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# Operation: Rd <- Rx & Ry << sa5
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# Syntax: and Rd, Rx, Ry << sa
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# 111x xxx1 1110 yyyy 0000 000t tttt dddd
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:AND erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=0 & erd0 & shift4_5 {
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erd0 = RX9A & (RY0A << shift4_5);
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NZSTATUS(erd0);
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}
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:AND erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=0 & erd0 & shift4_5 & erd0=0xf {
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PC = RX9A & (RY0A << shift4_5);
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NZSTATUS(PC);
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goto [PC];
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}
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# AND Format III
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# Operation: Rd <- Rx & Ry >> sa5
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# Syntax: and Rd, Rx, Ry >> sa
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# 111x xxx1 1110 yyyy 0000 001t tttt dddd
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:AND erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=1 & erd0 & shift4_5 {
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erd0 = RX9A & (RY0A >> shift4_5);
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NZSTATUS(erd0);
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}
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:AND erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=1 & erd0 & shift4_5 & erd0=0xf {
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PC = RX9A & (RY0A >> shift4_5);
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NZSTATUS(PC);
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goto [PC];
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}
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#---------------------------------------------------------------------
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# AND{cond4} - Conditional And
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# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}
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# {d,x,y} -> {0, 1, ..., 15}
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#---------------------------------------------------------------------
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# AND{cond4} Format I
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# Operation: if(cond4) then
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# Rd <- Rx & Ry
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# Syntax: and{cond4} Rd, Rx, Ry
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# 111x xxx1 1101 yyyy 1110 cccc 0010 dddd
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:AND^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;
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eop12_4=0xe & eop4_4=2 & ECOND_8_4 & erd0)
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{
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build ECOND_8_4;
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erd0 = RX9A & RY0A;
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}
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:AND^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;
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eop12_4=0xe & eop4_4=2 & ECOND_8_4 & erd0 & erd0=0xf)
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{
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build ECOND_8_4;
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PC = RX9A & RY0A;
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goto [PC];
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}
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#---------------------------------------------------------------------
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# ANDH, ANDL - Logical AND into high or low half of register
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# I, II, III, IV. d -> {0, 1, ..., 15}
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# imm -> {0, 1, ..., 65535}
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#---------------------------------------------------------------------
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# ANDH Format I
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# Operation: Rd[31:16] <- Rd[31:16] & imm16
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# Syntax: andh Rd, imm
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# 1110 01H0 0001 dddd iiii iiii iiii iiii
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# H == 0
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:ANDH rd0, imm16 is op10_6=0x39 & coh=0 & op4_5=1 & rd0 ; imm16
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{
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value:4 = (imm16 << 16) | 0xffff;
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rd0 = rd0 & value;
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NZSTATUS(rd0);
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}
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:ANDH rd0, imm16 is op10_6=0x39 & coh=0 & op4_5=1 & rd0 & rd0=0xf; imm16
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{
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value:4 = (imm16 << 16) | 0xffff;
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PC = inst_start & value;
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NZSTATUS(PC);
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goto [PC];
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}
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# ANDH Format II
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# Operation: Rd[31:16] <- Rd[31:16] & imm16
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# Rd[15:0] <- 0
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# Syntax: andh Rd, imm, COH
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# 1110 01H0 0001 dddd iiii iiii iiii iiii
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# H == 1
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:ANDH rd0, imm16^", COH" is op10_6=0x39 & coh=1 & op4_5=1 & rd0 ; imm16
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{
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value:4 = imm16 << 16;
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rd0 = rd0 & value;
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NZSTATUS(rd0);
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}
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:ANDH rd0, imm16^", COH" is op10_6=0x39 & coh=1 & op4_5=1 & rd0 & rd0=0xf; imm16
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{
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value:4 = imm16 << 16;
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PC = inst_start & value;
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NZSTATUS(PC);
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goto [PC];
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}
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# ANDL Format III
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# Operation: Rd[15:0] <- Rd[15:0] & imm16
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# Syntax: andl Rd, imm
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# 1110 00H0 0001 dddd iiii iiii iiii iiii
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# H == 0
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:ANDL rd0, imm16 is op10_6=0x38 & coh=0 & op4_5=1 & rd0 ; imm16
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{
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value:4 = imm16 | 0xffff0000;
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rd0 = rd0 & value;
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NZSTATUS(rd0);
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}
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:ANDL rd0, imm16 is op10_6=0x38 & coh=0 & op4_5=1 & rd0 & rd0=0xf ; imm16
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{
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value:4 = imm16 | 0xffff0000;
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PC = inst_start & value;
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NZSTATUS(PC);
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goto [PC];
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}
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# ANDL Format IV
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# Operation: Rd[15:0] <- Rd[15:0] & imm16
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# Rd[31:16] <- 0
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# Syntax: andl Rd, imm, COH
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# 1110 00H0 0001 dddd iiii iiii iiii iiii
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# H == 1
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:ANDL rd0, imm16^", COH" is op10_6=0x38 & coh=1 & op4_5=1 & rd0 ; imm16
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{
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value:4 = imm16;
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rd0 = rd0 & value;
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NZSTATUS(rd0);
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}
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:ANDL rd0, imm16^", COH" is op10_6=0x38 & coh=1 & op4_5=1 & rd0 & rd0=0xf; imm16
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{
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value:4 = imm16;
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PC = inst_start & value;
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NZSTATUS(PC);
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}
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#---------------------------------------------------------------------
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# ANDN - Logical AND NOT
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# I. {d, s} -> {0, 1, ..., 15}
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#---------------------------------------------------------------------
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# ANDN Format I
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# Operation: Rd <- Rd & Rs
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# Syntax: andn Rd, Rs
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# 000s sss0 1000 dddd
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:ANDN rd0, RS9A is op13_3=0 & op4_5=8 & rd0 & RS9A {
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rd0 = rd0 & ~RS9A;
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NZSTATUS(rd0);
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}
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:ANDN rd0, RS9A is op13_3=0 & op4_5=8 & rd0 & RS9A & rd0=0xf {
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PC = inst_start & ~RS9A;
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NZSTATUS(PC);
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goto [PC];
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}
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#---------------------------------------------------------------------
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# COM - One's Compliment
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# I. d -> {0, 1, ..., 15}
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#---------------------------------------------------------------------
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# COM Format I
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# Operation: Rd <- ~Rd
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# Syntax: com Rd
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# 0101 1100 1101 dddd
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:COM rd0 is op4_12=0x5cd & rd0
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{
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rd0 = ~rd0;
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ZSTATUS(rd0);
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}
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#---------------------------------------------------------------------
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# EOR - Logical Exclusive OR with optional logical shift
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# I. {d, s} -> {0, 1, ..., 15}
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# II, III. {d, x, y} -> {0, 1, ..., 15}
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# sa -> {0, 1, ..., 31}
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#---------------------------------------------------------------------
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# EOR Format I
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# Operation: Rd <- Rd & Rs
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# Syntax: eor Rd, Rs
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# 000s sss0 0101 dddd
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:EOR rd0, RS9A is op13_3=0x0 & op4_5=0x5 & rd0 & RS9A {
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rd0 = rd0 ^ RS9A;
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NZSTATUS(rd0);
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}
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:EOR rd0, RS9A is op13_3=0x0 & op4_5=0x5 & rd0 & RS9A & rd0=0xf {
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PC = inst_start ^ RS9A;
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NZSTATUS(PC);
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goto [PC];
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}
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# EOR Format II
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# Operation: Rd <- Rx & Ry << sa5
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# Syntax: eor Rd, Rx, Ry << sa
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# 111x xxx1 1110 yyyy 0010 000t tttt dddd
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:EOR erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=0x10 & erd0 & shift4_5 {
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erd0 = RX9A ^ (RY0A << shift4_5);
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NZSTATUS(erd0);
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}
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:EOR erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=0x10 & erd0 & shift4_5 & erd0=0xf {
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PC = RX9A ^ (RY0A << shift4_5);
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NZSTATUS(PC);
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goto [PC];
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}
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# EOR Format III
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# Operation: Rd <- Rx & Ry >> sa5
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# Syntax: eor Rd, Rx, Ry >> sa
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# 111x xxx1 1110 yyyy 0010 001t tttt dddd
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:EOR erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=0x11 & erd0 & shift4_5 {
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erd0 = RX9A ^ (RY0A >> shift4_5);
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NZSTATUS(erd0);
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}
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:EOR erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=0x11 & erd0 & shift4_5 & erd0=0xf {
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PC = RX9A ^ (RY0A >> shift4_5);
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NZSTATUS(PC);
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goto [PC];
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}
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#---------------------------------------------------------------------
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# EOR{cond4} - Conditional Logical EOR
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# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}
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# {d,x,y} -> {0, 1, ..., 15}
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#---------------------------------------------------------------------
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# EOR{cond4} Format I
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# Operation: if(cond4) then
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# Rd <- Rx ^ Ry
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# Syntax: eor{cond4} Rd, Rx, Ry
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# 111x xxx1 1101 yyyy 1110 cccc 0100 dddd
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:EOR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;
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eop12_4=0xe & eop4_4=4 & ECOND_8_4 & erd0)
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{
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build ECOND_8_4;
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erd0 = RX9A ^ RY0A;
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}
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:EOR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;
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eop12_4=0xe & eop4_4=4 & ECOND_8_4 & erd0 & erd0=0xf)
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{
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build ECOND_8_4;
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PC = RX9A ^ RY0A;
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goto [PC];
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}
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#---------------------------------------------------------------------
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# EORH, EORL - Logical EOR into high or low half of register
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# I, II. d -> {0, 1, ..., 15}
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# imm -> {0, 1, ..., 65535}
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#---------------------------------------------------------------------
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# EORH Format I
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# Operation: Rd[31:16] <- Rd[31:16] & imm16
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# Syntax: eorh Rd, imm
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# 1110 1110 0001 dddd iiii iiii iiii iiii
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:EORH rd0, imm16 is op4_12=0xee1 & rd0 ; imm16
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{
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value:4 = imm16 << 16;
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rd0 = rd0 ^ value;
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NZSTATUS(rd0);
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}
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:EORH rd0, imm16 is op4_12=0xee1 & rd0 & rd0=0xf ; imm16
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{
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value:4 = imm16 << 16;
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PC = inst_start ^ value;
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NZSTATUS(PC);
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goto [PC];
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}
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# EORL Format II
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# Operation: Rd[15:0] <- Rd[15:0] & imm16
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# Syntax: eorl Rd, imm
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# 1110 1100 0001 dddd iiii iiii iiii iiii
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:EORL rd0, imm16 is op4_12=0xec1 & rd0 ; imm16
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{
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value:4 = imm16;
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rd0 = rd0 ^ value;
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NZSTATUS(rd0);
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}
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:EORL rd0, imm16 is op4_12=0xec1 & rd0 & rd0=0xf ; imm16
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{
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value:4 = imm16;
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PC = inst_start ^ value;
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NZSTATUS(PC);
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goto [PC];
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}
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#---------------------------------------------------------------------
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# OR - Logical OR with optional logical shift
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# I. {d, s} -> {0, 1, ..., 15}
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# II, III. {d, x, y} -> {0, 1, ..., 15}
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# sa -> {0, 1, ..., 31}
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#---------------------------------------------------------------------
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# OR Format I
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# Operation: Rd <- Rd & Rs
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# Syntax: or Rd, Rs
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# 000s sss0 0100 dddd
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:OR rd0, RS9A is op13_3=0x0 & op4_5=0x4 & rd0 & RS9A {
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rd0 = rd0 | RS9A;
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NZSTATUS(rd0);
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}
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:OR rd0, RS9A is op13_3=0x0 & op4_5=0x4 & rd0 & RS9A & rd0=0xf {
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PC = inst_start | RS9A;
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NZSTATUS(PC);
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goto [PC];
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}
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# OR Format II
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# Operation: Rd <- Rx & Ry << sa5
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# Syntax: or Rd, Rx, Ry << sa
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# 111x xxx1 1110 yyyy 0001 000t tttt dddd
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:OR erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=8 & erd0 & shift4_5 {
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erd0 = RX9A | (RY0A << shift4_5);
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NZSTATUS(erd0);
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}
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:OR erd0, RX9A, RY0A^" << " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=8 & erd0 & shift4_5 & erd0=0xf {
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PC = RX9A | (RY0A << shift4_5);
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NZSTATUS(PC);
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goto [PC];
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}
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# OR Format III
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# Operation: Rd <- Rx & Ry >> sa5
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# Syntax: or Rd, Rx, Ry >> sa
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# 111x xxx1 1110 yyyy 0001 001t tttt dddd
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:OR erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=9 & erd0 & shift4_5 {
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erd0 = RX9A | (RY0A >> shift4_5);
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NZSTATUS(erd0);
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}
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:OR erd0, RX9A, RY0A^" >> " shift4_5 is op13_3=7 & op4_5=0x1e & RX9A & RY0A;
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eop9_7=9 & erd0 & shift4_5 & erd0=0xf {
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PC = RX9A | (RY0A >> shift4_5);
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NZSTATUS(PC);
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goto [PC];
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}
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#---------------------------------------------------------------------
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# OR{cond4} - Conditional Logical OR
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# I. cond4 -> {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}
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# {d,x,y} -> {0, 1, ..., 15}
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#---------------------------------------------------------------------
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# OR{cond4} Format I
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# Operation: if(cond4) then
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# Rd <- Rx | Ry
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# Syntax: or{cond4} Rd, Rx, Ry
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# 111x xxx1 1101 yyyy 1110 cccc 0011 dddd
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:OR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;
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eop12_4=0xe & eop4_4=3 & ECOND_8_4 & erd0)
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{
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build ECOND_8_4;
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erd0 = RX9A | RY0A;
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}
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:OR^{ECOND_8_4} erd0, RX9A, RY0A is (op13_3=0x7 & op4_5=0x1d & RX9A & RY0A;
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eop12_4=0xe & eop4_4=3 & ECOND_8_4 & erd0 & erd0=0xf)
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{
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build ECOND_8_4;
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PC = RX9A | RY0A;
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goto [PC];
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}
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#---------------------------------------------------------------------
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# ORH, ORL - Logical OR into high or low half of register
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# I, II. d -> {0, 1, ..., 15}
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# imm -> {0, 1, ..., 65535}
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#---------------------------------------------------------------------
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# ORH Format I
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# Operation: Rd[31:16] <- Rd[31:16] | imm16
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# Syntax: orh Rd, imm
|
|
# 1110 1010 0001 dddd iiii iiii iiii iiii
|
|
|
|
:ORH rd0, imm16 is op4_12=0xea1 & rd0 ; imm16
|
|
{
|
|
val:4 = (imm16 << 16);
|
|
rd0 = rd0 | val;
|
|
NZSTATUS(rd0);
|
|
}
|
|
|
|
:ORH rd0, imm16 is op4_12=0xea1 & rd0 & rd0=0xf ; imm16
|
|
{
|
|
val:4 = (imm16 << 16);
|
|
PC = inst_start | val;
|
|
NZSTATUS(PC);
|
|
goto [PC];
|
|
}
|
|
|
|
# ORL Format II
|
|
# Operation: Rd[15:0] <- Rd[15:0] | imm16
|
|
# Syntax: orl Rd, imm
|
|
# 1110 1000 0001 dddd iiii iiii iiii iiii
|
|
|
|
:ORL rd0, imm16 is op4_12=0xe81 & rd0 ; imm16
|
|
{
|
|
val:4 = imm16;
|
|
rd0 = rd0 | val;
|
|
NZSTATUS(rd0);
|
|
}
|
|
|
|
:ORL rd0, imm16 is op4_12=0xe81 & rd0 & rd0=0xf; imm16
|
|
{
|
|
val:4 = imm16;
|
|
PC = inst_start | val;
|
|
NZSTATUS(PC);
|
|
goto [PC];
|
|
}
|
|
|
|
#---------------------------------------------------------------------
|
|
# TST - Test Register
|
|
# I. {d, s} -> {0, 1, ..., 15}
|
|
#---------------------------------------------------------------------
|
|
|
|
# TST Format I
|
|
# Operation: Rd & Rs
|
|
# Syntax: tst Rd, Rs
|
|
# 000s sss0 0111 dddd
|
|
|
|
:TST RD0A, RS9A is op13_3=0x0 & op4_5=0x7 & RD0A & RS9A {
|
|
test:4 = RD0A & RS9A;
|
|
NZSTATUS(test);
|
|
}
|