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111 lines
2.5 KiB
Text
111 lines
2.5 KiB
Text
#---------------------------------------------------------------------
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# 8.3.10 System/Control
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#---------------------------------------------------------------------
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#---------------------------------------------------------------------
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# SR{cond} - Set Register Conditionally
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# I. cond4 -> {eq,ne,hs,lo,ge,lt,mi,pl,ls,gt,le,hi,vs,vc,qs,al}
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# d -> {0, 1, ..., 15}
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#---------------------------------------------------------------------
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# SR{cond} Format I
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# Operation: if (cond4) Rd <- 1; else Rd <- 0;
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# Syntax: SR{cond4} Rd
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# 0101 1111 cccc dddd
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:SR^{COND_4_4} rd0 is op8_8=0x5f & rd0 & COND_4_4 {
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rd0 = 0;
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build COND_4_4;
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rd0 = 1;
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}
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:BREAKPOINT is op0_16=0xd673 {
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trap();
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}
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:CACHE rd0[disp0_11],eop11_5 is op4_12=0xF41 & rd0 ; disp0_11 & eop11_5 {
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tmpa:4 = disp0_11;
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tmpb:4 = eop11_5;
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cacheOp(rd0,tmpa,tmpb);
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}
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:CSRF imm4_5 is op9_7=0x6a & op0_4=0x3 & imm4_5 {
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tmp:4 = 1 << imm4_5;
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SR = SR & ~tmp;
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SRTOFLAGS();
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}
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:CSRFCZ imm4_5 is op9_7=0x68 & imm4_5 & op0_4=0x3 {
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tmp:1 = ((SR >> imm4_5) & 0x1) != 0;
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C = tmp;
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Z = tmp;
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CZTOSR();
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}
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:FRS is op0_16=0xd743 { }
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:MFSR rd0,sysreg is op4_12=0xE1B & rd0 ; eop8_8=0 & sysreg {
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rd0 = sysreg;
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}
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:MTSR sysreg,rs0 is op4_12=0xE3B & rs0 ; eop8_8=0 & sysreg {
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sysreg = rs0;
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}
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:MFDR rd0, dbgreg is op4_12=0xe5b & rd0 ; eop8_8=0x0 & dbgreg {
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tmp:1 = dbgreg;
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MoveFromDebugReg(rd0,tmp);
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}
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:MTDR dbgreg, rs0 is op4_12=0xe7b & rs0 ; eop8_8=0x0 & dbgreg {
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tmp:1 = dbgreg;
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MoveToDebugReg(rs0,tmp);
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}
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:MUSFR rs0 is op4_12=0x5d3 & rs0 {
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SR = (SR & 0xFFFFFFF0) | (rs0 & 0xF);
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SRTOLOWFLAGS();
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}
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:MUSTR rd0 is op4_12=0x5d2 & rd0 {
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rd0 = SR & 0xF;
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}
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:NOP is op0_16=0xD703 {}
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# I found gcc assembler will also use an add r0,r0 for a nop which is an all 0 opcode
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:NOP is op0_16=0 {}
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:PREF rp0[disp_16] is op4_12=0xf21 & rp0 ; disp_16 {
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tmpa:2 = disp_16;
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tmp:4 = rp0 + sext(tmpa);
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CacheFetch(tmp);
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}
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SLGM: val is disp_8 [ val = disp_8 << 0; ] { export *[const]:1 val; }
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SLGM: val is eb7=1 & disp_8 [ val = disp_8 << 0; ] { GM = 0; export *[const]:1 val; }
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:SLEEP SLGM is op0_16=0xe9b0 ; eop8_8=0x0 & SLGM {
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doSleep(SLGM);
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}
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:SSRF imm4_5 is op9_7=0x69 & op0_4=0x3 & imm4_5 {
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tmp:4 = 1 << imm4_5;
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SR = SR | tmp;
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SRTOFLAGS();
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}
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:SYNC eop0_8 is op0_16=0xebb0 ; eop8_8=0x0 & eop0_8 {
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tmp:1 = eop0_8;
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SynchMemory(tmp);
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}
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:TLBR is op0_16=0xd643 {
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ReadTLBEntry();
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}
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:TLBS is op0_16=0xd653 {
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SearchTLBEntry();
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}
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:TLBW is op0_16=0xd663 {
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WriteTLBEntry();
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}
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