mirror of
https://github.com/NationalSecurityAgency/ghidra.git
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133 lines
3.1 KiB
Text
133 lines
3.1 KiB
Text
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@include "Scalar_SPFP.sinc"
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@ifdef IS_ISA
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@include "SPE_APU.sinc"
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@endif
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define pcodeop vectorExclusiveOr;
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define pcodeop vectorMergeHigh;
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define pcodeop vectorMergeLow;
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define pcodeop vectorLoadDoubleWordIntoDoubleWordIndexed;
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define pcodeop vectorStoreDoubleOfDoubleIndexed;
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define pcodeop initializeAccumulator;
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define pcodeop vectorShiftRightWordSigned;
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define pcodeop vectorShiftRightWordUnsigned;
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:evxor vrD_64_0,vrA_64_0,vrB_64_0 is OP=4 & vrD_64_0 & vrA_64_0 & vrB_64_0 & XOP_0_10=534
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{
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vrD_64_0 = vrA_64_0 ^ vrB_64_0;
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}
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@if REGISTER_SIZE=="8"
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:evmergehi S,A,B is OP=4 & S & A & B & XOP_0_10=556
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{
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S[32,32] = A[32,32];
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S[ 0,32] = B[ 0,32];
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}
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:evmergelo S,A,B is OP=4 & S & A & B & XOP_0_10=557
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{
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S[32,32] = A[0,32];
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S[ 0,32] = B[0,32];
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}
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@endif
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:evldd RT,dUI16PlusRAOrZeroAddress is OP=4 & RT & dUI16PlusRAOrZeroAddress & XOP_0_10=769
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{
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ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress;
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RT = *:8 ($(EATRUNC));
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}
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:evlddx RT,RA_OR_ZERO,RB is OP=4 & RT & RA_OR_ZERO & RB & XOP_0_10=768
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;
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RT = *:8 ($(EATRUNC));
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}
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@if REGISTER_SIZE=="8"
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@ifndef IS_ISA
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:evsrws S,A,B is OP=4 & S & A & B & XOP_0_10=545
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{
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local low:4 = A[0,32];
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local high:4 = A[32,32];
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local low_shift:1 = B[0,5];
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local high_shift:1 = B[32,5];
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S[0,32] = low s>> zext(low_shift);
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S[32,32] = high s>> zext(high_shift);
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}
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@endif
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@ifndef IS_ISA
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:evsrwu S,A,B is OP=4 & S & A & B & XOP_0_10=544
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{
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local low:4 = A[0,32];
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local high:4 = A[32,32];
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local low_shift:1 = B[0,5];
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local high_shift:1 = B[32,5];
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S[0,32] = low >> zext(low_shift);
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S[32,32] = high >> zext(high_shift);
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}
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@endif
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@endif
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:evstdd RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=801
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{
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ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress;
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*:8 ($(EATRUNC)) = RS;
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}
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:evstddx RS,RA_OR_ZERO,RB is OP=4 & RS & RA_OR_ZERO & RB & XOP_0_10=800
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;
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*:8 ($(EATRUNC)) = RS;
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}
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:evmra RT,RA is OP=4 & RT & RA & BITS_11_15=0 & XOP_0_10=1220
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{
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ACC = zext(RA);
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RT = RA;
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}
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@if REGISTER_SIZE=="8"
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# evmergehilo rD,rA,rB 010 0010 1110
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:evmergehilo S,A,B is OP=4 & S & A & B & XOP_0_10=558 {
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S[32,32] = A[32,32];
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S[ 0,32] = B[ 0,32];
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}
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# evmergelohi rD,rA,rB 010 0010 1111
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:evmergelohi S,A,B is OP=4 & S & A & B & XOP_0_10=559 {
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S[32,32] = A[ 0,32];
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S[ 0,32] = B[32,32];
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}
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@endif
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# evstwwe rS,rA,UIMM 011 0011 1001
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:evstwwe RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=0x339
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{
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ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress;
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*:4 ($(EATRUNC)) = RS:4;
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}
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# evstwwex rS,rA,rB 011 0011 1000
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:evstwwex RS,RA_OR_ZERO,RB is OP=4 & RS & RA_OR_ZERO & RB & XOP_0_10=0x338
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;
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*:4 ($(EATRUNC)) = RS:4;
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}
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:lvx vrD, RA_OR_ZERO, RB is OP=31 & vrD & RA_OR_ZERO & RB & XOP_1_10=103 & BIT_0=0
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;
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vrD = *:16 ($(EATRUNC));
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}
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:stvx vrS, RA_OR_ZERO, RB is OP=31 & vrS & RA_OR_ZERO & RB & XOP_1_10=231 & BIT_0=0
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;
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*:16 ($(EATRUNC)) = vrS;
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}
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