ghidra/Ghidra/Processors/PowerPC/data/languages/mulhwInstructions.sinc

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#macchw r0,r0,r0 0x10 00 01 58
:macchw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=0
{
D = macchw(D, A, B);
}
#macchw. r0,r0,r0 0x10 00 01 59
:macchw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=172 & Rc=1
{
D = macchw(D, A, B);
cr0flags(D);
}
#macchwo r0,r0,r0 0x10 00 05 58
:macchwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=0
{
D = macchw(D, A, B);
xer_mac_update(D, A, B);
}
#macchwo. r0,r0,r0 0x10 00 05 59
:macchwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=172 & Rc=1
{
D = macchw(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#macchws r0,r0,r0 0x10 00 01 d8
:macchws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=0
{
D = macchws(D, A, B);
}
#macchws. r0,r0,r0 0x10 00 01 d9
:macchws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=236 & Rc=1
{
D = macchws(D, A, B);
cr0flags(D);
}
#macchwso r0,r0,r0 0x10 00 05 d8
:macchwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=0
{
D = macchws(D, A, B);
xer_mac_update(D, A, B);
}
#macchwso. r0,r0,r0 0x10 00 05 d9
:macchwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=236 & Rc=1
{
D = macchws(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#macchwsu r0,r0,r0 0x10 00 01 98
:macchwsu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=0
{
D = macchwsu(D, A, B);
}
#macchwsu. r0,r0,r0 0x10 00 01 99
:macchwsu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=204 & Rc=1
{
D = macchwsu(D, A, B);
cr0flags(D);
}
#macchwsuo r0,r0,r0 0x10 00 05 98
:macchwsuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=0
{
D = macchwsu(D, A, B);
xer_mac_update(D, A, B);
}
#macchwsuo. r0,r0,r0 0x10 00 05 99
:macchwsuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=204 & Rc=1
{
D = macchwsu(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#macchwu r0,r0,r0 0x10 00 01 18
:macchwu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=0
{
D = macchwu(D, A, B);
}
#macchwu. r0,r0,r0 0x10 00 01 19
:macchwu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=140 & Rc=1
{
D = macchwu(D, A, B);
cr0flags(D);
}
#macchwuo r0,r0,r0 0x10 00 05 18
:macchwuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=0
{
D = macchwu(D, A, B);
xer_mac_update(D, A, B);
}
#macchwuo. r0,r0,r0 0x10 00 05 19
:macchwuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=140 & Rc=1
{
D = macchwu(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#machhw r0,r0,r0 0x10 00 00 58
:machhw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=0
{
D = machhw(D, A, B);
}
#machhw. r0,r0,r0 0x10 00 00 59
:machhw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=44 & Rc=1
{
D = machhw(D, A, B);
cr0flags(D);
}
#machhwo r0,r0,r0 0x10 00 04 58
:machhwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=0
{
D = machhw(D, A, B);
xer_mac_update(D, A, B);
}
#machhwo. r0,r0,r0 0x10 00 04 59
:machhwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=44 & Rc=1
{
D = machhw(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#machhws r0,r0,r0 0x10 00 00 d8
:machhws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=0
{
D = machhws(D, A, B);
}
#machhws. r0,r0,r0 0x10 00 00 d9
:machhws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=108 & Rc=1
{
D = machhws(D, A, B);
cr0flags(D);
}
#machhwso r0,r0,r0 0x10 00 04 d8
:machhwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=0
{
D = machhws(D, A, B);
xer_mac_update(D, A, B);
}
#machhwso. r0,r0,r0 0x10 00 04 d9
:machhwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=108 & Rc=1
{
D = machhws(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#machhwsu r0,r0,r0 0x10 00 00 98
:machhwsu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=0
{
D = machhwsu(D, A, B);
}
#machhwsu. r0,r0,r0 0x10 00 00 99
:machhwsu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=76 & Rc=1
{
D = machhwsu(D, A, B);
cr0flags(D);
}
#machhwsuo r0,r0,r0 0x10 00 04 98
:machhwsuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=0
{
D = machhwsu(D, A, B);
xer_mac_update(D, A, B);
}
#machhwsuo. r0,r0,r0 0x10 00 04 99
:machhwsuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=76 & Rc=1
{
D = machhwsu(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#machhwu r0,r0,r0 0x10 00 00 18
:machhwu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=0
{
D = machhwu(D, A, B);
}
#machhwu. r0,r0,r0 0x10 00 00 19
:machhwu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=12 & Rc=1
{
D = machhwu(D, A, B);
cr0flags(D);
}
#machhwuo r0,r0,r0 0x10 00 04 18
:machhwuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=0
{
D = machhwu(D, A, B);
xer_mac_update(D, A, B);
}
#machhwuo. r0,r0,r0 0x10 00 04 19
:machhwuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=12 & Rc=1
{
D = machhwu(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#maclhw r0,r0,r0 0x10 00 03 58
:maclhw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=0
{
D = maclhw(D, A, B);
}
#maclhw. r0,r0,r0 0x10 00 03 59
:maclhw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=428 & Rc=1
{
D = maclhw(D, A, B);
cr0flags(D);
}
#maclhwo r0,r0,r0 0x10 00 07 58
:maclhwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=0
{
D = maclhw(D, A, B);
xer_mac_update(D, A, B);
}
#maclhwo. r0,r0,r0 0x10 00 07 59
:maclhwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=428 & Rc=1
{
D = maclhw(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#maclhws r0,r0,r0 0x10 00 03 d8
:maclhws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=0
{
D = maclhws(D, A, B);
}
#maclhws. r0,r0,r0 0x10 00 03 d9
:maclhws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=492 & Rc=1
{
D = maclhws(D, A, B);
cr0flags(D);
}
#maclhwso r0,r0,r0 0x10 00 07 d8
:maclhwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=0
{
D = maclhws(D, A, B);
xer_mac_update(D, A, B);
}
#maclhwso. r0,r0,r0 0x10 00 07 d9
:maclhwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=492 & Rc=1
{
D = maclhws(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#maclhwsu r0,r0,r0 0x10 00 03 98
:maclhwsu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=0
{
D = maclhwsu(D, A, B);
}
#maclhwsu. r0,r0,r0 0x10 00 03 99
:maclhwsu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=460 & Rc=1
{
D = maclhwsu(D, A, B);
cr0flags(D);
}
#maclhwsuo r0,r0,r0 0x10 00 07 98
:maclhwsuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=0
{
D = maclhwsu(D, A, B);
xer_mac_update(D, A, B);
}
#maclhwsuo. r0,r0,r0 0x10 00 07 99
:maclhwsuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=460 & Rc=1
{
D = maclhwsu(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#maclhwu r0,r0,r0 0x10 00 03 18
:maclhwu D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=0
{
D = maclhwu(D, A, B);
}
#maclhwu. r0,r0,r0 0x10 00 03 19
:maclhwu. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=396 & Rc=1
{
D = maclhwu(D, A, B);
cr0flags(D);
}
#maclhwuo r0,r0,r0 0x10 00 07 18
:maclhwuo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=0
{
D = maclhwu(D, A, B);
xer_mac_update(D, A, B);
}
#maclhwuo. r0,r0,r0 0x10 00 07 19
:maclhwuo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=396 & Rc=1
{
D = maclhwu(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#mulchw r0,r0,r0 0x10 00 01 50
:mulchw D,A,B is OP=4 & D & A & B & XOP_1_10=168 & Rc=0
{
D = mulchw(D, A, B);
}
#mulchw. r0,r0,r0 0x10 00 01 51
:mulchw. D,A,B is OP=4 & D & A & B & XOP_1_10=168 & Rc=1
{
D = mulchw(D, A, B);
cr0flags(D);
}
#mulchwu r0,r0,r0 0x10 00 01 10
:mulchwu D,A,B is OP=4 & D & A & B & XOP_1_10=136 & Rc=0
{
D = mulchwu(D, A, B);
}
#mulchwu. r0,r0,r0 0x10 00 01 11
:mulchwu. D,A,B is OP=4 & D & A & B & XOP_1_10=136 & Rc=1
{
D = mulchwu(D, A, B);
cr0flags(D);
}
#mulhhw r0,r0,r0 0x10 00 00 50
:mulhhw D,A,B is OP=4 & D & A & B & XOP_1_10=40 & Rc=0
{
D = mulhhw(D, A, B);
}
#mulhhw. r0,r0,r0 0x10 00 00 51
:mulhhw. D,A,B is OP=4 & D & A & B & XOP_1_10=40 & Rc=1
{
D = mulhhw(D, A, B);
cr0flags(D);
}
#mulhhwu r0,r0,r0 0x10 00 00 10
:mulhhwu D,A,B is OP=4 & D & A & B & XOP_1_10=8 & Rc=0
{
D = mulhhwu(D, A, B);
}
#mulhhwu. r0,r0,r0 0x10 00 00 11
:mulhhwu. D,A,B is OP=4 & D & A & B & XOP_1_10=8 & Rc=1
{
D = mulhhwu(D, A, B);
cr0flags(D);
}
#mullhw r0,r0,r0 0x10 00 03 50
:mullhw D,A,B is OP=4 & D & A & B & XOP_1_10=424 & Rc=0
{
D = mullhw(D, A, B);
}
#mullhw. r0,r0,r0 0x10 00 03 51
:mullhw. D,A,B is OP=4 & D & A & B & XOP_1_10=424 & Rc=1
{
D = mullhw(D, A, B);
cr0flags(D);
}
# mulhwu r0,r0,r0 0x10 00 03 10
:mullhwu D,A,B is OP=4 & D & A & B & XOP_1_10=392 & Rc=0
{
D = mullhwu(D, A, B);
}
#mullhwu. r0,r0,r0 0x10 00 03 11
:mullhwu. D,A,B is OP=4 & D & A & B & XOP_1_10=392 & Rc=1
{
D = mullhwu(D, A, B);
cr0flags(D);
}
#nmacchw r0,r0,r0 0x10 00 01 5c
:nmacchw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=0
{
D = nmacchw(D, A, B);
}
#nmacchw. r0,r0,r0 0x10 00 01 5d
:nmacchw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=174 & Rc=1
{
D = nmacchw(D, A, B);
cr0flags(D);
}
#nmacchwo r0,r0,r0 0x10 00 05 5c
:nmacchwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=0
{
D = nmacchw(D, A, B);
xer_mac_update(D, A, B);
}
#nmacchwo. r0,r0,r0 0x10 00 05 5d
:nmacchwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=174 & Rc=1
{
D = nmacchw(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#nmacchws r0,r0,r0 0x10 00 01 dc
:nmacchws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=0
{
D = nmacchws(D, A, B);
}
#nmacchws. r0,r0,r0 0x10 00 01 dd
:nmacchws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=238 & Rc=1
{
D = nmacchws(D, A, B);
cr0flags(D);
}
#nmacchwso r0,r0,r0 0x10 00 05 dc
:nmacchwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=0
{
D = nmacchws(D, A, B);
xer_mac_update(D, A, B);
}
#nmacchwso. r0,r0,r0 0x10 00 05 dd
:nmacchwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=238 & Rc=1
{
D = nmacchws(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#nmachhw r0,r0,r0 0x10 00 00 5c
:nmachhw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=0
{
D = nmachhw(D, A, B);
}
#nmachhw. r0,r0,r0 0x10 00 00 5d
:nmachhw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=46 & Rc=1
{
D = nmachhw(D, A, B);
cr0flags(D);
}
#nmachhwo r0,r0,r0 0x10 00 04 5c
:nmachhwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=0
{
D = nmachhw(D, A, B);
xer_mac_update(D, A, B);
}
#nmachhwo. r0,r0,r0 0x10 00 04 5d
:nmachhwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=46 & Rc=1
{
D = nmachhw(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#nmachhws r0,r0,r0 0x10 00 00 dc
:nmachhws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=0
{
D = nmachhws(D, A, B);
}
#nmachhws. r0,r0,r0 0x10 00 00 dd
:nmachhws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=110 & Rc=1
{
D = nmachhws(D, A, B);
cr0flags(D);
}
#nmachhwso r0,r0,r0 0x10 00 04 dc
:nmachhwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=0
{
D = nmachhws(D, A, B);
xer_mac_update(D, A, B);
}
#nmachhwso. r0,r0,r0 0x10 00 04 dd
:nmachhwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=110 & Rc=1
{
D = nmachhws(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#nmaclhw r0,r0,r0 0x10 00 03 5c
:nmaclhw D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=0
{
D = nmaclhw(D, A, B);
}
#nmaclhw. r0,r0,r0 0x10 00 03 5d
:nmaclhw. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=430 & Rc=1
{
D = nmaclhw(D, A, B);
cr0flags(D);
}
#nmaclhwo r0,r0,r0 0x10 00 07 5c
:nmaclhwo D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=0
{
D = nmaclhw(D, A, B);
xer_mac_update(D, A, B);
}
#nmaclhwo. r0,r0,r0 0x10 00 07 5d
:nmaclhwo. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=430 & Rc=1
{
D = nmaclhw(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}
#nmaclhws r0,r0,r0 0x10 00 03 dc
:nmaclhws D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=0
{
D = nmaclhws(D, A, B);
}
#nmaclhws. r0,r0,r0 0x10 00 03 dd
:nmaclhws. D,A,B is OP=4 & D & A & B & OE=0 & XOP_1_9=494 & Rc=1
{
D = nmaclhws(D, A, B);
cr0flags(D);
}
#nmaclhwso r0,r0,r0 0x10 00 07 dc
:nmaclhwso D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=0
{
D = nmaclhws(D, A, B);
xer_mac_update(D, A, B);
}
#nmaclhwso. r0,r0,r0 0x10 00 07 dd
:nmaclhwso. D,A,B is OP=4 & D & A & B & OE=1 & XOP_1_9=494 & Rc=1
{
D = nmaclhws(D, A, B);
xer_mac_update(D, A, B);
cr0flags(D);
}