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https://github.com/NationalSecurityAgency/ghidra.git
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122 lines
3.5 KiB
Text
122 lines
3.5 KiB
Text
# These instructions show up in the Freescale PowerQUICC III instruction manual
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# (not present elsewhere)
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define pcodeop dataCacheBlockClearLock;
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define pcodeop prefetchDataCacheBlockLockSet;
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define pcodeop prefetchDataCacheBlockLockSetX;
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define pcodeop debuggerNotifyHalt;
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define pcodeop instructionCacheBlockClearLock;
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define pcodeop queryInstructionCacheBlockLock;
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define pcodeop prefetchInstructionCacheBlockLockSetX;
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define pcodeop moveFromAPIDIndirect;
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define pcodeop moveFromPerformanceMonitorRegister;
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define pcodeop moveToPerformanceMonitorRegister;
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define pcodeop invalidateTLB;
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#dcblc 0,0,r0 #FIXME
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:dcblc CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=390 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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dataCacheBlockClearLock(ea);
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}
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#dcbtls 0,0,r0 #FIXME
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:dcbtls CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=166 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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prefetchDataCacheBlockLockSet(ea);
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}
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#dcbtstls 0,0,r0 #FIXME
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:dcbtstls CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=134 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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prefetchDataCacheBlockLockSetX(ea);
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}
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#dnh 0,0 #FIXME
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:dnh DUI,DUIS is $(NOTVLE) & OP=19 & DUI & DUIS & XOP_1_10=198 & BIT_0=0
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{
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debuggerNotifyHalt(DUI:1,DUIS:2);
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}
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#icblc 0,0,r0 #FIXME
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:icblc CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=230 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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instructionCacheBlockClearLock(CT:1,ea);
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}
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:icblq CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=198 & BIT_0=1 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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cr0 = queryInstructionCacheBlockLock(CT:1,ea);
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}
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#icbtls 0,0,r0 #FIXME
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:icbtls CT,RA_OR_ZERO,B is OP=31 & CT & B & XOP_1_10=486 & BIT_0=0 & RA_OR_ZERO
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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prefetchInstructionCacheBlockLockSetX(ea);
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}
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:isel^CC_X_OPm D,RA_OR_ZERO,B,CC_X_OP is OP=31 & D & RA_OR_ZERO & B & CC_X_OP & CC_X_OPm & XOP_1_5=15
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{
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local tmp:$(REGISTER_SIZE) = RA_OR_ZERO;
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D = B;
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if (!CC_X_OP) goto inst_next;
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D = tmp;
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# D = (zext(CC_X_OP) * RA_OR_ZERO) + (zext(!CC_X_OP) * B);
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}
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#mfapidi r0,r1 #FIXME
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:mfapidi D,A is $(NOTVLE) & OP=31 & D & A & XOP_1_10=275
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{
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D = moveFromAPIDIndirect(A);
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}
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pmrn: pmr is BITS_16_20 & BITS_11_15 [ pmr = BITS_11_15 << 5 | BITS_16_20; ] { tmp:2 = pmr; export tmp; }
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#mfpmr r0,? #FIXME
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:mfpmr D,pmrn is OP=31 & D & pmrn & XOP_1_10=334 & BIT_0=0
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{
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D = moveFromPerformanceMonitorRegister(pmrn);
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}
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#mtpmr r0,? #FIXME
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:mtpmr pmrn,S is OP=31 & S & pmrn & XOP_1_10=462 & BIT_0=0
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{
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moveToPerformanceMonitorRegister(pmrn, S);
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}
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#rfdi #FIXME
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:rfdi is $(NOTVLE) & OP=19 & XOP_1_10=39
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{
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MSR = returnFromDebugInterrupt(MSR, spr23f); #DSRR1
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local ra = spr23e; #DSRR0
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return[ra];
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}
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#rfmci #FIXME
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:rfmci is $(NOTVLE) & OP=19 & XOP_0_10=76
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{
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MSR = returnFromMachineCheckInterrupt(MSR, spr23b); #MCSRR1
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local ra = spr23a; #MCSRR0
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return[ra];
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}
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# PowerISA II: 6.11.4.9 TLB Management Instructions
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# CMT: TLB Invalidate Local Indexed [Category: Embedded.Phased In]]
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# FORM: X-form
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define pcodeop TLBInvalidateLocalIndexed; # Outputs/affect TBD
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:tlbilx BITS_21_22,RA_OR_ZERO,RB_OR_ZERO is $(NOTVLE) & OP=31 & CRFD=0 & BITS_21_22 & RA_OR_ZERO & RB_OR_ZERO & XOP_1_10=18 & BIT_0=0 {
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TLBInvalidateLocalIndexed(BITS_21_22:1,RA_OR_ZERO,RB_OR_ZERO);
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}
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#tlbivax 0,r0 #FIXME
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:tlbivax RA_OR_ZERO,B is OP=31 & RA_OR_ZERO & B & XOP_1_10=786
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{
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ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
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invalidateTLB(ea);
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}
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