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https://github.com/NationalSecurityAgency/ghidra.git
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234 lines
11 KiB
Text
234 lines
11 KiB
Text
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109785
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define pcodeop vinserti128 ;
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:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0 {
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local tmp:16 = XmmReg2_m128;
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local cond0:16 = zext((imm8_0:1 & 0x1) == 0);
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local cond1:16 = zext((imm8_0:1 & 0x1) == 1);
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# ignoring all but the least significant bit
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YmmReg1[0,128] = (cond0 * tmp) + (cond1 * vexVVVV_YmmReg[0,128]);
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YmmReg1[128,128] = (cond0 * vexVVVV_YmmReg[128,128]) + (cond1 * tmp);
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}
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# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106903
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define pcodeop vgatherdpd ;
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:VGATHERDPD XmmReg1, q_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x92; (XmmReg1 & ZmmReg1) ... & q_vm32x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vgatherdpd(XmmReg1, q_vm32x, vexVVVV_XmmReg);
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local tmp:16 = vgatherdpd(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106908
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@ifdef IA64
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define pcodeop vgatherqpd ;
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:VGATHERQPD XmmReg1, q_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & ZmmReg1) ... & q_vm64x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vgatherqpd(XmmReg1, q_vm64x, vexVVVV_XmmReg);
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local tmp:16 = vgatherqpd(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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@endif
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# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106913
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:VGATHERDPD YmmReg1, q_vm32x, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x92; (YmmReg1 & ZmmReg1) ... & q_vm32x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# YmmReg1 = vgatherdpd(YmmReg1, q_vm32x, vexVVVV_YmmReg);
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YmmReg1 = vgatherdpd(YmmReg1, vexVVVV_YmmReg);
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ZmmReg1 = zext(YmmReg1);
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vexVVVV_YmmReg = 0;
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}
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# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106918
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@ifdef IA64
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:VGATHERQPD YmmReg1, q_vm64y, vexVVVV_YmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x93; (YmmReg1 & ZmmReg1) ... & q_vm64y {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# YmmReg1 = vgatherqpd(YmmReg1, q_vm64y, vexVVVV_YmmReg);
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YmmReg1 = vgatherqpd(YmmReg1, vexVVVV_YmmReg);
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ZmmReg1 = zext(YmmReg1);
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vexVVVV_YmmReg = 0;
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}
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@endif
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# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107130
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define pcodeop vgatherdps ;
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:VGATHERDPS XmmReg1, d_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x92; (XmmReg1 & ZmmReg1) ... & d_vm32x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vgatherdps(XmmReg1, d_vm32x, vexVVVV_XmmReg);
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local tmp:16 = vgatherdps(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107135
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@ifdef IA64
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define pcodeop vgatherqps ;
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:VGATHERQPS XmmReg1, d_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & ZmmReg1) ... & d_vm64x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vgatherqps(XmmReg1, d_vm64x, vexVVVV_XmmReg);
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local tmp:16 = vgatherqps(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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@endif
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# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107140
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:VGATHERDPS YmmReg1, d_vm32y, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x92; (YmmReg1 & ZmmReg1) ... & d_vm32y {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# YmmReg1 = vgatherdps(YmmReg1, d_vm32y, vexVVVV_YmmReg);
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YmmReg1 = vgatherdps(YmmReg1, vexVVVV_YmmReg);
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ZmmReg1 = zext(YmmReg1);
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vexVVVV_YmmReg = 0;
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}
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# VGATHERDPS/VGATHERQPS 5-256 PAGE 2080 LINE 107145
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@ifdef IA64
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:VGATHERQPS XmmReg1, d_vm64y, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x93; (XmmReg1 & ZmmReg1) ... & d_vm64y {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vgatherqps(XmmReg1, d_vm64y, vexVVVV_XmmReg);
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XmmReg1 = vgatherqps(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(XmmReg1);
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vexVVVV_XmmReg = 0;
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}
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@endif
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# PCMPEQQ 4-250 PAGE 1370 LINE 71171
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:VPCMPEQQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x29; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local mask:8 = 0xffffffffffffffff;
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YmmReg1[0,64] = zext(vexVVVV_YmmReg[0,64] == YmmReg2_m256[0,64]) * mask;
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YmmReg1[64,64] = zext(vexVVVV_YmmReg[64,64] == YmmReg2_m256[64,64]) * mask;
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YmmReg1[128,64] = zext(vexVVVV_YmmReg[128,64] == YmmReg2_m256[128,64]) * mask;
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YmmReg1[192,64] = zext(vexVVVV_YmmReg[192,64] == YmmReg2_m256[192,64]) * mask;
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ZmmReg1 = zext(YmmReg1);
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}
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# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107884
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define pcodeop vpgatherdd ;
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:VPGATHERDD XmmReg1, d_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x90; (XmmReg1 & ZmmReg1) ... & d_vm32x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vpgatherdd(XmmReg1, d_vm32x, vexVVVV_XmmReg);
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local tmp:16 = vpgatherdd(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107888
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@ifdef IA64
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define pcodeop vpgatherqd ;
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:VPGATHERQD XmmReg1, d_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & ZmmReg1) ... & d_vm64x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vpgatherqd(XmmReg1, d_vm64x, vexVVVV_XmmReg);
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local tmp:16 = vpgatherqd(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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@endif
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# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107892
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:VPGATHERDD YmmReg1, d_vm32y, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x90; (YmmReg1 & ZmmReg1) ... & d_vm32y {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# YmmReg1 = vpgatherdd(YmmReg1, d_vm32y, vexVVVV_YmmReg);
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YmmReg1 = vpgatherdd(YmmReg1, vexVVVV_YmmReg);
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ZmmReg1 = zext(YmmReg1);
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vexVVVV_YmmReg = 0;
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}
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# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107896
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@ifdef IA64
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:VPGATHERQD XmmReg1, d_vm64y, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & ZmmReg1) ... & d_vm64y {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vpgatherqd(XmmReg1, d_vm64y, vexVVVV_XmmReg);
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local tmp:16 = vpgatherqd(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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@endif
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# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108234
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define pcodeop vpgatherdq ;
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:VPGATHERDQ XmmReg1, q_vm32x, vexVVVV_XmmReg is $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x90; (XmmReg1 & ZmmReg1) ... & q_vm32x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vpgatherdq(XmmReg1, q_vm32x, vexVVVV_XmmReg);
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local tmp:16 = vpgatherdq(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108238
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@ifdef IA64
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define pcodeop vpgatherqq ;
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:VPGATHERQQ XmmReg1, q_vm64x, vexVVVV_XmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x91; (XmmReg1 & ZmmReg1) ... & q_vm64x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# XmmReg1 = vpgatherqq(XmmReg1, q_vm64x, vexVVVV_XmmReg);
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local tmp:16 = vpgatherqq(XmmReg1, vexVVVV_XmmReg);
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ZmmReg1 = zext(tmp);
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vexVVVV_XmmReg = 0;
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}
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@endif
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# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108242
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:VPGATHERDQ YmmReg1, q_vm32x, vexVVVV_YmmReg is $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x90; (YmmReg1 & ZmmReg1) ... & q_vm32x {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# YmmReg1 = vpgatherdq(YmmReg1, q_vm32x, vexVVVV_YmmReg);
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YmmReg1 = vpgatherdq(YmmReg1, vexVVVV_YmmReg);
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ZmmReg1 = zext(YmmReg1);
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vexVVVV_YmmReg = 0;
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}
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# VPGATHERDQ/VPGATHERQQ 5-280 PAGE 2104 LINE 108246
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@ifdef IA64
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:VPGATHERQQ YmmReg1, q_vm64y, vexVVVV_YmmReg is $(LONGMODE_ON) & $(VEX_DDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x91; (YmmReg1 & ZmmReg1) ... & q_vm64y {
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# TODO full semantics necessary for VSIB memory data access, leave out of data flow for now
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# YmmReg1 = vpgatherqq(YmmReg1, q_vm64y, vexVVVV_YmmReg);
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YmmReg1 = vpgatherqq(YmmReg1, vexVVVV_YmmReg);
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ZmmReg1 = zext(YmmReg1);
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vexVVVV_YmmReg = 0;
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}
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@endif
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# PMOVMSKB 4-338 PAGE 1458 LINE 75655
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:VPMOVMSKB Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & YmmReg2) & check_Reg32_dest
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{
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local byte_mask:4 = 0:4;
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byte_mask[0,1] = YmmReg2[7,1];
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byte_mask[1,1] = YmmReg2[15,1];
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byte_mask[2,1] = YmmReg2[23,1];
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byte_mask[3,1] = YmmReg2[31,1];
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byte_mask[4,1] = YmmReg2[39,1];
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byte_mask[5,1] = YmmReg2[47,1];
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byte_mask[6,1] = YmmReg2[55,1];
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byte_mask[7,1] = YmmReg2[63,1];
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byte_mask[8,1] = YmmReg2[71,1];
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byte_mask[9,1] = YmmReg2[79,1];
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byte_mask[10,1] = YmmReg2[87,1];
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byte_mask[11,1] = YmmReg2[95,1];
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byte_mask[12,1] = YmmReg2[103,1];
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byte_mask[13,1] = YmmReg2[111,1];
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byte_mask[14,1] = YmmReg2[119,1];
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byte_mask[15,1] = YmmReg2[127,1];
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byte_mask[16,1] = YmmReg2[135,1];
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byte_mask[17,1] = YmmReg2[143,1];
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byte_mask[18,1] = YmmReg2[151,1];
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byte_mask[19,1] = YmmReg2[159,1];
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byte_mask[20,1] = YmmReg2[167,1];
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byte_mask[21,1] = YmmReg2[175,1];
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byte_mask[22,1] = YmmReg2[183,1];
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byte_mask[23,1] = YmmReg2[191,1];
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byte_mask[24,1] = YmmReg2[199,1];
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byte_mask[25,1] = YmmReg2[207,1];
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byte_mask[26,1] = YmmReg2[215,1];
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byte_mask[27,1] = YmmReg2[223,1];
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byte_mask[28,1] = YmmReg2[231,1];
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byte_mask[29,1] = YmmReg2[239,1];
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byte_mask[30,1] = YmmReg2[247,1];
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byte_mask[31,1] = YmmReg2[255,1];
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Reg32 = zext(byte_mask);
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build check_Reg32_dest;
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}
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